Differential drivers may be used in electronic circuits to drive a differential electrical signal across a transmission line to a receiver. A typical differential driver includes a constant current supply generated by a field effect transistor operating in the saturation region. However, as modern integrated circuits are becoming increasingly miniaturized, the supply voltages are continuing to drop. It is therefore difficult to keep field effect transistors in a differential driver operating in the saturation region without reducing the output swing from the differential driver to undesirably small levels.
An exemplary differential driver includes first and second switches connected in parallel to a current source, with a pair of differential inputs connected to control inputs on the first and second switches, and first and second output drivers connected to the first and second switches through current mirrors.
Illustrative embodiments are shown in the accompanying drawings as described below.
The drawings and description, in general, disclose a differential driver circuit for driving a differential signal on a transmission line. A current source is provided in the differential driver outside of the output drivers, such as in the pre-driver, so that it does not reduce the output swing of the output drivers. Placing the current source outside the output drivers rather than inline in the output drivers also removes the parasitic capacitive loading of the current source from the output drivers, effectively improving the signal edge rate and driver return-loss characteristics.
A first exemplary embodiment of a differential driver 10 is illustrated in
A bias voltage vbiasp 50 is applied to the gate of the current source FET 12, and a voltage supply VDD 52 is applied to the source of the current source FET 12. As discussed above, the current source FET 12 is operated in the saturation region in order to provide a constant current. The term “saturation” refers herein to an operating region in which for a PFET, Vds<Vgs−Vth, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. For example, consider the case in which VDD 52 is 1.2 volts, the threshold voltage Vth for the current source FET 12 is −0.25 volts, and the drain voltage is 0.9 volts. Vds is therefore 0.9−1.2 or −0.3 volts, so the equation above is −0.3v<Vgs−(−0.25v) so Vgs should be greater than −0.55 volts. Therefore, Vbiasp −1.2v>−0.55v so Vbiasp should be greater than 0.65 volts.
The steering switches 14 and 16 may each comprise a PFET, having the sources both connected to the drain of the current source FET 12. A first differential input in_p 20 is connected to the gate of one of the steering FETS 14, and a second differential input in_n 22 is connected to the gate of the other steering FET 16.
The exemplary current mirrors 24 and 26 each comprise a pair of n-channel field effect transistors (NFETS) operating in the saturation region. Referring now to the first current mirror 24, the reference FET 54 is forced into the saturation region and is operated as a diode by connecting the drain and gate. The reference FET 54 carries the tail current as a reference current. The gate of the reference FET 54 is also connected to the gate of the output FET 42, ensuring identical control voltages Vgs at the gates of the current mirror FETS 54 and 42. The identical control voltages cause the tail current through the reference FET 54 to be mirrored to the output FET 42, with identical current levels if the reference and output FETS 54 and 42 are physically matched. Alternatively, the current through the output FET 42 may be mirrored at other desired fixed ratios by altering the dimensions of the reference and output FETS 54 and 42. The sources of the reference and output FETS 54 and 42 are connected to a ground 56. The first current mirror 24 is connected to the first steering switch 14 by connecting the drain of the reference FET 54 to the drain of the steering FET 14.
The second current mirror operates in the same fashion and includes a reference FET 60 and an output FET 44. The gate and drain of the reference FET 60 are connected to the gate of the output FET 44. The sources of the reference and output FETS 60 and 44 are connected to a ground 56. The second current mirror 26 is connected to the second steering switch 16 by connecting the drain of the reference FET 60 to the drain of the steering FET 16.
The output drivers 30 and 32 each comprise a resistor 62 and 64 connected to a termination voltage source VT 40. The output driver resistors 62 and 64 provide resistive loads to match the impedance of an external transmission line. The impedance or resistance of the output driver resistors 62 and 64 is selected to reduce signal reflection on the transmission line. The output drivers 30 and 32 are connected to the current mirrors 24 and 26 so that the mirrored tail current is pulled through the output drivers 30 and 32. For example, a first end of the resistor 62 in the first output driver 30 is connected to the termination voltage VT 40, and a second end of the resistor 62 is connected to the drain of the output FET 42 in the first current mirror 24. The first differential output out_p 34 is connected to the second end of the resistor 62 and the drain of the output FET 42 in the first current mirror 24. Similarly, the first end of the resistor 64 in the second output driver 32 is connected to the termination voltage VT 40, and a second end of the resistor 64 is connected to the drain of the output FET 44 in the second current mirror 26. The second differential output out_n 36 is connected to the second end of the resistor 64 and the drain of the output FET 44 in the second current mirror 26.
Note that in the exemplary embodiment, the supply voltage VDD 52 and the termination voltage VT 40 are set at the same voltage level, such as 1.2 volts. However, the supply voltage VDD 52 and the termination voltage VT 40 may be set at different voltage levels.
In the exemplary embodiment illustrated in
Another exemplary embodiment 70 is illustrated in
A bias voltage vbiasn 110 is applied to the gate of the current source FET 80, and the source of the current source FET 80 is grounded. As discussed above, the current source FET 80 is operated in the saturation region in order to provide a constant current. The steering switches 82 and 84 are connected to the current source FET 80 to direct the tail current to one side or the other of the differential driver 70 according to the differential inputs 86 and 90. In this exemplary embodiment, the steering switches 82 and 84 each comprise an NFET, having the sources both connected to the drain of the current source FET 80. The first differential input in_p 86 is connected to the gate of one of the steering FETS 82, and a second differential input in_n 90 is connected to the gate of the other steering FET 84.
The exemplary current mirrors 92 and 94 each comprise a pair of PFETS operating in the saturation region, wherein the drain and gate of the reference FETS 110 and 112 are connected to the gate of the associated output FETS 104 and 106. The sources of the reference and output FETS 110, 112, 104 and 106 in both current mirrors 92 and 94 are connected to the voltage supply VDD 102. The drains of the reference FETS 110 and 112 are connected to the drains of the steering FETS 82 and 84. The current mirrors operate as described above with respect to
The output drivers 96 and 100 each comprise a resistor 114 and 116 connected to a ground 76. The output driver resistors 114 and 116 provide resistive loads to match the impedance of an external transmission line. The impedance or resistance of the output driver resistors 114 and 116 is selected to reduce signal reflection on the transmission line. The output drivers 114 and 116 are connected to the current mirrors 92 and 94 so that the mirrored tail current is pulled through the output drivers 96 and 100. For example, a first end of the resistor 114 in the first output driver 96 is connected to ground 76, and a second end of the resistor 114 is connected to the drain of the output FET 104 in the first current mirror 92. The first differential output out_p 72 is connected to the second end of the resistor 114 and the drain of the output FET 104 in the first current mirror 92. Similarly, the first end of the resistor 116 in the second output driver 100 is connected to ground 76, and a second end of the resistor 116 is connected to the drain of the output FET 106 in the second current mirror 94. The second differential output out_n 74 is connected to the second end of the resistor 116 and the drain of the output FET 106 in the second current mirror 94.
In the exemplary embodiment illustrated in
In an alternative embodiment, the pre-driver portions of the exemplary circuits 10 and 70 illustrated in
The differential driver (e.g., 10, 70) may be connected to a receiver in any suitable manner desired, such as direct-current (DC) coupling as illustrated in
An exemplary operation for driving a differential signal on a transmission line is illustrated in the flowchart of
While illustrative embodiments have been described in detail herein, it is to be understood that the concepts disclosed herein may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art.