IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986. |
BiCMOS Circuit Technology for a High-Speed SRAM; Takakuni Douseki et al, IEEE Journal of Solid State Circuits, vol. 23, No. 1, Feb. 1988. |
A 9100 Gate ECL/TTL Compatible BiCMOs Gate Garray; Lin et al. |
13-ns, 500-mW, 64-kbit ECL RAM Using Hi-BICMOS Technology, Ogiue et al, IEEE Jour. of Solid State, vol. SC-21, No. 5, Oct. 1986. |
High Performance BIMOS Gate Arrays with Embedded Configurable Static Memory Bennett et al, 1987 IEEE. |
Perspective on BiCMOS VLSI's, Kubo et al, IEEE Jour. of Solid State, vol. 23, No. 1, Feb. 1988. |
A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic; Chu et al, IEEE Jour. of Solid-States, vol. Sc 22, No. 4, Aug. 1987. |
Implementation of Iterative Networks with CMOS Differential Logic; Shih-Lien IEEE Journal of Solid-State Circuits, vol. 23, No. 4, Aug. 1988. |
0.45 ns 7K Hi-BiCMOs Gate Array with Configurable 3-Port 4.6 K SRAM Nishio et al, Hitachi Research Laboratory IEEE 1987 Custom Integrated Circuits. |
A 4-ns 4K.times.1-bit Two-Port BiCMOS SRAM, Yang et al, IEEE Journal of Solid State Circuits, vol. 23, No. 5 Oct. 1988. |
A 12-ns ECL I/O 256 K.times.1-bit SRAM Using a 1-um BiCMOS Technology Kertis et al, IEEE Journal of Solid State Circuit, vol. 23, No. 5, Oct. 1988. |
High Speed Sram's Suzuki et al, 1989 IEEE International Solid State Circuits Conference. |
WAM 2.6 An 8ns BiCMOS 1 Mb ECL SRAM with a Configurable Memory Array Size 1989 IEEE International Solid State Circuits Conference Feb. 15, 1989. |
WAM 2.7 An 8ns 1 Mb ECL BiCMOS Sram, 1989 IEEE International Solid State Circuits Conference, Feb. 15, 1989. |