Patent Application
20130279548
The present invention relates generally to wireless communications, and more particularly, some embodiments relate to a differential binary phase shift keying modulation scheme.
With the many continued advancements in communications technology, more and more devices are being introduced in both the consumer and commercial sectors with advanced communications capabilities. Additionally, advances in processing power and low-power consumption technologies, as well as advances in data coding techniques have led to the proliferation of wired and wireless communications capabilities on a more widespread basis.
Implantable medical devices now routinely include wireless communications capabilities to allow, for example, wireless transmission of telemetry, such as patient or device data, from the device to a monitoring facility. Likewise command and control information can be wirelessly delivered to the medical device to control the device. This allows one- or two way communications without using wires or leads.
A wireless system for implantable medical device(s) typically includes at least one implanted medical device (IMD) and an external communication device (ECD). The IMD (for example, an ICD, glucose monitor) is typically tasked with monitoring and treating physiological conditions within the human body. The ECD can be a device that is capable of communicating both with the implant and with a second device, such as a remote monitoring station, perhaps using a different wireless system.
The combination of transmit and receive functions defines a transceiver. With many wireless devises, including IMDs, power consumption is an important parameter and system designers often want to keep the power consumption of the implantable device as low as possible. This includes, but is not limited to, the design of the communication link, the RF and analog front-end (AFE) design, component modules (e.g., use of slicer, or a 1-bit ADC, instead of multi-bit ADC) and features, and the efficient use of sleep mode(s) that reduce, as much as possible, the time when at least the radio of the implantable device is active.
In the design of the communication link for IMDs and other wireless devices, one of the factors to be considered is digital baseband processing required for the modulation and demodulation of the chosen digital modulation scheme. Phase-shift keying (PSK) is a digital modulation scheme in which data is communicated by modulating the phase of the carrier signal. With PSK, patterns of binary data are represented using a finite number of phases. Each bit pattern is represented by a symbol that is manifested in its particular phase. At the receiver, the demodulator determines the phase of the received signal and maps it to the symbol it represents, thus recovering the modulated data. To do this, the receiver compares the phase of the received signal to a set of valid modulator phases from a PSK constellation.
An alternative form of PSK is referred to as differential phase-shift keying (DPSK), where the symbols at the modulator's input are mapped to phase shifts, rather than absolute phases. In this system, the demodulator determines the changes in the phase of the received signal. With DPSK, the demodulator compares the phase of a given received symbol with that of the previously received symbol. One of the advantages of DPSK is that the demodulation can typically be done without the estimation of carrier phase at the receiver and this reduces the computational complexity and simplifies the receiver.
In digital communications, a modulator maps information symbols to a finite set of channel alphabet symbols represented as a set of constellation points, also referred as a modulator constellation represented by a constellation diagram. A modulator can be referred to as a constellation mapper. A constellation diagram illustrates the constellation points in a complex plane in which the real and imaginary axes are referred to as the in-phase and in-quadrature phase axes respectively. In conventional DPSK modulation, the modulator uses a PSK constellation of size equal to 2b, where b is the number of (coded) information bits to be mapped to a channel alphabet symbol (or letter) during one use of the modulator (i.e., the size of the finite alphabet at the modulator's input). In variations on DPSK modulation, e.g. π/2-DBPSK, the PSK constellation used by the DPSK modulator has size larger than 2b (i.e., 4>21 points in the mentioned case). PSK constellation points are usually chosen with uniform angular spacing around a circle, providing maximum phase-separation between adjacent points. The constellation points are typically positioned on a circle so that they can all be transmitted using the same level of energy.
In conventional differential binary PSK modulation (DBPSK), ‘0’ is transmitted by change of 0 degrees and ‘1’ is transmitted by change of 180 degrees (or π radians) in the transmitted symbol. One variation of DBPSK that is also widely used is π/2-DBPSK where the change in angle is +90 degrees (+π/2 radians) for transmission of ‘0’ and −90 degrees (either −π/2 or 3π/2 radians) for the transmission of ‘1’. An alternative interpretation for π/2-DBPSK is that a constant +π/2 radians is added to the symbol angle for every bit modulated according to conventional DBPSK. This is also the modulation adopted in the IEEE BAN draft standard.
According to various embodiments of the invention a variation on conventional binary DPSK modulators is provided. In some embodiments, the scheme uses 3π/8 rotating differential binary phase shift keying (3π/8-DBPSK) where one symbol (e.g., a ‘0’) is transmitted by phase change of 3π/8 radians and the opposite symbol (e.g., a ‘1’) is transmitted by phase change of −5π/8 (or 11π/8) radians.
Alternatively, this can be thought of as adding a constant 3π/8 radians to the phase shift for every bit modulated according to conventional DBPSK.
In another example, assume that first and second symbols, at discrete times k−1 and k, respectively, are output by the modulator. The phase shift of the symbol output at time k relative to that at time k−1 would be a function of the modulating data, either 3π/8 or 11π/8.
According to embodiments of the invention, the proposed variation on rotated DPSK for binary modulation substantially improves BER/PER performance over previously known rotated DPSK when a slicer or 1-bit ADC is employed at the receiver in order to keep implementation complexity low. Additionally, such a 3π/8 rotated differential modulation is more tolerant of a given frequency offset than the π/2-DBPSK modulation. This allows for receiver implementation where the frequency offset need be neither estimated nor compensated during payload demodulation.
Other features and aspects of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the features in accordance with embodiments of the invention. The summary is not intended to limit the scope of the invention, which is defined solely by the claims attached hereto.
The present invention, in accordance with one or more various embodiments, is described in detail with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict typical or example embodiments of the invention. These drawings are provided to facilitate the reader's understanding of the invention and shall not be considered limiting of the breadth, scope, or applicability of the invention. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale.
The figures are not intended to be exhaustive or to limit the invention to the precise form disclosed. It should be understood that the invention can be practiced with modification and alteration, and that the invention be limited only by the claims and the equivalents thereof.
Systems and methods described herein include a variation on conventional binary DPSK modulation schemes. In some embodiments, the scheme uses 3π/8 differential binary phase shift keying (3π/8-DBPSK) where one symbol (e.g., a ‘0’) is transmitted by phase change of 3π/8 radians and the other symbol (e.g., a ‘1’) is transmitted by phase change of −5π/8 radians (or equivalently 11π/8). Alternatively, this can be thought of as having an additional constant rotation of 3π/8 radians to the phase rotation of conventional DBPSK.
In another example, assume that a first and second symbols, at discrete times k−1 and k, respectively, are output by the modulator. The phase shift of the symbol output at time k relative to that at time k−1 would be a function of the modulating data, either 3π/8 or 11π/8.
According to embodiments of the invention, the proposed variation on rotated DPSK for binary modulation improves BER/PER performance in the presence of frequency offset between the transmitter and receiver when one chooses to not compensate for, or correct, the frequency offset in order to keep implementation complexity low. This is possible because such a 3π/8 rotated differential modulation is more tolerant of a given frequency offset than the π/2-DBPSK modulation is. This allows for receiver implementation where the frequency offset need be neither estimated nor compensated during payload demodulation.
A differentially modulated signal can be demodulated both coherently and differentially (in other words, non-coherently). With differential demodulation, the data can be recovered based on the phase change from one symbol to next, and this can be estimated by multiplying consecutive received symbols and making decisions based on the result. The derivation of the exact value of the probability of bit error for differential demodulation is difficult in general. However, for differential binary PSK, the bit error probability can be given by:
Where Eb/N0 is the signal-to-noise ration (SNR) per bit. This formula assumes that the frequency of the local reference signal is synchronized to the received signal and is valid for both conventional DBPSK and any rotated DBPSK, such as π/2-DBPSK. This is because the additional fixed rotation can be undone before the demodulation processing.
Embodiments described herein utilize a different angle rotation pair for a DBPSK modulation. One scheme uses 3π/8 rotated differential binary phase shift keying (3π/8-DBPSK) where one symbol (e.g., a ‘0’) is transmitted by phase change of 3π/8 radians and the other symbol (e.g., a ‘1’) is transmitted by phase change of −5π/8 radians.
The binary bit stream is mapped to complex symbols by binary differential phase shift keying modulation. The symbols s(k), k=0, 1, . . . , N/log 2M−1 and the bits b(n), n=0, 1, 2, . . . , N−1 are related by means of the following:
where
is the reference for the first symbol applied to the modulator, and the angle φk takes values from the following tables.
The BER performance of (rotated) DBPSK will generally degrade from that given above in paragraph [0026] in the presence of uncorrected frequency offset at the receiver. However, this loss can be reduced by use of a practically advantageous rotated DBPSK, e.g. 3π/8-DBPSK, as described in an embodiment of this invention. This allows for receiver implementation where the frequency offset need be neither estimated nor compensated during payload demodulation consequently reducing computation and power consumption at the receiver. Further improvement in BER/PER is obtained as described in an embodiment of this invention when a slicer is used instead of multi-bit converter. Using a slicer, such as a one-bit ADC, can lead to a lower-power design because the slicer typically consumes less power than a multi-bit ADC. Additionally, an implementation based on a slicer does not require a variable gain amplifier, which in turn results in a relatively simpler receive gain control mechanism that involves only switching the low-noise-amplifier state.
The constellation mapper 124 maps segments of the bitstream 122 by assigning them a single complex value in a constellation. Specifically, in some embodiments constellation mapper 124 accepts the input bits 122 and maps the input bits 122, or sets of input bits, to a sample point taken from signal point constellation. For example, in terms of the 3π/8 DBPSK modulation scheme, one symbol (e.g., a ‘0’) is transmitted by phase change of 3π/8 radians and the other symbol (e.g., a ‘1’) is transmitted by phase change of −5π/8 radians.
Constellation mapper 124 generates two outputs that are typically referred to as the in-phase, or I, and in-quadrature, or Q, samples.
The pulse shaper 126 can be included to make the transmitted signal better suited to the communication channel by limiting the effective bandwidth of the transmission. One commonly used pulse shaper is a square root raised cosine filter, although other pulse shapers or low pass filtering techniques can be used.
The in-phase samples are applied via pulse shaper 126 to modulator 128, which multiplies the applied signal by a carrier (e.g., sin ωt). The in-quadrature samples are applied via pulse shaper 126 to modulator 128, which multiplies the applied signal by a second carrier that is orthogonal to the first carrier (e.g., cos ωt). The I and Q output signals of the modulators are added to create the analog signal that is transmitted across wireless channel 133. The transmit DAC/RF Section 128 in this example includes a digital-to-analog converter and a transmitter to transmit the data across the wireless channel 133. With the DAC, the number of bits typically ranges from 4-6 bits.
At the receiver, the RF Section 142 downconverts the received RF signal to an IF or baseband signal. Although not illustrated, filtering can be included to select the desired channel. Also, an additional filtering scheme can be included that also functions as a matched filter to the pulse shaper 126 used in the transmit chain.
An ADC or a slicer/hard limiter 144 may be employed to interface to the digital section. The slicer 144 can be implemented as a 1-bit ADC or a hard limiter. A single slicer 144 evaluates the signal on a real IF signal or there may be one slicer on each of the I and Q channels, which determines if it is a positive or a negative value. In other words, for binary DPSK, the slicer can be configured to output the sign of the received symbol. For example, if the received symbol is positive on inphase signal, slicer maps it to +1.
In some embodiments, the demodulator generates the estimated data bit streams by matching the received symbols to the best-fit symbol, taking into account the modulation scheme employed at the transmitter. In the case of a PSK-modulated signal, for example, the signal phase of the received signal can be compared to all possible phase options as dictated by the modulator. For DPSK, the change in signal phase of the received symbol compared to the phase of the previously received symbol is used to determine the data. In other words, with DPSK, the received symbols are not decoded one-by-one to the constellation points, but instead, phase change Δθk=θk−θk-1 between successive symbols is computed and compared to all possible phase changes. The phase selected is the phase that yields the minimum Euclidian distance to the received phase (i.e. has the maximum likelihood).
For example, for a received symbol γk in the kth timeslot with a phase φk, the symbol can be denoted by γk=√{square root over (Es)}ejφk+ηk, where nk is the additive white Gaussian noise term. The decision for the phase difference between successive symbols, k and k−1, is based on the phase of the complex number:
γkγ*k-1=Esej(θ
In the absence of noise, the phase of this complex number is θk−θk-1.
In the case of binary DPSK in accordance with the constellation set forth in
In the illustrated example, the output symbols are pulse shaped at pulse shaper 146 and sent to Demap and demodulation 148. Demapper 148 essentially performs the inverse of constellation mapper 124 and maps the recovered symbol points into their corresponding bit sets to form the recovered digital data stream.
The above examples describe the DPSK system in terms of a 3π/8-DBPSK constellation mapping. In alternative embodiments, other symbol mapping schemes can be used, such as, for example, 5π/8-DBPSK and 7π/8-DBPSK, or in general (2k+1)π/8-DPSK, where kε{0, 1, 2, 3, 4, 5, 6, 7}. Likewise, schemes such as 3π/16-DBPSK, 5π/16-DBPSK, 7π/16-DBPSK, or other arbitrary angles, can be utilized.
Simulation results comparing the performance of π/2-DBPSK and 3π/8-DBPSK modulations are presented in
Although the invention is described above in terms of various exemplary embodiments and implementations, it should be understood that the various features, aspects and functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described, but instead can be applied, alone or in various combinations, to one or more of the other embodiments of the invention, whether or not such embodiments are described and whether or not such features are presented as being a part of a described embodiment. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments.
Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as meaning “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; the terms “a” or “an” should be read as meaning “at least one,” “one or more” or the like; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future. Likewise, where this document refers to technologies that would be apparent or known to one of ordinary skill in the art, such technologies encompass those apparent or known to the skilled artisan now or at any time in the future.
The presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to” or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent. The use of the term “module” does not imply that the components or functionality described or claimed as part of the module are all configured in a common package. Indeed, any or all of the various components of a module, whether control logic or other components, can be combined in a single package or separately maintained and can further be distributed in multiple groupings or packages or across multiple locations.
Additionally, the various embodiments set forth herein are described in terms of exemplary block diagrams, flow charts and other illustrations. As will become apparent to one of ordinary skill in the art after reading this document, the illustrated embodiments and their various alternatives can be implemented without confinement to the illustrated examples. For example, block diagrams and their accompanying description should not be construed as mandating a particular architecture or configuration.
