BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
FIG. 1 is a circuit block diagram which illustrates a phase detector with high speed and higher resolution in accordance with the prior art;
FIG. 2 illustrates a circuit diagram of the half-transparent (HT) module of the phase detector in FIG. 1;
FIG. 3 illustrates a first timing diagram of the first working condition of the phase detector in accordance with the prior art;
FIG. 4 illustrates a second timing diagram of the second working condition of the phase detector in accordance with the prior art;
FIG. 5 illustrates a curve chart of the input-output conversion of the phase detector in accordance with the prior art;
FIG. 6 is a circuit diagram which illustrates another phase detector based on dynamic circuit design in accordance with the prior art;
FIG. 7 is a circuit block diagram which illustrates a differential high-speed phase detector of the first embodiment of the present invention;
FIG. 8 is a circuit diagram which illustrates a DTHT module of the first embodiment in FIG. 7;
FIG. 9 illustrates a timing diagram of the first working condition of the differential high-speed phase detector of the present invention;
FIG. 10 illustrates a timing diagram of the second working condition of the differential high-speed phase detector of the present invention;
FIG. 11 illustrates a curve chart of the input-output conversion of the differential high-speed phase detector of the present invention;
FIG. 12 illustrates another curve chart of the input-output conversion of the differential high-speed phase detector of the present invention; and
FIG. 13 is another circuit diagram which illustrates a second embodiment of the DTHT module in FIG. 7.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the figures, in which like reference numerals are carried forward.
Refer to FIG. 7 and FIG. 8. FIG. 7 illustrates a circuit block diagram of the differential high-speed phase detector of the first embodiment of the present invention, and FIG. 8 illustrates a circuit diagram of a DTHT module of the first embodiment in FIG. 7.
The differential-type high-speed phase detector of the first embodiment of the present invention includes a first DTHT module 300 and a second DTHT module 400. Because the circuit scheme of the first DTHT module 300 is the same as the circuit scheme of the second DTHT module 400, only the first DTHT module 300 is described in the following.
The first DTHT module 300 includes a first input 301 for receiving a signal CK_ref, a second input 302 for receiving a signal CK_fb, a first logic unit 310, a second logic unit 320, a third logic unit 330 and an output 303.
The second DTHT module 400 includes a first input 401 for receiving a signal CK_ref, a second input 402 for receiving a signal CK_fb and an output 403. Furthermore, the first input 301 of the first DTHT module 300 connects with the second input 402 of the second DTHT module 400, and the second input 302 of the first DTHT module 300 connects with the first input 401 of the second DTHT module 400. The output 303 of the first DTHT module 300 connects with an output out_u, and the output 403 of the second DTHT module 400 connects with an output out_d.
The first logic unit 310 includes a first capacitor 311 (C1) and a second capacitor 312 (C2). The capacitors 311 and 312 may use fixed capacitors or metal-oxide-semiconductor (MOS) capacitors. The capacitance value of the first capacitor 311 is slightly bigger than the capacitance value of the second capacitor 312.
The input signal y entered from the first input 301 is transformed to a first input new signal y′ through the first capacitor 311 (C1); the input signal x entered from the second input 302 is transformed to a second input new signal x′ through the second capacitor 312 (C2).
The second logic unit 320 includes a first switch element 321 (M0, P-type metal-oxide-semiconductor: PMOS), a second switch element 322 (M1, P-type metal-oxide-semiconductor: PMOS) and a third switch element 323 (M2, N-type metal-oxide-semiconductor: NMOS), wherein these three switch elements are cascaded with each other. Both the gates (G) of the first switch element 321 and the third switch element 323 are connected with the first input 301 of the first DTHT module 300, and the gate (G) of the second switch element 322 is connected with the second input 302 of the first DTHT module 300. The second switch element 322 and the third switch element 323 of the second logic unit 320 respectively have a drain (D) connected to each other to form an output 324 (w) of the second logic unit 320.
The third logic unit 330 includes a first switch element 331 (M3, P-type metal-oxide-semiconductor: PMOS), a second switch element 332 (M4, N-type metal-oxide-semiconductor: NMOS) and a third switch element 333 (M5, N-type metal-oxide-semiconductor: NMOS), wherein these three switch elements are cascaded with each other. Both the gates (G) of the first switch element 331 and the third switch element 333 are connected with the output 324 (w) of the second logic unit 320, and a gate (G) of the second switch element 332 is connected with the second input new signal x′. The first switch element 331 and the second switch element 332 of the third logic unit 330 respectively have a drain (D) connected to each other to form an output 303 (z) of the first DTHT module 300.
Refer to FIG. 8. The first capacitor 311 and the second capacitor 312 are set on the paths of the input signal x and the input signal y in parallel. Moreover, the capacitance value of the first capacitor 311 is slightly bigger than the capacitance value of the second capacitor 312. Therefore, an imperceptible delay period difference tdc1−tdc2 is produced on the paths connected with the input signal y and the input signal x (shown in FIG. 9).
Refer to FIG. 9 and FIG. 10. FIG. 9 illustrates a timing diagram of the first working condition, and FIG. 10 illustrates a timing diagram of the second working condition of the differential-type high-speed phase detector of the present invention. In FIG. 9, the rising edge of the input signal y is lagged than the rising edge of the input signal x. In FIG. 10, the rising edge of the input signal y is led to the rising edge of the input signal x.
Refer to FIG. 8 and FIG. 9. In the first logic unit 310, the period difference+Δ (the phase difference is +Δ/tcyc·2π, and tcyc denotes the periods of the input signals x and y) between the input signal x and the input signal y is transformed to the period difference+Δ+(tdc1−tdc2) between the first input new signal y′ and the second input new signal x′. As the aforementioned description, the imperceptible delay period difference tdc1−tdc2 is produced by the capacitance difference between the first capacitor 311 and the second capacitor 312 of the first logic unit 310. In the second logic unit 320, when the first input new signal y′ and the second input new signal x′ are both low level (y′=0, x′=0), the first switch element 321 (M0) and the second switch element 322 (M1) are closed. Therefore, the output signal w is raised to a high level such that the first switch element 331 (M3) of the third logic unit 330 is opened and the third switch element 333 (M5) is closed. Meanwhile, because the second input new signal x′ is at a low level, the second switch element 332 (M4) of the third logic unit 330 is opened to keep the output signal z in the previous high level condition. When the second input new signal x′ is transformed to a high level, the second switch element 322 (M1) of the second logic unit 320 is opened, and the second switch element 332 (M4) of the third logic unit 330 is closed to transform the output signal z from high level to low level. The output signal z is kept at a low level until the first input new signal y′ is transformed to a high level. The output signal (w) of the second logic unit 320 is transformed to a low level because the first input new signal y′ is transformed to a high level. Thus, the first switch element 331 (M3) of the third logic unit 330 is closed and the third switch element 333 (M5) is opened to raise the output signal z to a high level. As a result, the output signal z is kept in low level until the first input new signal y′ is transformed to a high level.
Consequently, the rising edge signal period difference (+Δ+(tdc1−tdc2)) between the second input new signal x′ and the first input new signal y′ is bigger than the period difference (+Δ) between the input signal x and the input signal y because of the differential effect of the capacitance value between the capacitor C1 and the capacitor C2 of the first logic unit 310. Thus, each of the above switch elements (M0˜M5) has a longer period to generate a complete signal with an accurate level to output.
In the timing diagram of the first embodiment in FIG. 9 which illustrates capacitance difference effect of the first logic unit 310. If the period difference +A between the original input signals x and y is unable to let the output signal z be completely discharged to a low level to generate a complete signal output with an accurate level through the path caused by the closing of the second switch element 332 (M4) and the third switch element 333 (M5), the sum (+Δ+(tdc1−tdc2)) of the imperceptible delay period difference (tdc1−tdc2) caused by the capacitance differential effect and the original period difference +Δ of the first logic unit 310 allows each of the above switch elements (M0˜M5) to have a sufficient period to generate a complete signal output at an accurate level.
Likewise, if the phase difference (−Δ) between the rising edge of the input signal y and the rising edge of the input signal x is dealt by the capacitance differential effect of the first logic unit 310, a period difference −Δ+(tdc1−tdc2) between the first input new signal y′ and the second input new signal x′ is generated. Besides, in order to insulate the discharge path of the input signal z of the DTHT module and keep the signal at in a high level, the value of (tdc1−tdc2) is set lower than or same as the Δ value. Thus, in the assumed condition, (tdc1−tdc2)=Δ, the equivalent period difference value in the first embodiment in FIG. 9 is shown as the following equation:
+Δ+(tdc1−tdc2)=2Δ
; and another equivalent period difference value in the second embodiment in FIG. 10 is shown as the following equation:
−Δ+(tdc1−tdc2)=0
When the first DTHT module 300 is dealt with the capacitance difference effect of the first logic unit 310, and conditions of generating the imperceptible delay period difference (tdc1−tdc2) and the period difference A are the same, a complete logic level output pulse 500 with a 2Δ(+Δ+(tdc1−tdc2) width is generated in the first working condition timing diagram of FIG. 9. The output signal z is maintained at a high level because there is no discharge path in the second working condition timing diagram of FIG. 10. The differential-type high-speed phase detector of the present invention not only diminishes the size of the dead zone of the phase detector in accordance with the prior art but also keeps original tri-state output [( out_u, out_d)=(0,1)(1,0)(1,1,)].
Considering manufacturing inaccuracies, the produced (tdc1−tdc2) value is possibly bigger than the Δ value. In this condition, the original output ( out_u, out_d)=(0,1,)(1,0)(1,1) is transformed to the output ( out_u, out_d)=(0,1)(1,0)(0,0,). In other words, when the phase difference between the input signal y and the input signal x is approximately zero, both the output out_u and the output out_d each generate a low level pulse signal (500) with different pulse widths. Therefore, the result of phase lagging or leading between the two input signals can be determined by the width of two output pulse signals.
The tri-state output result caused when the manufacturing process inaccuracies occur or dead zone is approximately zero does not affect the application using a charge pump to be the circuit controller. Even though each of the output out_u and the output out_d generate a pulse signal, the charge pump (not shown) of the phase detector can determine the current control level depending on the difference of the pulse width.
Refer to FIG. 5, FIG. 11 and FIG. 12. FIG. 11 illustrates a curve chart of the input-output conversion of the differential high-speed phase detector of the present invention, and FIG. 12 illustrates another curve chart of the input-output conversion of the differential high-speed phase detector of the present invention. The size of the dead zone of the phase detector of the present invention is much smaller than the one of the prior art such that the dead zone efficiency of the present invention is much better.
Compared with the defects of the phase detector in accordance with the prior art, the differential-type high-speed phase detector of the present invention modifies the capacitance value of the different path to generate an imperceptible delay period difference to increase the period difference between the input signal y and the input signal x of the two DTHT modules. Thus, the switch elements (M0-M5) have a sufficient switch period to respond and the output signal z is completely discharged to low level. The DTHT module of this invention can diminish the size of the dead zone of the HT module of the phase detector in accordance with the prior art. Moreover, only the input signal y and the input signal x are used without an additional input signal. As a result, the easier timing control of the circuit can be directly applied to other designs.
Refer to FIG. 13. FIG. 13 is another circuit diagram which illustrates a second embodiment of the DTHT module in FIG. 7. The difference between FIG. 8 and FIG. 13 is that the first capacitor 311 and the second capacitor 312 of the first embodiment are changed into the first MOS capacitor 311′ and the second MOS capacitor 312′ of the first logic unit 310′. A fourth logic unit 340 is also added between the paths of the input signal y and the input signal x and the first logic unit 310′. The fourth logic unit 340 includes a first logic gate 341 (Ma) cascaded in the input signal y and a second logic gate 342 (Mb) cascaded in the input signal x, and both the first logic gate 341 (Ma) and the second logic gate 342 (Mb) are buffers. The circuit schemes of the second logic unit 320′ and the third logic unit 330′ are the same as the circuit schemes of the first embodiment in FIG. 8.
The second embodiment of the present invention can make the integrated circuit of the phase detector practice, and further produces a more imperceptible delay period difference. In addition, the first logic gate 341 (Ma) and the second logic gate 342 (Mb) can reduce signal strength tolerance of the input signal y and the input signal x.
Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, other embodiments are possible. Therefore, their spirit and scope of the appended claims should no be limited to the description of the preferred embodiments container herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080061838
