Patent Application
20170054415
Field
This disclosure relates generally to a voltage reference buffer, and more specifically, to reducing flicker noise in the voltage reference buffer using resistor chopping.
Background
A current-source based voltage reference buffer drives a resistive digital to analog converter (RDAC) used in the receive path of an encoder/decoder (CODEC). To achieve good total harmonic distortion plus noise (THD+N) in the CODEC, the noise of the current-source based voltage reference buffer needs to be low. In particular, the resistor flicker noise can be particularly troublesome as it may be very significant at low frequencies.
The present disclosure describes various implementations of circuits, apparatus, and methods for reducing flicker noise of a differential signal in a voltage reference buffer.
In one embodiment, a voltage reference buffer circuit is disclosed. The circuit includes: an amplifier having input terminals and output terminals; a plurality of current sources coupled to the input terminals of the amplifier, the plurality of current sources including a plurality of degeneration resistors coupled to a first plurality of voltage supplies; and a degeneration resistor chopping module comprising a first and second plurality of switches coupled to the plurality of degeneration resistors.
In another embodiment, a method of reducing flicker noise of a differential signal in a voltage reference buffer is disclosed. The method includes: frequency chopping a plurality of degeneration resistors by configuring first and second pluralities of switches; controlling the first plurality of switches with a first clock signal; and controlling the second plurality of switches with a second clock signal, wherein the first and second clock signals are complementary signals.
In a further embodiment, a method for reducing flicker noise of a differential signal in a voltage reference buffer is disclosed. The method includes: frequency chopping a plurality of degeneration resistors by synchronously reversing polarity of the differential signal on the plurality of degeneration resistors at a chopping frequency to move the differential signal to higher frequencies; configuring a first plurality of switches controlled by a first clock signal; and configuring a second plurality of switches controlled by a second clock signal, wherein the first and second clock signals are complementary signals.
In yet another embodiment, an apparatus for reducing flicker noise of a differential signal in a voltage reference buffer is disclosed. The apparatus includes: means for frequency chopping a plurality of degeneration resistors of a plurality of current sources of the voltage reference buffer, the means for frequency chopping further comprising means for synchronously reversing polarity of the differential signal on the plurality of degeneration resistors at a first chopping frequency to move at least a portion of the flicker noise in the differential signal to higher frequencies.
Other features and advantages of the present disclosure should be apparent from the present description which illustrates, by way of example, aspects of the disclosure.
The details of the present disclosure, both as to its structure and operation, may be gleaned in part by study of the appended further drawings, in which like reference numerals refer to like parts, and in which:
As stated above, flicker noises of a current-source based voltage reference buffer need to be low. The resistor flicker noise can be particularly troublesome as it is very significant at low frequencies. One technique involves moving the noise in the signal to higher frequencies. For example, the signal at the resistors can be chopped with a frequency to carry an alternating current (AC) signal, which can be filtered to attenuate the flicker noise. In one embodiment, a low-pass filter can be used to filter out the noise in the high frequency signals. In another embodiment, for example in audio frequencies, the noise is moved into the high frequency signals and is ignored.
After reading this description it will become apparent how to implement the disclosure in various implementations and applications. Although various implementations of the present disclosure will be described herein, it is understood that these implementations are presented by way of example only, and not limitation. As such, this detailed description of various implementations should not be construed to limit the scope or breadth of the present disclosure.
The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.
Wireless device 210 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. Wireless device 210 may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. Wireless device 210 may communicate with wireless system 200. Wireless device 210 may also receive signals from broadcast stations (e.g., broadcast station 224), signals from satellites (e.g., satellite 240) in one or more global navigation satellite systems (GNSS), etc. Wireless device 210 may support one or more radio technologies for wireless communication including LTE, WCDMA, CDMA 1×, EVDO, TD-SCDMA, GSM, 802.11, etc.
In the transmit path, the data processor/controller 310 may process (e.g., encode and modulate) data to be transmitted and provide the data to a digital-to-analog converter (DAC) 330. The DAC 330 converts a digital input signal to an analog output signal. The analog output signal is provided to a transmit (TX) baseband (lowpass) filter 332, which may filter the analog output signal to remove images caused by the prior digital-to-analog conversion by the DAC 330. An amplifier 334 may amplify the signal from the TX baseband filter 332 and provide an amplified baseband signal. An upconverter (mixer) 336 may receive the amplified baseband signal and a TX local oscillator (LO) signal from a TX LO signal generator 372. The upconverter 336 may upconvert the amplified baseband signal with the TX LO signal and provide an upconverted signal. A filter 338 may filter the upconverted signal to remove images caused by the frequency upconversion. A power amplifier (PA) 340 may amplify the filtered RF signal from the filter 338 to obtain the desired output power level and provide an output RF signal. The output RF signal may be routed through a duplexer/switch 364.
For frequency-division duplexing (FDD), the transmitter 320 and the receiver 350 may be coupled to the duplexer 364, which may include a transmit (TX) filter for the transmitter 320 and a receive (RX) filter for the receiver 350. The TX filter may filter the output RF signal to pass signal components in a transmit band and attenuate signal components in a receive band. For time-division duplexing (TDD), the transmitter 320 and the receiver 350 may be coupled to the switch 364. The switch 364 may pass the output RF signal from the transmitter 320 to the antenna 390 during uplink time intervals. For both FDD and TDD, the duplexer/switch 364 may provide the output RF signal to the antenna 390 for transmission via a wireless channel.
In the receive path, the antenna 390 may receive signals transmitted by base stations and/or other transmitter stations and may provide a received RF signal. The received RF signal may be routed through duplexer/switch 364. For FDD, the RX filter within the duplexer 364 may filter the received RF signal to pass signal components in a receive band and attenuate signal components in the transmit band. For TDD, the switch 364 may pass the received RF signal from the antenna 390 to the receiver 350 during downlink time intervals. For both FDD and TDD, the duplexer/switch 364 may provide the received RF signal to the receiver 350.
Within the receiver 350, the received RF signal may be amplified by a low noise amplifier (LNA) 352 and filtered by a filter 354 to obtain an input RF signal. A downconverter (mixer) 356 may receive the input RF signal and an RX LO signal from an RX LO signal generator 370. The downconverter 356 may downconvert the input RF signal with the RX LO signal and provide a downconverted signal. The downconverted signal may be amplified by an amplifier 358 and further filtered by an RX baseband (lowpass) filter 360 to obtain an analog input signal. The analog input signal is provided to an analog-to-digital converter (ADC) 362. The ADC 362 converts an analog input signal to a digital output signal. The digital output signal is provided to the data processor/controller 310.
The data processor/controller 310 may perform various functions for the wireless device. For example, the data processor/controller 310 may perform processing for data being transmitted via the transmitter 320 and received via the receiver 350. The data processor/controller 310 may control the operation of various circuits within the transmitter 320 and the receiver 350. The data processor/controller 310 may also interface with output devices 382 (e.g., a speaker) and input devices 384 (e.g., a microphone) through the CODEC 380. The memory 312 may store program codes and data for the data processor/controller 310. The memory 312 may be internal or external to the data processor/controller 310. The memory 312 may be referred to as a computer-readable medium. The data processor/controller 310 may be implemented on one or more application specific integrated circuits (ASICs) and/or other ICs.
The transmit channel 420 includes an analog signal processor 426, an ADC 424, and a digital signal processor 422. The analog signal processor 426 receives and processes an analog input signal from the input devices 384. The ADC 424 converts the processed analog input signal to a digital signal. The digital signal processor 422 receives and processes the converted digital signal and outputs the processed digital signal to the data processor/controller 310.
In the illustrated embodiment of
Referring back to
In the illustrated embodiment of
As stated above, the degeneration resistors 602, 604 provide a negative feedback for the common-source amplifier configurations of the PMOS/NMOS transistors 612, 614. In other embodiments, the common-source amplifiers can be configured differently, while providing the same functions. For example, the common-source amplifiers 612, 614 can be configured with different combinations of complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), bipolar-CMOS (BiCMOS) transistors, silicon germanium (SiGe) transistors, gallium arsenide (GaAs) transistors, heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), and silicon-on-insulators (SOIs).
In the illustrated embodiment of
By chopping the resistors at the chopping frequency, substantial portion of the flicker noise in the differential signal is moved to higher frequencies, which may be filtered to attenuate the flicker noise. Thus, the higher frequency signals are then filtered, at block 730, to attenuate the flicker noise. In the alternative, the higher frequency signals (e.g., above 100 KHz to 200 KHz in audio applications) may be ignored since they are not audible. The range of the higher frequency signals may vary depending on the application of the CODEC. For example, in an audio application, the range of low frequency signals of interest is between 20 Hz and 20 KHz, while in an ultrasonic application, the range of low frequency signals of interest is between 20 Hz and 100 KHz. In either audio or ultrasonic application, signals above 200 KHz would be considered higher frequency signals and are either filtered out (e.g., using a low-pass filter) or ignored.
Although several embodiments of the disclosure are described above, many variations of the disclosure are possible. For example, although the illustrated embodiments of the frequency chopper are configured for a voltage reference buffer, the frequency chopper can be configured for use in other modules such as low noise amplifiers or power amplifiers. Further, features of the various embodiments may be combined in combinations that differ from those described above. Moreover, for clear and brief description, many descriptions of the systems and methods have been simplified. Many descriptions use terminology and structures of specific standards. However, the disclosed systems and methods are more broadly applicable.
Those of skill will appreciate that the various illustrative blocks and modules described in connection with the embodiments disclosed herein can be implemented in various forms. Some blocks and modules have been described above generally in terms of their functionality. How such functionality is implemented depends upon the design constraints imposed on an overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosure. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module or block without departing from the disclosure.
The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, it is to be understood that the description and drawings presented herein represent presently preferred embodiments of the disclosure and are therefore representative of the subject matter which is broadly contemplated by the present disclosure. It is further understood that the scope of the present disclosure fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present disclosure is accordingly limited by nothing other than the appended claims.
