Claims
- 1. In a particular portion of a state-variable electronic apparatus employing an efficient digit-serial arithmetic and being supplied recurring clockwise signals to advance data in parallel with other portions of said state-variable electronic apparatus, each digit-serial operand employed in the digit-serial arithmetic of said particular portion of the state-variable electronic apparatus having data words invariably of W bits supplied n bits at a time in W/n successive digits of progressively grater significance, where n is an integer at least three and W is a multiple at least twice of n, the bits in each succeeding digit of each successive data word of each said digit-serial operand being identified by respective ones of consecutive ordinal numbers first through n.sup.th in order of their increasing significance, the n.sup.th bit of the last digit of each data word being indicative of its sign when that said data word is a signed number, a combination comprising:
- first, second and third n-bit-wide data latches arranged for simultaneously latching responsive to each of said clocking signals to advance data, each said data latch comprising a respective plurality n in number of unit-clock delay elements identified by respective ordinal numbers first through n.sup.th and provided with respective input connections and respective output connections;
- means for applying a stream of first digit-serial operands to the respective input connections of the first through n.sup.th unit-clock delay elements in said first n-bit-wide data latch;
- means for applying a stream of second digit-serial operands to the respective input connections of the first through n.sup.th unit-clock delay elements in said first n-bit-wide data latch so the least significant digit of each said second digit-serial operand has its n bits latched at the respective output connections of the first through n.sup.th unit-clock delay elements in said second n-bit-wide data latch at the same time as the least significant digit of a corresponding one of said first digit-serial operands has its n bits latched at the respective output connections of the first through n.sup.th unit-clock delay elements in said first n-bit-wide data latch;
- a plurality n in number of full adders identified by respective ordinal numbers first through n.sup.th, each full adder provided with a respective addend input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said first n-bit-wide data latch, a respective augent input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said second n-bit-wide data latch, a respective carry input connection, a respective sum output connection connected to the input connection of the unit-clock delay element identified by corresponding ordinal number in said third n-bit-wide data latch, and a respective carry output connection, the carry output connection of each of said full adders except the n.sup.th respectively connecting to the carry input connection of said full adder identified by the next higher ordinal number; and
- selection apparatus for selecting a forced carry bit to the carry input connection of sad first full adder during said times the first digits of said first and second digit-serial operands are latched and for otherwise selecting the bits supplied at the carry output connection of said n.sup.th full adder as delayed one clock interval to the carry input connection of said first full adder.
- 2. The combination set forth in claim 1 wherein W/n is greater than three.
- 3. In a particular portion of a state-variable electronic apparatus employing an efficient digit-serial arithmetic and being supplied recurring clocking signals to advance data in parallel with other portions of said state-variable electronic apparatus, each digit-serial operand employed in the digit-serial arithmetic of said particular portion of the state-variable electronic apparatus having data words invariably of W bits supplied n bits at a time in W/n successive digits of progressively greater significance, where n is an integer at least three and W is a multiple of at least twice of n, the bits in each successive digit of each successive data word of each said digit-serial operand being identified by respective ones of consecutive ordinal numbers first through n.sup.th inn order of their increasing significance, a combination comprising:
- first, second and third n-bit-wide data latches arranged for simultaneously latching responsive to each of said clocking signals to advance data, each said data latch comprising a respective plurality n in number of unit-clock delay elements identified by respective ordinal numbers first through n.sup.th and provided with respective input connections and respective output connections;
- means for applying a stream of first digit-serial operands to the respective input connections of the first through n.sup.th unit-clock delay elements in aid first n-bit-wide data latch;
- means for applying a stream of second digit-serial operands to the respective input connections of the first through n.sup.th unit-clock delay elements in said second n-bit-wide data latch so the least significant digit of said second digit-serial operand has its n bits latched at the respective output connections of the first through n.sup.th unit-clock delay elements in said second n-bit-wide data latch at the same times as the least significant digit of said first digit-serial operand has its n bits latched at the respective output connections of the first through n.sup.th unit-clock delay elements in said first n-bit-wide data latch;
- a plurality n in number of full adders identified by respective ordinal numbers first through n.sup.th, each full adder provided with a respective addend input connection connected from the output connection of the unit-clock delay element identified by corresponding ordinal number in said first n-bit-wide data latch, a respective augend input connection, a respective carry input connection, a respective sum output connection connected to the input connection of the unit-clock delay element identified by corresponding ordinal number in said third n-bit-wide data latch, and a respective carry output connection, the carry output connection of each of said full adders except the n.sup.th respectively connecting to the carry input connection of said full adder identified by the next higher ordinal number;
- selection apparatus for selecting a forced carry bit to the carry input connection of said first full adder during said times the first digits of said first and second digit-serial operands are latched and for other selecting the bits supplied at the carry output connection of said n.sup.th full adder as delayed one clock interval too the carry input connection of said first full adder; and
- means for selectively one's complementing the bits from the output connections of said first through n.sup.th unit-clock delay elements in said second n-bit-data latch, for application to the augend input connections of said first through n.sup.th full adders respectively.
- 4. The combination set forth inn claim 3 wherein W/n is greater than three.
BACKGROUND OF THE INVENTION
This is a continuation-in-part of U.S. Pat. application Ser. No. 265,210 filed 31 Oct. 1988, now U.S. Pat. No. 5,010,511 issued, which is a continuation-in-part of U.S. Pat. application Ser. No. 182,602 filed 18 Apr. 1988, now U.S. Pat. No. 4,951,221 issued 21 Aug. 1990.
The invention relates to combining apparatus as may perform, on a pipelined basis, addition and subtraction processes. More particularly, the invention relates to pipe-lined linear combining apparatus for performing these processes on digit-serial data.
Digital signals having words of a number W of bits may be subjected to parallel processing, serial processing, or processing that combines features of parallel and serial processing. Parallel processing of the W-bit words wherein the W bits flow in respective bit streams for simultaneous individual processing allows relatively high rates of processing with relatively low latency. However, processing circuitry is in large part replicated W-fold with attendant cost in terms of operating power and digital hardware. In monolithic integrated circuit constructions, more die area is consumed because of the increased hardware requirements. Serial prccessing, wherein the W bits of each word are sequentially processed, does not require W-fold replication of hardware. However, processing is slower and latency in terms of clock cycles is longer than for parallel processing
To obtain favorable trade offs between speed of processing and digital hardware requirements, the W-bit words can each be divided into W/n subwords or digits of n bits each, providing W is a multiple of n. Then, the digits are serially subjected to parallel processing in n parallel bit streams.
M.J. Irwin and R.M Owens describe a specific system of this general sort in "Digit-Pipelined Arithmetic as Illustrated by the Paste-Up System: A Tutorial", Computer, Apr. 1987, pages 73-85. Irwin and Owen espouse a system wherein successive digits of a word are supplied in order of decreasing significance of their bits. Irwin and Owen in FIG. 3 of their article show a pipelined adder for such a system That adder requires two single-bit addition steps per bit of each digit Irwin and Owen avoid the need to wait for a carry that ripples up from the least significant end by using signed-digit or redundant arithmetic.
Such arithmetic is described by A. Avizienis in Signed-Digit Number Representations for Fast Parallel Arithmetic", IRE Transactions in Electronic Computers, Sept. 1961, pages 389-400. Signed-digit arithmetic is redundant in that positive and negative digits are differently represented Essentially, signed arithmetic costs a sign bit per digit, rather than just one sign bit per word. A pipelined arithmetic that is efficient is desirable, however, since a digital hardware saving of almost one-n.sup.th would then be possible
If Irwin and Owen are correct in their opinion that most-significant-digit-first processing mandates redundant arithmetic, then least-significant-digit-first processing must be employed in order to use efficient digits.
S.G. Smith and P.A. Denyer describe the use of an efficient digital arithmetic with two-bit digits in "Radix-4 Modules for Higher-Performance Bit-Serial Computation", IEE Proceedings, Vol 134, Pt. E, No. 6, Nov. 1987, pages 271-276. They denominate normal bit-serial data communication carried out on a single wire as being "radix-two" bit-serial data communication. In radix-two-bit-serial communication, they note, computational elements have one logical input per input operand. An W-bit data word is transmitted least significant bit first and is processed in W clock cycles, one bit per clock cycle Smith and Denyer propose what they term "radix-four bit-serial" data communication which is performed concurrently on a pair of wires, one carrying even-numbered bits, the other odd-numbered bits. The concurrent bit pairs, or radix-four digits, represent side-by-side bit places from the data word; and data are transmitted in order of increasing bit significance. That is, the relatively less significant digits of a word are transmitted before the relatively more significant bits of a word Computational elements for the radix-four digital data have two logical inputs per input operand; and a W-bit, (W/2)-digit data word is processed in W/2 clock cycles Radix-four bit-serial data communication is also described in less particular terms in an earlier-published S G Smith, M.S McGregor and P.B Denyer paper "Techniques to Increase the Computational Throughout of Bit-Serial Architectures", IEEE Proceedings of ICASSP 1987, Apr. 1987, pages 543-546.
U.S. Pat. application Ser. No. 182,602, filed 18 Apr. 1988 by P.F. Corbett and R.I. Hartley issued 21 Aug. 1990 as U.S. Pat. No 4,951,221, entitled A CELL STACK FOR VARIABLE DIGIT WIDTH SERIAL ARCHITECTURE, assigned to General Electric Company and not acknowledged by this disclosure to constitute prior art adversely affecting the patentability of the present invention, is of interest. This application defines "digit-serial arithmetic" wherein W-bit operand words are grouped on the basis of bit significance into W/n successive digits of n bits each, which digits occur in successive clock intervals in order of increasing significance with passage of time. The n parallel bit streams that provide serial digit flow are accompanied by a control signal identifying the partitioning between successive words. U.S. Pat. No. 4,951,221 indicates that digit-serial data processing using digits of four to eight bits usually provides the best trade-offs between throughput rate and efficient utilization of monolithic-integrated-circuit die area. That is, radix-16, radix-32, radix-64, radix-128, or radix-256 digits are indicated to be generally preferable to radix-four digits. U.S. Pat. No. 4,952,221 notes that these optima had not been previously appreciated in the serial computational arts.
Of particular interest in the above-referred-to Nov. 1987 Smith and Denyer paper, insofar as the invention herein described is concerned, is the radix-four cascade adder of FIG. 6b in that paper. This adder is similar to cascade adders for digit-serial numbers for higher radix digits, as described in U.S. Pat. No. 4,951,221.
The invention is embodied in linear combining apparatus for combining first and second digit-serial operands, the words of which have W bits apiece supplied n bits at a time on W/n successive digits during respective clock intervals, n and W/n being plural integers. Generally it is preferable that n be at least three. The n bits of each digit of the first and second operands are identified by respective consecutive ordinal numbers first through n.sup.th assigned in order of increasing significance. The linear combining apparatus includes a plurality in number of n full adders respectively identified by consecutive ordinal numbers first through n.sup.th, each full adder adding a bit of said first operand identified by the same ordinal number as it is either to the bit of said second operand also identified by the same ordinal number or to the complement of that bit. The carry bits generated by each of the first through (n-1).sup.th full adders is applied as carry input signal to the full adder with next higher ordinal number. Either the carry bit of the n.sup.th full adder, as delayed by one clock interval, or a forced carry bit is selectively supplied as the carry input signal of the first full adder.
US Referenced Citations (6)
Non-Patent Literature Citations (6)
| Entry |
| M. J. Irwin & R. M. Owens, "Digit-Pipelined Arithmetic as Illustrated by the Paste-Up System: A Tutorial", Computer, Apr. 1987, pp. 61-73. |
| A. Avizienis, "Signed-Digit Number Representations for Fast Parallel Arithmetic", Ire Transactions in Electronic Computers, Sep. 1961, pp. 389-400. |
| S. G. Smith, P. B. Denver, "Radix-4 Modules for Higher Performance Bit-Serial Computation", IEEE Proceedings, vol. 34, Pt. 3, No. 6, Nov. 1987, pp. 271-276. |
| Jean-Loup Baer, Computer Systems Architecture, 1980 Computer Science Press, Inc., Potomac, Md., pp. 113-116. |
| Bell et al.-"Serial Adder", IBM Technical Disclosure Bulletin, vol. 4, No. 8, p. 37, Jan. 1962. |
| Larsen et al., "Introductory Experiments in Digital Electronics and 8080A Microcomputer Programming and Interfacing", vol. 2, pp. 115-124, Howard W. Sams & Co., Indianapolis, Ind. 1978. |
Continuation in Parts (2)
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Number |
Date |
Country |
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265210 |
Oct 1988 |
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| Parent |
182602 |
Apr 1988 |
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Patent Grant
5084834
