Digital-analog converter, data driver, and flat panel display device using the same

Abstract

A digital-analog converter (DAC) including: a gray scale generator for generating gray scale voltages corresponding to digital data input through charge sharing between a plurality of data lines and a plurality of dummy data lines; a switching signal generator for providing operation control signals for a plurality of switches of the gray scale generator; and a reference voltage generator for generating reference voltages and for providing the reference voltages to the gray scale generator. According to the present invention, the digital-analog converter uses capacitance components existing in the respective data lines and the dummy data lines as a sampling capacitor and a holding capacitor to generate desired gray scale voltages through charge sharing between the data lines and the dummy data lines, thereby reducing area and power consumption over an existing R-string type of DAC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.

FIG. 1 is a block diagram showing a conventional data driver;

FIG. 2 is a block diagram showing a digital-analog converter (DAC) of the data driver of FIG. 1;

FIG. 3 is a block diagram showing a DAC according to an embodiment of the present invention;

FIG. 4 is a block diagram showing a gray scale generator of the DAC of FIG. 3;

FIG. 5 is a signal waveform diagram showing an example of digital data input to the gray scale generator shown in FIG. 4;

FIG. 6 is a simulation waveform diagram showing outputs of the gray scale generator for the inputs shown in FIG. 5;

FIG. 7 is a constitutional block diagram showing a data driver according to an embodiment of the present invention; and

FIG. 8 is a block diagram showing a flat panel display device according to an embodiment of the present invention.

Claims

1. A digital-analog converter comprising: a gray scale generator for generating gray scale voltages corresponding to digital data input through charge sharing between a plurality of data lines and a plurality of dummy data lines;a switching signal generator for providing operation control signals for a plurality of switches of the gray scale generator; anda reference voltage generator for generating reference voltages and for providing the reference voltages to the gray scale generator.

2. The digital-analog converter as claimed in claim 1, wherein the charge sharing is executed by using respective parasitic capacitance components existing in the data lines and the dummy data lines as a holding capacitor and a sampling capacitor.

3. The digital-analog converter as claimed in claim 1, wherein the gray scale generator comprises: a sampling capacitor formed by parasitic capacitance components existing in at least one of the dummy data lines;a holding capacitor formed by parasitic capacitance components existing in at least one of the data lines;a first switch for controlling a reference voltage at a high level to be supplied to the sampling capacitor depending on respective bit values of input digital data;a second switch for controlling a reference voltage at a low level to be supplied to the sampling capacitor depending on the respective bit values of the input digital data;a third switch provided between the sampling capacitor and the holding capacitor for applying the charge sharing between the sampling capacitor and the holding capacitor; anda fourth switch connected to the holding capacitor to initialize the holding capacitor.

4. The digital-analog converter as claimed in claim 3, wherein the holding capacitor is initialized with at least one of the reference voltage at the high level or the reference voltage at the low level by turning on the fourth switch.

5. The digital-analog converter as claimed in claim 3, wherein the charge sharing between the sampling capacitor and the holding capacitor is executed for a plurality of periods during which each of a plurality of bits of the digital data is input, and wherein a result of the charge sharing executed at a last one of the plurality of periods is applied to the data lines as fine ones of the gray scale voltages.

6. The digital-analog converter as claimed in claim 5, wherein the charge sharing evenly distributes the reference voltages stored in the sampling and holding capacitors by turning on the third switch for a period of each of the plurality of periods.

7. The digital-analog converter as claimed in claim 6, wherein the third switch is turned on after a turn on operation of at least one of the first switch or the second switch is completed.

8. The digital-analog converter as claimed in claim 1, wherein the dummy data lines are adjacent to the data lines so that the data lines and the dummy lines are alternately formed on a panel of a display device including the digital-analog converter.

9. A data driver comprising: a shift register unit for providing sampling signals by generating a shift register clock;a sampling latch unit for sampling and latching digital data having a plurality of bits by receiving the sampling signals for every column line;a holding latch unit for simultaneously receiving and latching digital data latched in the sampling latch unit, and for converting and outputting the digital data in a serial state for every each of the bits of the digital data; anda digital-analog converter for generating gray scale voltages to correspond to bit values of the digital data supplied from the holding latch unit in a serial state through charge sharing between a plurality of data lines and a plurality of dummy data lines provided on a panel of a display device including the data driver and for providing the gray scale voltages to the data lines.

10. The data driver as claimed in claim 9, wherein the holding latch unit receives a shift register clock signal generated from the shift register, and converts the digital data received in a parallel state into the serial state through the clock signal and outputs the digital data in the serial state to the digital-analog converter.

11. The data driver as claimed in claim 9, wherein the digital-analog converter generates the analog gray scale voltages corresponding to the bit values of the digital data input through charge sharing between at least one of the data lines and at least one of the dummy data lines formed adjacent to the at least one of the data lines and outputs the gray scale voltages to the corresponding pixels connected to the data lines.

12. The data driver as claimed in claim 11, wherein the charge sharing is executed by using respective parasitic capacitance components existing in the at least one of the data lines and the at least one of the dummy data lines as a holding capacitor and a sampling capacitor.

13. The data driver as claimed in claim 11, wherein the data lines and the dummy lines are alternately formed on the panel.

14. A flat panel display device comprising: a display region comprising a plurality of pixels connected with a plurality of scan lines arranged in a first direction, a plurality of data lines arranged in a second direction, and a plurality of dummy data lines formed adjacent to the respective data lines;a data driver for supplying gray scale voltages to the plurality of pixels; anda scan driver for supplying scan signals to the scan lines,wherein the data driver generates the gray scale voltages corresponding to the digital data input through charge sharing between the data lines and the dummy data lines and provides the gray scale voltages to corresponding ones of the pixels.

15. The flat panel display device as claimed in claim 14, wherein the charge sharing is executed by using respective parasitic capacitance components existing in the data lines and the dummy data lines as a holding capacitor and a sampling capacitor.

16. The flat panel display device as claimed in claim 14, wherein the data lines and the dummy lines are alternately formed on a panel of the flat panel display device, and wherein the respective data lines and the dummy data lines adjacent to the respective data lines are formed in pairs.

17. The flat panel display device as claimed in claim 14, where the pixels are connected with the data lines arranged in the second direction, and wherein the pixels are not connected with the dummy data lines formed adjacent to the respective data lines.

18. A data driving method of a flat panel display device comprising the steps of: serially inputting each of a plurality of bits of digital data;executing charge sharing between respective data lines and dummy data lines formed adjacent to the respective data lines for a plurality of periods during which each of the plurality of bits of the digital data is input; andapplying a result of the charge sharing executed at a last one of the plurality of periods to corresponding ones of the pixels through the data lines as final gray scale voltages.

19. The data driving method of a flat panel display device as claimed in claim 18, wherein the charge sharing is executed by using respective parasitic capacitance components existing in the data lines and the dummy data lines formed adjacent to the data lines as a sampling capacitor and a holding capacitor.

20. The data driving method of a flat panel display device as claimed in claim 19, wherein the charge sharing evenly distributes a plurality of reference voltages stored in the sampling and holding capacitors for a period of each of the plurality of periods.