Digital average input current control in power converter

Information

  • Patent Grant
  • 8319483
  • Patent Number
    8,319,483
  • Date Filed
    Wednesday, August 6, 2008
    15 years ago
  • Date Issued
    Tuesday, November 27, 2012
    11 years ago
Abstract
A digital average-input current-mode control loop for a DC/DC power converter. The power converter may be, for example, a buck converter, boost converter, or cascaded buck-boost converter. The purpose of the proposed control loop is to set the average converter input current to the requested current. Controlling the average input current can be relevant for various applications such as power factor correction (PFC), photovoltaic converters, and more. The method is based on predicting the inductor current based on measuring the input voltage, the output voltage, and the inductor current. A fast cycle-by-cycle control loop may be implemented. The conversion method is described for three different modes. For each mode a different control loop is used to control the average input current, and the control loop for each of the different modes is described. Finally, the algorithm for switching between the modes is disclosed.
Description
BACKGROUND

The subject invention relates to control loops for switching converters. The following articles and patents, which may or may not be prior art, and which are incorporated here by reference, may be relevant to the subject invention.

    • Jingquan Chen, Aleksandar Prodic, Robert W. Erickson and Dragan Maksimovic, “Predictive Digital Current Programmed Control”. IEEE Transaction on Power Electronics, Vol. 18, No. 1, January 2003
    • U.S. Pat. No. 7,148,669, “Predictive Digital Current Controllers for Switching Power Converters” by Dragan Maksimovic, Jingquan Chen, Aleksandar Prodic, and Robert W. Erickson.
    • K Wallace, G Mantov, “DSP Controlled Buck/Boost Power Factor Correction for Telephony Rectifiers”. INTELEC 2001, 14-18 October 2001.
    • U.S. Pat. No. 6,166,527, “Control Circuit and Method for Maintaining High Efficiency in a Buck-Boost Switching Regulator” by David M. Dwelley, and Trevor W. Barcelo.


Additionally, the following basic text is incorporated here by reference, in order to provide the reader with relevant art and definitions:

    • Robert W. Erickson, Dragan Maksimovic, “Fundamentals of Power Electronics” (Second Edition), ISBN 0792372700.


SUMMARY

Aspects of the invention provide a method and system for digitally controlling the average input current in a non-inverting buck-boost converter. The method provides a fast cycle-by-cycle control loop to set the average input current when the converter is working in three different modes: buck, buck-boost and boost. Unlike analog control where it is difficult to change the parameters of the control loop in an adaptive manner, a digital control system can adjust the control loop parameters according to various parameters measured such as input voltage, output voltage and inductor current. In general, this enables to achieve a fast and stable control loop that controls the input current in various working points of the converter.


Aspects of the invention also provide for a method and system for digitally controlling the input current in a non-inverting (cascaded) buck-boost converter operating in a buck-boost mode, i.e., alternating between buck and boost in each cycle. Such an operation mode is particularly beneficial when the required converter output current is similar to the converter's input current. Since there are limits to the maximal and minimal allowed PWM values of the buck or boost operational modes, there are areas in which control is impossible without use of the alternating buck-boost mode.


Aspects of the invention further provide for a method and system for controlling the operational mode switching of a cascaded buck-boost converter. According to aspects of the invention, whenever the converter has been operated in one mode, i.e., buck or boost, for at least a predetermined period, and is needed to change into the other operational mode, i.e., to boost or buck, the transition is performed by forcing the converter to first execute several cycles on alternating buck and boost modes and only then switching to the other mode. Thus, for example, if the converter has been operating in a buck mode and is now to be switched to a boost mode, it is first switched to operate in an alternating buck-boost mode, in which the converter alternates by each cycle between buck and boost modes for several cycles, and only then switches to boost mode. This feature avoids the current jumps or discontinuities that are generally observed when a converter switches between buck and boost modes of operation.


Aspects of the invention further provide for a method and system for controlling the operation of a cascaded buck-boost converter, operable in one of three modes: buck, boost, and alternating buck-boost. The system includes three preprogrammed PWM control modules, each for controlling the input current according to one of the converter's operational modes. During operation of the converter, the operational mode is determined and the corresponding PWM control module is selected to control the input current.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 illustrate an example of a digital controlled non-inverting buck-boost converter according to aspects of the invention.



FIG. 2 illustrates the waveforms of trailing triangle PWM modulation.



FIG. 3 illustrates the waveforms of leading triangle PWM modulation.



FIG. 4 shows the inductor current waveform during two switching cycles using trailing edge triangle PWM modulation.



FIG. 5 illustrates a block diagram of predictive buck input current control, according to embodiment of the invention.



FIG. 6 illustrates the inductor current waveforms for a buck-boost switching cycle.



FIG. 7 illustrates the inductor current waveforms for a buck-boost switching cycle according to embodiment of the invention.



FIG. 8 shows a block diagram of control loops for buck-boost input current control, according to embodiment of the invention.



FIG. 9 shows a state diagram and the possible options to switch between the three different states.





DETAILED DESCRIPTION

A digital controlled non-inverting (cascaded) buck-boost converter, as described in FIG. 1, is a topology for a converter that is capable of both increasing the input voltage and decreasing it. The proposed topology is beneficial over prior art converters for at least the following reasons: 1) high conversion efficiency can be achieved; 2) component stress is relatively low as apposed to other buck-boost topologies; and 3) low component count—only one inductor, two capacitors and four switches. When buck-boost converters are discussed in this specification, we typically refer to cascaded buck-boost topology, sometimes named “non-inverting buck-boost” converter, rather then the lower efficiency (inverting) buck-boost converter.


While in general control loops of converters the inductor current is controlled, according to an embodiment of the invention, a control loop is provided in order to set the average input current to the requested current (Iref) Controlling the average input current can be relevant for various applications such as: power factor correction (PFC), photovoltaic inverters, and more. In this example, the control is based on predicting the inductor current for the next switching cycle based on measuring the input voltage ( VIn), the output voltage (VOut) and the inductor current (IL) in the current switching cycle. By using a predictive method a fast, cycle-by-cycle, control loop can be implemented.


Converter Modes


The cascaded buck-boost topology can achieve the desired input average current at various output currents. Depending on the output current, the converter can work in 3 different modes:

    • 1. Iref>Iout: Boost Converter—Switch A is constantly conducting and switch B is not conducting.
    • 2. Iref<Iout: Buck Converter—Switch D is constantly conducting and switch C is not conducting.
    • 3. Iref≈Iout: Buck-Boost Converter—All four switches are being used to control the input current.


Each of the three modes may have a different control schemes. The control loop will decide which control scheme is used at each switching cycle.


Predictive Average Input Current Control Using Triangle PWM Modulation


The control scheme of this example is based on predicting the inductor current for the next switching cycle based on measuring the inductor current and the input and output voltage. Based on the inductor current the control loop sets the average input current. Because of the fact that the predictive control loop is a non-linear control loop and it is executed on every PWM cycle, a high control bandwidth can be achieved.


The following sections will explain the concept of triangle PWM modulation and the three control schemes mentioned above.


Triangle PWM Modulation


There are two types of triangle PWM modulation—leading and trialing triangle modulation. FIG. 2 illustrates the waveforms of trailing triangle PWM modulation.


Each cycle, having length Ts and a duty cycle of d, starts with an on-time of length







d
2



T
s






an off-time of (1−d)Ts and another on-time of the same length. Leading triangle modulation is similar but the on-time and off-times are switched, as shown in FIG. 3. Both methods are suitable for input average current control because of the fact that the average inductor current is always at the beginning of each PWM cycle. This enables the digital control loop to sample the average inductor current at fixed intervals, at the beginning of each cycle.


Controlling Average Input Current Using the Inductor Current


The method of this example uses the inductor current to set the average input current when the converting is operating in continuous conduction mode (CCM). The converter can work in one of three different modes—Buck, Boost, Buck-Boost. For each mode there is a different equation for converting the average inductor current to the average input current in each switching cycle. Derived from the power train properties of the converter, the equations are:

    • 1. Boost: ĨInL
    • 2. Buck: ĨInL*d, where d is the duty cycle.
    • 3. Buck-Boost: ĨInL*dbuck where dbuck is the buck duty cycle


For all of the equations above ĨIn, ĨL denote the average input current and average inductor current, respectively.


Control Loops


The converter works in 3 different modes. For each mode a different control loop is used to control the average input current. This section will describe each control loop for the different modes. Later on, the algorithm for switching between the modes will be described.


Predictive Boost Input Current Control


The goal of the control loop is to insure that the average input current follows the reference Iref. As described above, when the converter operates in a boost mode the steady state average input current is the same as the average inductor current. In this mode the boost control will try to set the average inductor current to Iref. The required boost duty cycle for the next switching cycle is predicted based on the sampled inductor current, the input voltage and the output voltage. FIG. 4 shows the inductor current waveform during two switching cycles using trailing edge triangle PWM modulation. The sampled inductor current at switching cycle n, i(n), can be calculated using the previous sample, i(n−1), and the input and output voltage. The calculation is based on the inductor current slopes during the on-time and off-time.


Since the input and output voltage change slowly we assume that they are constant during a switching cycle. For a boost converter the on-time slope (m1) and off-time slope (m2) are given by the following equations:










m
1

=


V
in

L





(
1
)







m
2

=



V
in

-

V
out


L





(
2
)







Based on these equations we can predict i(n) using the following equation:











i
pred



(
n
)


=


i


(
n
)


=


i


(

n
-
1

)


+



V
in



d


[
n
]




T
s


L

+



(


V
in

-

V
out


)




d




[
n
]




T
s


L







(
3
)







Where d′[n]=1−d[n], Ts is the switching cycle time and L is the inductor inductance. Equation (3) can also be written as:











i
pred



(
n
)


=


i


(
n
)


=


i


(

n
-
1

)


+



V
out



d


[
n
]




T
s


L

+



(


V
in

-

V
out


)



T
s


L







(
4
)







We now have the prediction equation for one switching cycle. Because of the fact that every digital implementation of the control loop will have an execution delay, we will extend the prediction to one more switching cycle. So the prediction will set the duty cycle of the n+1 switching cycle based on the samples of the n−1 switching cycle. Extending equation (4) to two switching cycles we get:










i


(

n
+
1

)


=



i
pred



(
n
)


+



V
out



d


[

n
+
1

]




T
s


L

+



(


V
in

-

V
out


)



T
s


L






(
5
)







The prediction for the duty cycle d[n+1] can now be obtained based on the values sampled in the previous switching period. By substituting i(n+1) with the desired current Iref, in equation (5), and by solving the equation for d[n+1] we get:










d


[

n
+
1

]


=



(


I
ref

-


i
pred



(
n
)



)



L


T
s

*

V
out




+
1
-


V
in


V
out







(
6
)







Because of the fact that the inductor inductance can vary and to be able to achieve a slower control loop, we modify equation (6) with a variable gain that can be pre-adjusted, and we get:










d


[

n
+
1

]


=



(


I
ref

-


i
pred



(
n
)



)




L
*
K



T
s

*

V
out




+
1
-


V
in


V
out







(
7
)







Equation (7) is the control law when the converter is in boost mode.


If we denote Ti as the beginning time of each switching cycle (i), the above method samples the input voltage, output voltage, and inductor current at time T0, utilizes the time until T1 to predict the inductor current at T1 using the input voltage, output voltage and the knowledge of the inductor inductance, and calculate the needed duty-cycle in order to reach the desired input current (Iref) at T2, and set that duty cycle to be performed in the switching cycle between T1 and T2.


Predictive Buck Input Current Control


The principles of the predictive buck average input current control loop are similar to those of the boost current control loop. For the buck converter, the on-time and off-time inductor slopes are given by the following equations:










m
1

=



V
in

-

V
out


L





(
8
)







m
2

=

-


V
out

L






(
9
)







For switching cycle number n the average input current, based on the inductor current, is:











i
~



(
n
)


=


(


i


(

n
-
1

)


+


m





1


d


[
n
]



Ts

L

+


m





2



d




[
n
]



Ts

L


)

*

d


[
n
]







(
10
)







Based on equations (8) and (9) we can predict the inductor current for one switching cycle, and get the following equation:










i


(
n
)


=


i


(

n
-
1

)


+



(


V
in

-

V
out


)



d


[
n
]




T
s


L

-



V
out




d




[
n
]




T
s


L






(
11
)







Combining equations (10) and (11) we get:











i
~



(

n
+
1

)


=


(


i


(

n
-
1

)


+



V
in



d


[
n
]



Ts

L

-

2




V
out


Ts

L


+



V
in



d


[

n
+
1

]



L


)



d


[

n
+
1

]







(
12
)







The prediction for the duty cycle d[n+1] can now be obtained based on the values sampled in the previous switching period. Denoting the sampled current as is[n], and substituting the control objective ĩ(n+1)=Iref in (11), we have:











0
=




d
2



[

n
+
1

]


*



V
in



T
s


L


+


d


[

n
+
1

]


[


i


(

n
-
1

)


+



V
in



d


[
n
]




T
s


L

-

2




V
out



T
s


L



)



]

-

I
ref





(
13
)







Equation (13) is the control law when the converter is in buck mode. Because of the fact that this equation is a quadratic equation, one of the methods of solving it in an efficient manner is to use Newton Raphson method to approximate the solution.


If we denote Ti as the beginning time of each switching cycle (i), the above method samples the input voltage, output voltage, and inductor current at time T0, utilizes the time until T1 to predict the inductor current at T1 using the input voltage, output voltage and the knowledge of the inductor inductance, and calculate the needed duty-cycle in order to reach the desired input current (Iref) at T2, that is dependent on the inductor current and the duty cycle at T2, and set that duty cycle to be performed in the switching cycle between T1 and T2.


Predictive Buck Input Current Control—Alternative Embodiment


Another method for controlling the converter's input current in a buck converting is by controlling the inductor current and using the converter's input and output voltage to set the correct inductor reference value in an adaptive manner. FIG. 5 shows the block diagram of the control loops for this method. Equation 14 holds true in steady state in a buck converter:











I
~

in

=



V

out







V
in





I
~

L






(
14
)







By using equation (14) we can set the required inductor current (IL Ref) according to Vin and Vout in the following way:










I
L_Ref

=


I
ref

*


V
in


V
out







(
15
)







Equation (15) is the feed-forward block that runs every switching cycle. After calculating the cycle-by-cycle inductor current reference, an inductor current loop is used to set the required inductor current.


Predictive Buck Inductor Current Control


By using equation (11), extending it for two switching cycles and replacing i(n) with ipred(n) we get the following equation:











i


(

n
+
1

)





i
pred



(
n
)



+



V
in



d


[

n
+
1

]




T
s


L

-



V
out



T
s


L





(
16
)







By solving equation (16) for d[n+1] we get:










d


[

n
+
1

]


=



(


I
L_ref

-


I
pred



[
n
]



)



L


T
s

*

V
in




+


V
out


V
in







(
17
)







Because of the fact that the inductor inductance can vary and to be able to achieve a slower control loop, we modify equation (17) with a variable gain that can be pre-adjusted, and we get:










d


[

n
+
1

]


=



(


I
L_ref

-


I
pred



[
n
]



)




L
*
K



T
s

*

V
in




+


V
out


V
in







(
18
)







Equation (18) is the control law for the buck inductor current loop.


If we denote Ti as the beginning time of each switching cycle (i), the above method samples the input voltage, output voltage, and inductor current at time T0, utilizes the time until T1 to estimate the needed inductor current (ILRef) according to the input voltage, output voltage and desired input current (Iref). In addition, predicting the inductor current at T1 using the input voltage, output voltage and the knowledge of the inductor inductance, and calculate the needed duty-cycle in order to reach the needed inductor current (ILref) at T2, and set that duty cycle to be performed in the switching cycle between T1 and T2.


Predictive Cascaded Buck-Boost Input Current Control


When the converter is in buck-boost mode all four switches are being used to set the correct converter's average input current. This can be shown in FIG. 6 for trailing triangle PWM modulation. Switches B and D are complementary to switches A and C respectively. In each switching cycle both the buck and boost switches are being used to control the converter's average input current. In general, the boost switches will operate at a low duty cycle while the buck switches will operate at a high duty cycle.



FIG. 6 illustrates a method enabling the converter to set the converter's average input current correctly when the output current is relatively close to the reference current. In order to simplify the control loop the buck duty cycle will be fixed to a value, dbuck, and the control loop will set the boost duty cycle every switching cycle.



FIG. 7 illustrates the inductor current waveforms for a buck-boost switching cycle. The on-time and off-time inductor current slopes for the buck cycle and boost cycle are identical to the equations in (8), (9) and (1), (2). In addition, the average input current can be calculated from the average inductor current with the following equation:

ĨInL*dbuck   (19)


Based on all these equations the predictive control law can be built for calculating the required boost duty cycle:











i
~



(
n
)


=


(


i


(

n
-
1

)


+



(


V
in

-

V
out


)



d
buck



T
s


L

-



V
out



d
buck




T
s


L

+



V
in



d


[
n
]




T
s


L

+



(


V
in

-

V
out


)




d




[
n
]




T
s


L


)



d
buck






(
20
)







Denoting the sampled current as is[n] substituting the control objective ĩ(n)=iref in the equation above, and solving for d[n], we get the following:










d


[
n
]


=

2
+


(



i
ref


d
buck


-


i
s



[
n
]



)



L


V
out



T
s




-



V
in


V
out




d
buck







(
21
)







Equation (21) is the control law for setting the boost duty cycle when the converter is in buck-boost mode.


If we denote Ti as the beginning time of each switching cycle (i), the above method samples the input voltage, output voltage, and inductor current at time T0, utilizes the time until T1 to predict the inductor current at T1, based on the fact that the converter is in alternating buck-boost mode, using the input voltage, output voltage and the knowledge of the inductor inductance, and calculate the needed duty-cycle in order to reach the desired input current (Iref) at T2, and set that duty cycle to be performed in the switching cycle between T1 and T2.


Predictive Buck-Boost Input Current Control—Alternative Embodiment


Another method for controlling the converter's input current in a cascaded buck-boost converting is by controlling the inductor current and using the input and output voltage to set the correct inductor reference value in an adaptive manner. FIG. 8 shows the block diagram of the control loops for this method.


Predictive Buck-Boost Inductor Current Control


An efficient method of controlling the inductor current in a cascaded buck-boost converter is setting a linear relation between the boost and buck duty cycle in the following manner:

dbuck=1−c+dboost   (22)
Where:
0≦c≦1


Using equations (1), (2), (8) and (9) we can estimate the inductor at the end of switching cycle n:













i


(
n
)


=




i


(

n
-
1

)


+



(


V
in

-

V
out


)




d
buck



[
n
]




T
s


L

-



V
out




d
buck




[
n
]




T
s


L

+













V
in




d
boost



[
n
]




T
s


L

+



(


V
in

-

V
out


)




d
boost




[
n
]




T
s


L









i


(
n
)


=




i


(

n
-
1

)


+



V
in




d
buck



[
n
]




T
s


L

+













V
out




d
boost



[
n
]



Ts

L

+



(


V
in

-

2


V
out



)


Ts

L









(
23
)







Combining equations (22) and (23) and we get:











i
pred



(
n
)


=


i


(
n
)


=


i


(

n
-
1

)


+



V
in




d
boost



[
n
]




T
s


L

+



V
out




d
boost



[
n
]



Ts

L

+



(



V
in



(

2
-
c

)


-

2


V
out



)


Ts

L







(
24
)







By extending equation (24) to another switching cycle we get:










i


(

n
+
1

)


=



i
pred



(
n
)


+



V
in




d
boost



[

n
+
1

]




T
s


L

+



V
out




d
boost



[

n
+
1

]



Ts

L

+



(



V
in



(

2
-
c

)


-

2


V
out



)


Ts

L






(
25
)







Solving equation (25) for dboost[n+1] and replacing i(n+1) with the control objective, ILRef, we get:











d
boost



[

n
+
1

]


=



(


i
L_Ref

-

i


(

n
-
1

)



)

*


L
*
K



(


V
out

+

V
in


)

*
Ts



-


(



V
in



(

2
-
c

)


-

2


V
out



)



V
out

+

V
in








(
26
)







Equation (26) is the control law for the inductor current control in a cascaded buck-boost converter.


Feed Forward


In order to control the converter's input current, a cycle by cycle feed-forward is used in order to change the inductor current reference according to the required converter input current and input and output voltage. In a cascaded buck-boost converter we know that in steady state:











V
out


V
in


=


D
buck


1
-

D
boost







(

27

a

)









i
~

in



i
~

l


=

D
buck





(

27

b

)







Using equations (27) and (22) we can get:










i
L_Ref

=


i
ref





V
in

+

V
out




(

2
-
c

)



V
out








(
28
)







Using equation (28) we can set the required inductor current according to the desired input current and input and output voltages.


If we denote Ti as the beginning time of each switching cycle (i), the above method samples the input voltage, output voltage, and inductor current at time T0, utilizes the time until T1 to estimate the needed inductor current (ILRef) according to the input voltage, output voltage and desired input current (Iref). In addition, predicting the inductor current at T1 using the input voltage, output voltage and the knowledge of the inductor inductance, and calculate the needed duty-cycle in order to reach the needed inductor current (ILref) at T2, and set that duty cycle to be performed in the switching cycle between T1 and T2.


Switching Between Converter Modes


The converter needs to switch between three different modes depending on the reference current and the output current. FIG. 9 shows a state diagram and the possible options to switch between the three different states. The following sections will describe the logic from switching between the different states.


Switching From Buck Mode


When in buck mode, the duty cycle will be monitored every switching cycle. If the duty cycle is higher than the threshold set, 0<Thbucl<1, for more than Xbuck consecutive switching cycles the converter will switch to buck-boost mode.


Switching From Buck-Boost Mode


When in buck-boost mode, the duty cycle of the boost converter will be monitored every boost switching cycle (every second switching cycle). Two thresholds will be set—Thhigh and Thlow. If the duty cycle is higher than Thhigh for more than Xhigh consecutive switching cycles the converter will switch to boost mode. If the duty cycle is lower than Thlow for more than Xlow consecutive switching cycles the converter will switch to buck mode.


Switching From Boost Mode


When in boot mode, the duty cycle will be monitored every switching cycle. If the duty cycle is lower than the threshold set, 0<Thboost<1, for more than Xboost consecutive switching cycles the converter will switch to buck-boost mode.

Claims
  • 1. A method for switching between buck, boost, and alternating buck-boost modes of operation of a cascaded buck-boost converter, the converter comprising an inductor, the method comprising: if the converter is in boost mode and the duty cycle drops below a predetermined value for at least a first predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in buck mode and the duty cycle climbs above a second predetermined value for at least a second predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in alternating buck-boost mode, and the duty cycle climbs above a third predetermined value for at least a third predetermined number of cycles, transferring the converter to boost mode, while if the duty cycle drops below a fourth predetermined value for at least a fourth predetermined number of cycles, transferring the converter to buck mode;when the converter operates in a buck mode, controlling the input current according to a pre-programmed buck mode input current control;when the converter operates in a boost mode, controlling the input current according to a pre-programmed boost mode input current control; and,when the converter operates in an alternating buck-boost mode, controlling the input current according to a pre-programmed buck-boost mode input current control.
  • 2. A method for switching between buck, boost, and alternating buck-boost modes of operation of a cascaded buck-boost converter, wherein the converter comprises input terminals having input current and input voltage applied thereto and an inductor coupled to the input terminals, the method comprising: if the converter is in boost mode and the duty cycle drops below a predetermined value for at least a first predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in buck mode and the duty cycle climbs above a second predetermined value for at least a second predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in alternating buck-boost mode, and the duty cycle climbs above a third predetermined value for at least a third predetermined number of cycles, transferring the converter to boost mode, while if the duty cycle drops below a fourth predetermined value for at least a fourth predetermined number of cycles, transferring the converter to buck mode;when the converter operates in a buck mode, controlling the input current according to a pre-programmed buck mode input current control;when the converter operates in a boost mode, controlling the input current according to a pre-programmed boost mode input current control; and,when the converter operates in an alternating buck-boost mode, controlling the input current according to a pre-programmed buck-boost mode input current control;sampling current flowing in the inductor;sampling the input voltage;sampling output voltage output by the converter;digitally predicting the input current in a subsequent cycle based on the sampled current in the inductor, the sampled input voltage, and the sampled output voltage according to one of the pre-programmed buck mode input current control, boost mode input current control, or buck-boost mode input current control; andcontrolling duty cycle needed for reaching the desired input current at a subsequent cycle.
  • 3. A method for switching between buck, boost, and alternating buck-boost modes of operation of a cascaded buck-boost converter, wherein the converter comprises input terminals having input current and input voltage applied thereto and an inductor coupled to the input terminals, the method further comprising: if the converter is in boost mode and the duty cycle drops below a predetermined value for at least a first predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in buck mode and the duty cycle climbs above a second predetermined value for at least a second predetermined number of cycles, transferring the converter to alternating buck-boost mode;if the converter is in alternating buck-boost mode, and the duty cycle climbs above a third predetermined value for at least a third predetermined number of cycles, transferring the converter to boost mode, while if the duty cycle drops below a fourth predetermined value for at least a fourth predetermined number of cycles, transferring the converter to buck mode;sampling current flowing in the inductor;sampling the input voltage;sampling output voltage output by the converter;digitally predicting the input current in a subsequent cycle based on the sampled current in the inductor, the sampled input voltage, and the sampled output voltage; andcontrolling duty cycle needed for reaching the desired input current at a subsequent cycle.
  • 4. The method of claim 3, wherein controlling duty cycle comprises performing a triangle pulse width modulation (PWM).
RELATED APPLICATIONS

This Application claims priority from U.S. Provisional Application No. 60/954,261 filed on Aug. 6, 2007 and U.S. Provisional Application No. 60/954,354 filed on Aug. 7, 2007.

US Referenced Citations (333)
Number Name Date Kind
3369210 Menickella Feb 1968 A
3596229 Hohorst Jul 1971 A
4060757 McMurray Nov 1977 A
4101816 Shepter Jul 1978 A
4171861 Hohorst Oct 1979 A
4452867 Conforti Jun 1984 A
4460232 Sotolongo Jul 1984 A
4481654 Daniels et al. Nov 1984 A
4554515 Burson et al. Nov 1985 A
4598330 Woodworth Jul 1986 A
4623753 Feldman et al. Nov 1986 A
4637677 Barkus Jan 1987 A
4641042 Miyazawa Feb 1987 A
4641079 Kato et al. Feb 1987 A
4644458 Harafuji et al. Feb 1987 A
4652770 Kumano Mar 1987 A
4783728 Hoffman Nov 1988 A
4868379 West Sep 1989 A
4888063 Powell Dec 1989 A
4888702 Gerken et al. Dec 1989 A
4899269 Rouzies Feb 1990 A
4903851 Slough Feb 1990 A
4987360 Thompson Jan 1991 A
5045988 Gritter et al. Sep 1991 A
5081558 Mahler Jan 1992 A
5191519 Kawakami Mar 1993 A
5280232 Kohl et al. Jan 1994 A
5327071 Frederick et al. Jul 1994 A
5345375 Mohan Sep 1994 A
5402060 Erisman Mar 1995 A
5446645 Shirahama et al. Aug 1995 A
5460546 Kunishi et al. Oct 1995 A
5493154 Smith et al. Feb 1996 A
5497289 Sugishima et al. Mar 1996 A
5517378 Asplund et al. May 1996 A
5548504 Takehara Aug 1996 A
5604430 Decker et al. Feb 1997 A
5616913 Litterst Apr 1997 A
5644219 Kurokawa Jul 1997 A
5646501 Fishman et al. Jul 1997 A
5659465 Flack et al. Aug 1997 A
5686766 Tamechika Nov 1997 A
5773963 Blanc et al. Jun 1998 A
5777515 Kimura Jul 1998 A
5780092 Agbo et al. Jul 1998 A
5798631 Spee et al. Aug 1998 A
5801519 Midya et al. Sep 1998 A
5804894 Leeson et al. Sep 1998 A
5821734 Faulk Oct 1998 A
5822186 Bull et al. Oct 1998 A
5838148 Kurokami et al. Nov 1998 A
5869956 Nagao et al. Feb 1999 A
5873738 Shimada et al. Feb 1999 A
5886890 Ishida et al. Mar 1999 A
5892354 Nagao et al. Apr 1999 A
5905645 Cross May 1999 A
5919314 Kim Jul 1999 A
5923158 Kurokami et al. Jul 1999 A
5932994 Jo et al. Aug 1999 A
5933327 Leighton et al. Aug 1999 A
5945806 Faulk Aug 1999 A
5949668 Schweighofer Sep 1999 A
5963010 Hayashi et al. Oct 1999 A
5990659 Frannhagen Nov 1999 A
6031736 Takehara et al. Feb 2000 A
6038148 Farrington et al. Mar 2000 A
6046919 Madenokouji et al. Apr 2000 A
6050779 Nagao et al. Apr 2000 A
6078511 Fasullo et al. Jun 2000 A
6081104 Kern Jun 2000 A
6082122 Madenokouji et al. Jul 2000 A
6105317 Tomiuchi et al. Aug 2000 A
6111188 Kurokami et al. Aug 2000 A
6111391 Cullen Aug 2000 A
6111767 Handleman Aug 2000 A
6163086 Choo Dec 2000 A
6166455 Li Dec 2000 A
6166527 Dwelley et al. Dec 2000 A
6169678 Kondo et al. Jan 2001 B1
6219623 Wills Apr 2001 B1
6255360 Domschke et al. Jul 2001 B1
6256234 Keeth et al. Jul 2001 B1
6259234 Perol Jul 2001 B1
6262558 Weinberg Jul 2001 B1
6285572 Onizuka et al. Sep 2001 B1
6301128 Jang et al. Oct 2001 B1
6304065 Wittenbreder Oct 2001 B1
6320769 Kurokami et al. Nov 2001 B2
6339538 Handleman Jan 2002 B1
6351130 Preiser et al. Feb 2002 B1
6369462 Siri Apr 2002 B1
6380719 Underwood et al. Apr 2002 B2
6396170 Laufenberg et al. May 2002 B1
6433522 Siri Aug 2002 B1
6448489 Kimura et al. Sep 2002 B2
6452814 Wittenbreder Sep 2002 B1
6493246 Suzui et al. Dec 2002 B2
6507176 Wittenbreder, Jr. Jan 2003 B2
6531848 Chitsazan et al. Mar 2003 B1
6545211 Mimura Apr 2003 B1
6548205 Leung et al. Apr 2003 B2
6590793 Nagao et al. Jul 2003 B1
6593521 Kobayashi Jul 2003 B2
6608468 Nagase Aug 2003 B2
6611441 Kurokami et al. Aug 2003 B2
6628011 Droppo et al. Sep 2003 B2
6650031 Goldack Nov 2003 B1
6650560 MacDonald et al. Nov 2003 B2
6653549 Matsushita et al. Nov 2003 B2
6672018 Shingleton Jan 2004 B2
6678174 Suzui et al. Jan 2004 B2
6690590 Stamenic et al. Feb 2004 B2
6731136 Knee May 2004 B2
6738692 Schienbein et al. May 2004 B2
6765315 Hammerstrom et al. Jul 2004 B2
6768047 Chang et al. Jul 2004 B2
6788033 Vinciarelli Sep 2004 B2
6795318 Haas et al. Sep 2004 B2
6801442 Suzui et al. Oct 2004 B2
6850074 Adams et al. Feb 2005 B2
6882131 Takada et al. Apr 2005 B1
6914418 Sung Jul 2005 B2
6919714 Delepaut Jul 2005 B2
6927955 Suzui et al. Aug 2005 B2
6933627 Wilhelm Aug 2005 B2
6936995 Kapsokavathis et al. Aug 2005 B2
6950323 Achleitner et al. Sep 2005 B2
6963147 Kurokami et al. Nov 2005 B2
6984967 Notman Jan 2006 B2
6984970 Capel Jan 2006 B2
7030597 Bruno et al. Apr 2006 B2
7031176 Kotsopoulos et al. Apr 2006 B2
7042195 Tsunetsugu et al. May 2006 B2
7046531 Zocchi et al. May 2006 B2
7053506 Alonso et al. May 2006 B2
7072194 Nayar et al. Jul 2006 B2
7079406 Kurokami et al. Jul 2006 B2
7087332 Harris Aug 2006 B2
7090509 Gilliland et al. Aug 2006 B1
7091707 Cutler Aug 2006 B2
7097516 Werner et al. Aug 2006 B2
7126053 Kurokami et al. Oct 2006 B2
7126294 Minami et al. Oct 2006 B2
7138786 Ishigaki et al. Nov 2006 B2
7148669 Maksimovic et al. Dec 2006 B2
7158359 Bertele et al. Jan 2007 B2
7158395 Deng et al. Jan 2007 B2
7174973 Lysaght Feb 2007 B1
7193872 Siri Mar 2007 B2
7218541 Price et al. May 2007 B2
7248946 Bashaw et al. Jul 2007 B2
7256566 Bhavaraju et al. Aug 2007 B2
7277304 Stancu et al. Oct 2007 B2
7282814 Jacobs Oct 2007 B2
7291036 Daily et al. Nov 2007 B1
RE39976 Schiff et al. Jan 2008 E
7336056 Dening Feb 2008 B1
7348802 Kasanyal et al. Mar 2008 B2
7352154 Cook Apr 2008 B2
7371963 Suenaga et al. May 2008 B2
7372712 Stancu et al. May 2008 B2
7385380 Ishigaki et al. Jun 2008 B2
7385833 Keung Jun 2008 B2
7394237 Chou et al. Jul 2008 B2
7420815 Love Sep 2008 B2
7435134 Lenox Oct 2008 B2
7435897 Russell Oct 2008 B2
7471014 Lum et al. Dec 2008 B2
7504811 Watanabe et al. Mar 2009 B2
7589437 Henne et al. Sep 2009 B2
7600349 Liebendorfer Oct 2009 B2
7602080 Hadar et al. Oct 2009 B1
7605498 Ledenev et al. Oct 2009 B2
7646116 Batarseh et al. Jan 2010 B2
7719140 Ledenev et al. May 2010 B2
7748175 Liebendorfer Jul 2010 B2
7759575 Jones et al. Jul 2010 B2
7763807 Richter Jul 2010 B2
7780472 Lenox Aug 2010 B2
7782031 Qiu et al. Aug 2010 B2
7787273 Lu et al. Aug 2010 B2
7804282 Bertele Sep 2010 B2
7812701 Lee et al. Oct 2010 B2
7839022 Wolfs Nov 2010 B2
7843085 Ledenev et al. Nov 2010 B2
7868599 Rahman et al. Jan 2011 B2
7880334 Evans et al. Feb 2011 B2
7893346 Nachamkin et al. Feb 2011 B2
7900361 Adest et al. Mar 2011 B2
7919953 Porter et al. Apr 2011 B2
7948221 Watanabe et al. May 2011 B2
7952897 Nocentini et al. May 2011 B2
7960650 Richter et al. Jun 2011 B2
7960950 Glovinsky Jun 2011 B2
8003885 Richter et al. Aug 2011 B2
8004116 Ledenev et al. Aug 2011 B2
8004117 Adest et al. Aug 2011 B2
8013472 Adest et al. Sep 2011 B2
8077437 Mumtaz et al. Dec 2011 B2
8093756 Porter et al. Jan 2012 B2
8093757 Wolfs Jan 2012 B2
8111052 Glovinsky Feb 2012 B2
20010023703 Kondo et al. Sep 2001 A1
20020044473 Toyomura et al. Apr 2002 A1
20020056089 Houston May 2002 A1
20030058593 Bertele et al. Mar 2003 A1
20030066076 Minahan Apr 2003 A1
20030075211 Makita et al. Apr 2003 A1
20030080741 LeRow et al. May 2003 A1
20030214274 Lethellier Nov 2003 A1
20040041548 Perry Mar 2004 A1
20040061527 Knee Apr 2004 A1
20040125618 De Rooij Jul 2004 A1
20040140719 Vulih et al. Jul 2004 A1
20040169499 Huang et al. Sep 2004 A1
20040201279 Templeton Oct 2004 A1
20040201933 Blanc Oct 2004 A1
20040246226 Moon Dec 2004 A1
20050002214 Deng et al. Jan 2005 A1
20050005785 Poss et al. Jan 2005 A1
20050017697 Capel Jan 2005 A1
20050057214 Matan Mar 2005 A1
20050057215 Matan Mar 2005 A1
20050068820 Radosevich et al. Mar 2005 A1
20050099138 Wilhelm May 2005 A1
20050103376 Matsushita et al. May 2005 A1
20050105224 Nishi May 2005 A1
20050162018 Realmuto et al. Jul 2005 A1
20050172995 Rohrig et al. Aug 2005 A1
20050226017 Kotsopoulos et al. Oct 2005 A1
20060001406 Matan Jan 2006 A1
20060017327 Siri et al. Jan 2006 A1
20060034106 Johnson Feb 2006 A1
20060038692 Schnetker Feb 2006 A1
20060053447 Krzyzanowski et al. Mar 2006 A1
20060066349 Murakami Mar 2006 A1
20060068239 Norimatsu et al. Mar 2006 A1
20060108979 Daniel et al. May 2006 A1
20060113843 Beveridge Jun 2006 A1
20060113979 Ishigaki et al. Jun 2006 A1
20060118162 Saelzer et al. Jun 2006 A1
20060132102 Harvey Jun 2006 A1
20060149396 Templeton Jul 2006 A1
20060162772 Presher, Jr. et al. Jul 2006 A1
20060163946 Henne et al. Jul 2006 A1
20060171182 Siri et al. Aug 2006 A1
20060174939 Matan Aug 2006 A1
20060185727 Matan Aug 2006 A1
20060192540 Balakrishnan et al. Aug 2006 A1
20060208660 Shinmura et al. Sep 2006 A1
20060227578 Datta et al. Oct 2006 A1
20060237058 McClintock et al. Oct 2006 A1
20070044837 Simburger et al. Mar 2007 A1
20070075711 Blanc et al. Apr 2007 A1
20070081364 Andreycak Apr 2007 A1
20070147075 Bang Jun 2007 A1
20070159866 Siri Jul 2007 A1
20070164750 Chen et al. Jul 2007 A1
20070165347 Wendt et al. Jul 2007 A1
20070205778 Fabbro et al. Sep 2007 A1
20070227574 Cart Oct 2007 A1
20070236187 Wai et al. Oct 2007 A1
20070273342 Kataoka et al. Nov 2007 A1
20080024098 Hojo Jan 2008 A1
20080080177 Chang Apr 2008 A1
20080088184 Tung et al. Apr 2008 A1
20080097655 Hadar et al. Apr 2008 A1
20080106250 Prior et al. May 2008 A1
20080115823 Kinsey May 2008 A1
20080136367 Adest et al. Jun 2008 A1
20080143188 Adest et al. Jun 2008 A1
20080143462 Belisle et al. Jun 2008 A1
20080144294 Adest et al. Jun 2008 A1
20080147335 Adest et al. Jun 2008 A1
20080150366 Adest et al. Jun 2008 A1
20080164766 Adest et al. Jul 2008 A1
20080179949 Besser et al. Jul 2008 A1
20080236647 Gibson et al. Oct 2008 A1
20080236648 Klein et al. Oct 2008 A1
20080238195 Shaver et al. Oct 2008 A1
20080246460 Smith Oct 2008 A1
20080246463 Sinton et al. Oct 2008 A1
20090066399 Chen et al. Mar 2009 A1
20090073726 Babcock Mar 2009 A1
20090084570 Gherardini et al. Apr 2009 A1
20090097172 Bremicker et al. Apr 2009 A1
20090102440 Coles Apr 2009 A1
20090140715 Adest et al. Jun 2009 A1
20090141522 Adest et al. Jun 2009 A1
20090145480 Adest et al. Jun 2009 A1
20090146667 Adest et al. Jun 2009 A1
20090146671 Gazit Jun 2009 A1
20090147554 Adest et al. Jun 2009 A1
20090190275 Gilmore et al. Jul 2009 A1
20090206666 Sella et al. Aug 2009 A1
20090224817 Nakamura et al. Sep 2009 A1
20090237042 Glovinski Sep 2009 A1
20090237043 Glovinsky Sep 2009 A1
20090273241 Gazit et al. Nov 2009 A1
20090282755 Abbott et al. Nov 2009 A1
20090322494 Lee Dec 2009 A1
20100052735 Burkland et al. Mar 2010 A1
20100085670 Palaniswami et al. Apr 2010 A1
20100124027 Handelsman et al. May 2010 A1
20100139743 Hadar et al. Jun 2010 A1
20100214808 Rodriguez Aug 2010 A1
20100244575 Coccia et al. Sep 2010 A1
20100269430 Haddock Oct 2010 A1
20100282290 Schwarze et al. Nov 2010 A1
20100301991 Sella et al. Dec 2010 A1
20100308662 Schatz et al. Dec 2010 A1
20110006743 Fabbro Jan 2011 A1
20110043172 Dearn Feb 2011 A1
20110084553 Adest et al. Apr 2011 A1
20110114154 Lichy et al. May 2011 A1
20110121652 Sella et al. May 2011 A1
20110125431 Adest et al. May 2011 A1
20110133552 Binder et al. Jun 2011 A1
20110140536 Adest et al. Jun 2011 A1
20110181251 Porter et al. Jul 2011 A1
20110210611 Ledenev et al. Sep 2011 A1
20110254372 Haines et al. Oct 2011 A1
20110267859 Chapman Nov 2011 A1
20110271611 Maracci et al. Nov 2011 A1
20110273015 Adest et al. Nov 2011 A1
20110273016 Adest et al. Nov 2011 A1
20110285205 Ledenev et al. Nov 2011 A1
20110290317 Naumovitz et al. Dec 2011 A1
20110291486 Adest et al. Dec 2011 A1
20110316346 Porter et al. Dec 2011 A1
20120007613 Gazit Jan 2012 A1
20120032515 Ledenev et al. Feb 2012 A1
20120091810 Aiello et al. Apr 2012 A1
Foreign Referenced Citations (63)
Number Date Country
1309451 Aug 2001 CN
19737286 Mar 1999 DE
102005030907 Jan 2007 DE
102008057874 May 2010 DE
0419093 Mar 1991 EP
0420295 Apr 1991 EP
0604777 Jul 1994 EP
0756178 Jan 1997 EP
0827254 Mar 1998 EP
1330009 Jul 2003 EP
1503490 Feb 2005 EP
1531545 May 2005 EP
1657557 May 2006 EP
1657797 May 2006 EP
1887675 Feb 2008 EP
2048679 Apr 2010 EP
2249147 Mar 2006 ES
2249149 Mar 2006 ES
2480015 Nov 2011 GB
2480015 Dec 2011 GB
61065320 Apr 1986 JP
6165320 May 1986 JP
11041832 Feb 1999 JP
11103538 Apr 1999 JP
2003124492 Apr 2003 JP
2003-134667 May 2003 JP
2007-058845 Mar 2007 JP
WO 9313587 Jul 1993 WO
WO 9613093 May 1996 WO
9823021 May 1998 WO
WO 9823021 May 1998 WO
0000839 Jan 2000 WO
0021178 Apr 2000 WO
0075947 Dec 2000 WO
0231517 Apr 2002 WO
WO 03050938 Jun 2003 WO
WO 03071655 Aug 2003 WO
WO 2004023278 Mar 2004 WO
WO 2004090993 Oct 2004 WO
2004107543 Dec 2004 WO
2005076444 Aug 2005 WO
WO 2005076445 Aug 2005 WO
2006005125 Jan 2006 WO
2006007198 Jan 2006 WO
WO 2006078685 Jul 2006 WO
WO 2007006564 Jan 2007 WO
2007048421 May 2007 WO
2007073951 Jul 2007 WO
WO 2007084196 Jul 2007 WO
2007090476 Aug 2007 WO
WO 2007113358 Oct 2007 WO
2008132551 Nov 2008 WO
2008132553 Nov 2008 WO
2009051853 Apr 2009 WO
2009118682 Oct 2009 WO
2009118683 Oct 2009 WO
2009136358 Nov 2009 WO
2010065043 Jun 2010 WO
2010065388 Jun 2010 WO
2010072717 Jul 2010 WO
2010134057 Nov 2010 WO
2011011711 Jan 2011 WO
2011017721 Feb 2011 WO
Related Publications (1)
Number Date Country
20090039852 A1 Feb 2009 US
Provisional Applications (2)
Number Date Country
60954261 Aug 2007 US
60954354 Aug 2007 US