DIGITAL BIOPOTENTIAL ACQUISITION SYSTEM HAVING 8 CHANNELS

Abstract

A biocompatible recording system includes a number of input channels for acquiring electronic information from the neural system of a living being. The recording system includes a preamplifier and further amplifier stages. An input of a second amplifier stage is coupled to an output of the preamplifier. A low-pass filter having a capacitance multiplier is connected to the second amplifier stage. The preamplifier of the recording system is designed using P-MOS technology.

Description

FIELD

The invention relates to a biocompatible, neural implant for recording neural signals in a living being. In particular, the present invention discloses an acquisition system for neural signals within a chip for implantation in a living being.

BACKGROUND

A biopotential is an electrical potential that is measured between points in living cells, tissue and organisms and occurs in connection with all biochemical processes. It also describes the transfer of information between and within cells. It is an electrical quantity (voltage, current or field strength) that is caused by chemical reactions of charged ions. The term is further used in the description of the transfer of information between and within cells, for example in signal transmission.

Neural implants can electrically stimulate, capture and block (or even simultaneously capture and stimulate) signals from individual neurons or groups of neurons (biological neural networks) in a living being.

The present invention discloses the design and test of an integrated CMOS biopotential acquisition chip having 8 channels and consisting of a low-noise amplifier (LNA), a second stage, a multiplexer and two analogue-to-digital converters (ADC).

Due to its variable power consumption, the integrated noise of the first stage can be reduced from 1.94 to 0.693 μV_RMS (I_SS=250 μA). The device has variable lower and upper corner frequencies and outputs two 16-bit digital data streams at 1 Mb/s.

The chip die is manufactured in X-Fab 0.35 μm CMOS technology and has an area of 10 mm².

Neural implants are devices that support the treatment of diseases such as Parkinson's disease, hearing impairments and heart defects.

Such devices connect the neural system by electrical stimulation to induce a reaction of the body. For example, cochlear implants stimulate the auditory nerve to create the sensory impression of hearing, pacemakers stimulate the inner wall of the heart to trigger heart muscle contractions, and deep brain stimulators generate signals that prevent unwanted muscle twitches caused by Parkinson's disease.

Medical research aims to understand how neural implants should affect the neural system. Normally, large recording systems are used in experiments on humans and animals that make it possible to visualize and process signals from the brain or nerves. Current experiments show a clear tendency towards the use of implantable acquisition systems, as they are one step closer to the reality of medical implants.

Depending on the type of application, bioelectric signals cover a wide range of amplitudes, noise levels and frequency bands. For this reason, a recording system that can adapt its properties to the respective applications is extremely desirable.

Ghovanloo shows a system with an extremely low power consumption that can detect brain signals and includes a variable bandwidth and radio transmission. M. Yin and M. Ghovanloo, “A low-noise clockless simultaneous 32-channel wireless neural recording system with adjustable resolution,” Analog Integrated Circuits and Signal Processing, vol. 66, no. 3, S. 417-431, ISI:000287319400010, 2011. Harrison et al. shows a versatile acquisition amplifier which has proven itself in the case of brain action potentials, electroencephalography (EEG), electrocardiography (ECG) and electromyography (EMG).

A disadvantage of these acquisition systems is their noise level of 4 μV_RMs and 2 l μV_RMS each, which is relatively high in applications with EEG and electroneurography (ENG).

Amplifiers also generate noise, which is divided into thermal noise and flicker noise.

The thermal noise density is constant with respect to the frequency and is proportional to the equivalent resistance of the transistor.

The flicker noise density, on the other hand, depends on the frequency with a factor of 1/f and is inversely proportional to the transistor surface.

Some effort has already been put into overcoming noise limitation. A notable work is represented by the BJT input transconductance operational amplifier (OTA) for ENG, proposed by R. Rieger and N. Donaldson.

Since BJT transistors do not generate flicker noise, the resulting input-related noise of 300 nV_RMS is significantly lower than that of previous amplifiers. However, this architecture has two serious disadvantages:

• • 1. It has a residual DC current of 20 nA from the electrode-tissue interface, which in the long term can lead to corrosion at the contacts, and
  • 2. The technology is “open loop”, which causes the gain to be a random variable, which may be a problem for the “True Tripole arrangement” used for a cuff electrode recording.

In addition, a chopper structure was proposed that shifts the signal to a frequency at which the flicker noise is negligible. The signal is then demodulated without flicker noise. Unfortunately, the chopper amplifier needs at least ten times more bandwidth to ensure that the signal is sufficiently far away. This requirement increases the power consumption of the amplifier.

SUMMARY

The present invention shows a versatile, low-noise amplifier to achieve an input noise level of sub-μV_RMS. The applied approach to noise reduction consists in an appropriate transistor size and power and in using PMOS input transistors with a lower flicker noise constant. The present system shown in FIG. 1 has 8 bipolar input channels and two independent serial digital outputs with two 10-bit ADCs.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 is a block diagram of a recording system in accordance with the present disclosure;

FIGS. 2A and 2B are diagrams of an architecture in accordance with the present disclosure;

FIG. 3 is a graph of performance curves for predefined noise behavior;

FIG. 4 is a block diagram of a second stage in accordance with the present invention;

FIG. 5 is another block diagram of a second stage in accordance with the present invention;

FIG. 6 is a block diagram of a control current capacitance multiplier;

FIG. 7 is a block diagram of signal paths from amplifier outputs to serial digital outputs;

FIG. 8 is a schematic image of a chip with 8 bipolar input channels in accordance with the present disclosure;

FIG. 9 is a diagram of I/O pins of an LNA8 chip in accordance with the present disclosure;

FIG. 10A is a graph showing variation of lower cut-off frequency via VTune in accordance with the present disclosure;

FIG. 10B is a graph showing variation of upper cut-off frequency via control of the bas VGC+ of the capacitance multiplier in accordance with the present disclosure;

FIG. 11 is a first graph showing frequency versus magnitude in accordance with the present disclosure;

FIG. 12A is a second graph showing frequency versus magnitude in accordance with the present disclosure;

FIG. 12B is a third graph showing frequency versus magnitude in accordance with the present disclosure;

FIG. 12C is a graph showing frequency versus phase in accordance with the present disclosure;

FIG. 13 is a graph showing measured curves in comparison to schematic and analog extracted simulations;

FIG. 14 is a graph showing total integrated input noise for different amplifier configurations;

FIG. 15A is an image of three successive contractions of an exemplary biceps by EMG detection;

FIG. 15B is an image of three successive contractions of an exemplary biceps by ECG detection;

FIG. 16 shows a comparison of a low-noise amplifier (LNA) according to the present disclosure with other systems;

FIG. 17A are diagrams based on the source neural impulse and muscular impulse; and

FIG. 17B are diagrams based on image action potential and action current.

DETAILED DESCRIPTION

LNA Preamplifier

It is known that the first stage (preamplifier) is the most important stage in an amplifier chain, as it is the component which is most susceptible to noise. For this reason, a fully-differential telescopic architecture has been used.

The architecture shown in FIGS. 2a and 2b provides high gain and bandwidth in a single stage and theoretically an infinite common mode rejection ratio (CMRR) and infinite noise suppression (PSRR).

The equations of the amplifier channels are known, and rephrased for the g_m/I_D design methodology, the noise model is as follows:

$\begin{array}{cc}\stackrel{\_}{V_{n,\mathrm{in}}^z}=\frac{16\mathrm{kT}\left(\Delta f-1\right)}{3{\left(\frac{g_m}{I_D}\right)}_{1.2}}\left(1+\frac{{\left(\frac{g_m}{I_D}\right)}_{7.0}}{{\left(\frac{g_m}{I_D}\right)}_{1.2}}\right)\frac{1}{I_D}+\frac{2\ln \Delta f}{C_{\mathrm{ox}}}\left(\frac{K_n}{{\left(\mathrm{WL}\right)}_{1.2}}+{\frac{K_p}{{\left(\mathrm{WL}\right)}_{7.8}}\left[\frac{{\left(\frac{g_m}{I_D}\right)}_{7.0}}{{\left(\frac{g_m}{I_D}\right)}_{1.2}}\right]}^2\right)& \left(1\right)\end{array}$

And the transfer function:

$\begin{array}{cc}H\left(s\right)=2\frac{C_{\mathrm{IN}}}{C_F}\frac{\frac{s}{2\pi f_{\mathrm{cL}}}}{\left(1\begin{array}{c}s\\ 2\pi f_{\mathrm{cL}}\end{array}\right){\left(1\begin{array}{c}s\\ 2\pi f_{\mathrm{cL}}\end{array}\right)}^{\prime }}\mathrm{with}& \left(2\right)\\ f_{\mathrm{cL}}=\frac{1}{2\pi R_FC_F};f_{\mathrm{cU}}=\frac{C_F}{C_{\mathrm{IN}}}\frac{g_{m1,2}}{\pi C_I}=\frac{C_F}{C_{\mathrm{IN}}}\frac{\sqrt{{\beta }_{1,2}}}{\pi C_L}\sqrt{I_{\mathrm{SS}}}& \left(3\right)\end{array}$

Legend:

Kn	Glitter noise constant	NMOS	120 × 10−24 V2F
Kp	Glitter noise constant	PMOS	20 × 10−24 V2F
k	Boltzmann's constant		1,3806 × 10−23 m2kg/s2K
(1)
V2n, in	Total input noise	VRMS
k	Boltzmann's constant	l
T	Temperature	K
gm	Transconductance	A/V
ID	Current level at drain terminal	A
(2)
CIN	Input capacity	F
CF	Feedback capacity	F
fcL	lower corner frequency	Hz
fcU	upper corner frequency	Hz
(3)
RF	Feedback resistance	Ω
β	MOSFET transistor current amplification	A/V2
ISS	Polarization current for FD telescope amplifier	A

Using the PMOS transistors and the optimal point marked in FIG. 3, the variables shown in Table 1 below were determined:

TABLE 1
Variables of the PMOS FD telescope amplifier
	FD-telescopic
	Parameter
	Variables	W [μm]	L [μm]
	M1, 2	8000	1.5
	M3, 4	1728	0.5
	M5, 6	168	1
	M7, 8	288	24
	Load capacity	30.5 pF
	Bias current Iss	205 μA
	Active surface	0.04 mm2
	Layout surface	0.15 mm2
	Channel surface	2028 × 720 μm2

Second Stage

The second stage shown in FIG. 4 is responsible for the conversion from FD (fully differential) to single-ended, with an input noise in an amount of 6 μV_RMS for a power consumption of 148 μW (11 μV_RMS and 46 μW in LP mode). Due to feedback, it delivers a gain of either 0 dB or 20 dB. The OTA consists of a single-ended 2-stage Miller amplifier.

In the field of electronics, the Miller effect is the increase in the equivalent input capacitance of an inverting voltage amplifier due to the amplification of the effect of the capacitance between the input and output terminals. The apparently increased input capacity due to the Miller effect results as follows:

C _M =C(1+A_v)

where −A_v is the gain and C is the feedback capacitance.

Although the term Miller effect usually refers to capacitances, any impedance connected between the input and another node showing gain can modify the amplifier input impedance with this effect.

Low-Pass Filter with Capacitance Multiplier

Since different applications require different upper corner frequencies fcu, a variable RC low-pass filter has been integrated.

In one reference, this variation was achieved by adjusting the LNA bias current Iss, creating a variation of the noise behavior. O. F. Cota, et al., “In-vivo characterization of a 0.8-3 \muV RMS input-noise versatile CMOS pre-amplifier,” Neural Engineering (NER), 2015 7th International IEEE/EMBS Conference on, 2015, S. 458-461. To avoid this unwanted coupling, a capacitance multiplier was proposed which uses the control current OTA from J. Ramirez-Angulo, et al., “Gain programmable current mirrors based on current steering,” Electronics Letters, vol. 42, no. 10, S. 559-560, 2006 and which is connected to the second stage as is described in J. A. Ruiz, et al., “Three novel improved CMOS capacitance scaling schemes,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, S. 1304-1307. The capacitance multiplication factor (from 50 pF to 5 nF) is set by the differential input V_GC±, the bias current of 56 μA and an area of 0.013 mm².

MUX, Analog-to-Digital Converter and Serial Output

The chip uses the X-Fab 0.35 μm library 10-bit SAR-ADC and integrates a user-defined flip-flop-based parallel-serial converter. The 16-bit little-endian output is combined as in J. Ramirez-Angulo, S. R. Garimella, A. J. López-Martin, and R. G. Carvajal, “Gain programmable current mirrors based on current steering,” Electronics Letters, vol. 42, no. 10, S. 559-560, 2006, where S represents the start token bits (H L), bits C3-C0 represent the channel number and bits D9-D0 represent the ADC sample values.

Power Consumption

The power consumption of the chip is summarized in Table 2:

TABLE 2
		2 St +	Cap. mult.		Total (sim)
(*sim values)	1 St [mW]	Bias.	(mW)	ADCs	mW
29	μA	0.765	2.03	1.19	0.495	4.49
29	μA LP		1.23	(optional)		3.68
210	μA	5.54 mW	2.03	1.19		9.26
210	μA		1.23	(optional)		8.46
271	μA	7.15 mW	2.03	1.19		10.87
271	μA		1.23	(optional)		10.06

Result

The chip shown in FIG. 8 is manufactured using X-Fab 0.35 μm technology. The amplifier I/O pins are summarized in Table 2. The system pins offer flexibility for the parameters:

• • Enable function: continuous ISS variation, second stage low-power (LP) mode, capacitance multiplier, 20 dB gain
  • Bias voltage: V_{REF_ISS}, V_{REF_CMFB}
  • Frequency range variation: V_GCP/N, V_TUNE

Although the chip is designed for digital output, it contains test pins to support its characterization, such as the analog outputs of the preamplifier and the low-pass filter of channels 1 and 5.

Table 3, below, shows I/O pins of the LNA8 chip. Underlined pins represent outputs.

	TABLE 3
	Analog		Digital
	(D, A)VDD	3	ISS(T1-T4)	4
	(D, A)VSS	3	V_REF_ISS_EN
	VREF ISS		LP EN
	VIN(N/P)(1-8)	16	RESET EN
	VREF CMFB		GAIN_0dB_EN
	VGCP/N	2	CAP MULT EN
	VTUNE		CLK
	VREFH		CHSEL0-3	4
	VREFL		DSOUT(½)	2
Test (analog)
	VEXTCMFB
	VDDISS(1, 5)	2
	V OUTN/P(1, 5)	2
	V OUT1/5	2
Test (digital)
	RESET ADC
	Q1 0-3	4
	EOC1
	SW1

The ADCs can be clocked with two serial digital outputs up to 1 MHz.

Frequency Response

The LNA8 recording system has variable corner frequencies fcU, fcL in each case by varying the potentials V_TUNE and V_GC±.

Noise Behavior

The spectral noise density of the amplifier was measured for different bias currents and bandwidth setting voltages.

The graphical representation in FIG. 13 shows the measured curves in comparison to the schematic and analog extracted simulations. FIG. 14 shows the total integrated input noise for different amplifier configurations. The curve shows a minimum noise of *(sim. value) 0.6 V_RMS for I_SS=250 μA.

In Vivo Recording

The acquisition system has been tested with bioelectric in-vivo signals as shown in FIG. 15. The bioelectric signals were extracted directly from the serial digital outputs using SPI decoding. The SPI bus (Serial Peripheral Interface) is a synchronous, serial communication interface specification used for short-range communication. SPI devices can communicate with a single master in full duplex operation using a master-slave architecture. The master device generates the frame for reading and writing. A multitude of slave devices are supported by selection with individual slave select lines (SS).

FIG. 15A shows three successive contractions of an exemplary biceps EMG detection. FIG. 15B shows an ECG detection.

The foregoing description shows the implementation of a biopotential acquisition system with 8 channels.

Although the best noise efficiency factor is achieved by the design that uses BJT transistors, this has the disadvantage that a residual DC current of 20 nA remains, which can lead to electrode corrosion in the long run.

The capacitance multiplier fulfilled its function of providing a wide range for the upper cut-off frequency.

However, since it was dimensioned for minimum area and power consumption, the noise behavior could not be kept below 1 μV_RMS without a capacitance multiplier; the noise behavior can be maintained by software filtering.

Table 4 shows a comparison of the shown low-noise amplifier (LNA) with other systems.

TABLE 4
System	Amplification/db	Noise/μVRMS	Power/Channel/μW	fcL/Hz	fcU/Hz	CMRR/db	NRF
M. Yin and M.	40; 77	4.9	49	0.01-1k	700-10k	139	7.84
Ghovanloo
J. Taylor and	80	0.291	2400	(5 V)	DC	5k	82	3.57
R. Rieger
F. Zhang,	40	2.2	12	(IV)	0.3	10k	80	2.9
et al.
[9]	>100	1.9(10 kHz)	576	(1.8 V)	DC	20k	>99	12.9
Before O. F.	41-45	0.8-2.7	3.3-3300	0.2-10k	38-11k	78	8.9-15
Cota, et al.
Present	39.3 or	1.94-0.69*	303-1200*	0.1-10k	200-20k	60.3; 74	3.52 (1. stage)
Design	58.4	(sim val)	(sim)				6.57 (2. stage)

Compared to the previous work in O. F. Cota, et al., the present design integrated the other blocks of the desired system.

The amplifier area has been reduced by a factor of four and an analog output.

Result

The invention shows the successful implementation and the testing of a versatile bioelectric signal acquisition chip with 8 channels. The amplified channels are selected from two analog multiplexers and are output by two SPI-compatible 16-bit data streams. The total integrated input noise can be reduced to *(sim. value) 0.6 μV_RMS for bandwidths between 1 Hz and 10 kHz. The acquisition system has been tested for ECG and EMG applications.

Claims

1. A biocompatible recording system for acquiring electronic information from the neural system of a living being, the recording system comprising: a first amplifier stage comprising a preamplifier;a second amplifier stage, wherein an input of the second amplifier stage is coupled to an output of the preamplifier; anda low-pass filter having a capacitance multiplier connected to the second amplifier stage.

2. The recording system according to claim 1, wherein the preamplifier uses P-MOS input transistors in the first amplifier stage.

3. The recording system according to claim 1, wherein the recording system can acquire at least two signals independently of one another with at least two recording channels.

4. The recording system according to claim 1, wherein the recording system has variable lower (fcL) and upper (fcU) corner frequencies by variation of predetermined signals.

5. The recording system according to claim 2, wherein the first amplifier stage comprises a fully-differential telescopic architecture.

6. The recording system according to claim 1 comprising a flip-flop-based parallel-serial converter that is integrated into the recording system.