Patent Application
20180196452
The present invention relates to a digital calibration method for a low power voltage reference generator.
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single integrated circuit (“IC”), or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Non-volatile solid-state memory systems are widely used in a variety of mobile and handheld devices, notably smart phones, tablets, laptops, and other consumer electronics products. Solid state memory, which can include embedded or stand-alone charge-based flash memory, phase change memory, resistive RAM (“RRAM”), or magneto-resistive memory (“MRAM”), is of particular advantage for battery operated mobile devices that have limited available power. Typically, electronic systems in such devices have processors, microcontrollers (“MCUs”), or other electronic controllers that support architected power states (e.g., an active state, a stand-by or sleep state, a deep sleep state, etc.). As compared to active states, the power consumption in these electronic systems can be significantly reduced when the device is maintained in stand-by or sleep states.
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Nano-amp reference voltage generators are known which can achieve +/−20% of total variation over process, voltage, and temperature, while consuming only 1 nA of quiescent current. This variation can be reduced to approximately +/−5% by calibrating process and mismatch errors at production test. While +/−5% may be sufficient for some applications, it may still limit the design of downstream circuits by, inter alia:
In order to achieve +/−5% accuracy over supply and temperature, the inherent process and mismatch-induced errors in the reference need to be reduced. Modern implementations often use digital trimming for this purpose.
Although “At Test” trimming is effective in many ways, it is unable entirely to remove some sources of error that may still degrade the performance of a reference generator in the field, including:
What is needed is a method and apparatus for trimming the reference voltage during operation in the field.
In accordance with a first embodiment, a method is provided for digitally calibrating, selectively during normal operation, a reference signal generator adapted to develop an analog reference signal as a function of a digital control signal. In this embodiment, the method first develops a digital reference signal as a function of the analog reference signal. A digital ideal reference signal is also developed. Finally, the digital control signal is developed as a function of a difference between the digital reference signal and the digital ideal reference signal.
In accordance with another embodiment, a reference signal generator facility is configured to perform the above method.
In accordance with one other embodiment, an electronic system comprises this reference signal generator facility.
In accordance with yet another embodiment, a non-transitory computer readable medium includes executable instructions which, when executed in a processing system, causes the processing system to perform the steps of the above method.
The invention may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:
In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that the invention requires identity in either function or structure in the several embodiments.
In order to correct for the low-frequency components of the several errors noted above, the embodiment shown in
Once the calibration cycle is complete, the ADC and bandgap reference can be powered down to save power. Since this calibration loop will typically be employed only to correct for very low frequency errors, a calibration cycle can be performed once a second or even less frequently. If the ADC and bandgap reference only need to be powered up for 1 μs, the duty-cycling of these blocks over a 1 second period means their contribution to the average power of the chip is only 1/1,000,000th of their active power.
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It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Thus, it is intended that the disclosed embodiments cover modifications and variations that come within the scope of the claims that eventually issue in a patent(s) originating from this application and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined in whole or in part.
