The present invention relates generally to signal measurement, and more particularly to a digital AC voltage measurement device and method.
Many practical applications require the measurement of AC signal metrics. Typical metrics of interest include peak and root mean square voltage measurements of AC signals.
For example, alarm systems and universal power supplies monitor input voltages to ensure they do not deviate significantly. Certain measuring equipment used by technicians similarly measures AC voltages. Often a digital representation of such measurements is advantageous, as the digital representation can be further processed, or more clearly presented.
Unfortunately, determining a digital value corresponding to a measured AC voltage often requires floating point calculations (e.g. division). This, in turn, requires certain processing abilities and accuracies.
As such, simplified circuits and associated methods for measuring AC voltage metrics, and in particular AC RMS voltages are desired.
Exemplary of an embodiment of the present invention, an AC measurement circuit includes a rectifier for receiving an AC signal; a peak detection circuit; and a voltage divider, interconnected with an output of the rectifier, and the input of the peak detection circuit to provide the peak detection circuit with a voltage value equal to a fraction of the AC signal. An analog to digital converter, has its analog input interconnected with an output of the peak detection circuit, for providing a digital output corresponding to its analog input. A summing circuit sums n samples of the digital output. The voltage divider is configured so that the summing circuit calculates an average measurement of the AC signal by summing n samples and without requiring floating point division.
In a further embodiment, a method of measuring an AC input voltage, includes providing the AC signal to a rectifier to provide a rectified output; providing the rectified output to the input of a voltage divider that outputs a fraction of the rectified output; detecting a peak of the output of the voltage divider over time; sampling the peak of the output at an analog to digital converter to produce a digital value; and summing n of the digital values. The voltage divider is configured so that an average measurement of the AC signal is calculated by summing the n of the digital values without requiring floating point operations (e.g. division).
Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.
In the figures which illustrate by way of example only, embodiments of the present invention,
Bridge rectifier 12 receives a sinusoidal AC voltage, VAC(t), from source 14 as depicted in
Voltage divider 16 further presents a fraction of the rectified voltage to the input of peak detection circuit 18, to present
Peak detection circuit 18 detects the peak of any voltage presented at its input (i.e. the peak of VRECT). Peak detection circuit 18 may be formed as an operational amplifier 30, having its inverting input connected in feedback, a capacitor 32 connected to ground at the inverting input, to store any applied voltage and provide output voltage VIN
The output VIN
Buffer 28 may be in communication with a summing circuit, which may be part of a processor 26 such as a microcontroller, digital signal processor (DSP) or other processor. Processor 26 may sum samples provided by ADC 20 stored in buffer 28. ADC 20 may also be part of the processor/microcontroller and the microcontroller would perform the summing function. Processor 26 may include, or be otherwise in communication with, suitable memory for storing program instructions, and samples. Buffer 28 may be formed in such memory.
The input of peak detection circuit 18, VIN(t) may not have the same range as VAC(t) provided by source 14. For example, peak detection circuit 18 may have an operating range of less than 5 V, while source 14 may provide a 16, 18 or 120 VAC signal.
Voltage divider 16, as such, reduces the voltage provided to peak detection circuit 18. Thus, the input to peak detection circuit 18 may be determined as a fraction of VRECT, that is VIN=η·VRECT. Accounting for the voltage drop across diodes 22, VIN(t)=η·(VAC(t)−VOFFSET). VPK is the peak voltage of VAC(t), provided by source 14. Thus, VIN
ADC 20 may be continuously provided the output of peak detection circuit 18. Under control of processor 26, ADC 28 samples this output, VIN
The sampled values may be used to calculate an average measurement of VPK, VPK
To do so, circuit 10 relies on the observation that
VOFFSET (the drop across diodes 22) can be considered constant, so,
V
OFFSET
=V
OFFSET[1]=VOFFSET[2]= . . . =VOFFSET[n] (2)
Now, the digital average of n samples, ADC_OUTAVG (for n samples) is defined as
This means:
The average of VPK, VPK
Dividing the both sides of equation (4) by η yields,
This allows calculation of RMS voltages as
Now, by selecting
to equal or approximate integer, e.g.
Thus, if RMS voltage is to be measured,
may be chosen to equal an integer (e.g. 1) to avoid floating point division.
That is, by so choosing n and η, only addition is required to calculate the average because of the resistor divider ratio of voltage divider 16.
η may further be selected to accommodate the maximum input voltage at the input of ADC 20 in order to maximize the dynamic range of the measurement and maximize measurement resolution. This means, the maximum peak voltage at the input VPK, after division should be close to the maximum range of the ADC 20 which measures the peak voltage.
Now, n, is the number of samples to be taken to determine the average voltage. A suitable value for n may be chosen based on the input voltage range to be measured.
For example n may be chosen, so that
where VPK is the maximum peak expected value of voltage source 14 VAC, VADC
Now, VOFFSET introduced by diodes 22 may be calibrated and stored. Thereafter, the past n samples of the AC RMS or AC peak voltage may be continuously averaged, as described above. VOFFSET can be a constant in the processor memory that is added to ADC_OUTAVG. To allow averaging of the past n samples of peak detection circuit 18, buffer 28 may be a circular buffer.
After each sample, the circular buffer may be advanced, and thus store the previous n samples of ADC 20, with the n+1st sample replacing the 1st sample in the buffer. This would allow constant averaging at each AC half cycle, using the past n samples, independent of the choice of n. As noted, the buffer 28 may be formed in memory used by the described processor 26.
For example: if VAC(t) provided by source 14 is an 18 volts AC (RMS) input signal with a 15% overvoltage, the maximum input voltage would be 20.7 VAC(RMS). VPK of 20.7 VAC(RMS)=20.7*√2=29.274 V. Assuming ADC 20 has a dynamic range of 2.8 volts, the number of samples n may be chosen as:
This then allows choice of η, the resistor divider ratio for peak detection circuit 18, as:
Thus the resistor divider ratio would be 1:11.3137 and the voltage across R3 would be related to the ratio η=R3/(R1+R3)=0.088388.
Because of this resistor divider ratio, only eight samples of peak detection circuit 18 need to be added to produce the RMS voltage to be measured. Correspondingly, a sample and hold buffer need only store eight samples.
Conveniently, averaging the voltage value over “n” samples (RMS or peak) reduces any instantaneous errors. It further compensates the voltage drop across rectifier 12, thereby providing greater accuracy.
Conveniently, the calculation requires only summing, and thus allows for quick AC voltage evaluation without requiring division, shifts, or floating point calculations. Further, sampling interval/period of ADC 20 need not be overly precise—peak detection circuit 18, instead, ensures that peak values are sampled. Sampling and averaging can be performed only once every half period, and averaging can be performed at the same frequency. The described technique is also tolerant to jitter and further the effective measurement dynamic range of ADC 20 may be adjusted/maximized by η—that is, the resistor divider ratio of voltage divider 16 can be chosen to accommodate a different input voltage range.
An example, circuit 10 may be formed as depicted in
Many variations to the circuit of
Of course, the above described embodiments are intended to be illustrative only and in no way limiting. The described embodiments of carrying out the invention are susceptible to many modifications of form, arrangement of parts, details and order of operation. The invention, rather, is intended to encompass all such modification within its scope, as defined by the claims.
The present application claims priority from U.S. Provisional Patent Application No. 61/577,303, filed Dec. 19, 2011, the contents of which are hereby incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
61577303 | Dec 2011 | US |