Claims
- 1. A programmable digital device comprising:a programmable digital circuit block that is configurable to perform any one of a plurality of predetermined digital functions upon being configured with a single register write operation.
- 2. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block is configurable into a serial arrangement.
- 3. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block is configurable into a parallel arrangement.
- 4. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.
- 5. The programmable digital device as recited in claim 1 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.
- 6. The programmable digital device as recited in claim 1 wherein said predetermined digital functions are 8-bit predetermined digital functions.
- 7. The programmable digital device as recited in claim 1 wherein said programmable digital circuit block further comprises:a configuration register for receiving and storing a plurality of configuration data corresponding to any of said plurality of predetermined digital functions; and a plurality of selectable logic circuits which perform any of said plurality of predetermined digital functions, wherein said predetermined digital functions determine size and arrangement of said selectable logic circuits.
- 8. A programmable digital device comprising:an array of programmable digital circuit blocks, each programmable digital circuit block is configurable to perform any one of a plurality of predetermined digital functions upon being configured with a single register write operation.
- 9. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is configurable into a serial arrangement.
- 10. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block is configurable into a parallel arrangement.
- 11. The programmable digital device as recited in claim 8 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.
- 12. The programmable digital device as recited in claim 8 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.
- 13. The programmable digital device as recited in claim 8 wherein said predetermined digital functions are 8-bit predetermined digital functions.
- 14. The programmable digital device as recited in claim 8 wherein each programmable digital circuit block further comprises:a configuration register for receiving and storing a plurality of configuration data corresponding to any of said plurality of predetermined digital functions; and a plurality of selectable logic circuits which perform any of said plurality of predetermined digital functions, wherein said predetermined digital functions determine size and arrangement of said selectable logic circuits.
- 15. A method of configuring a programmable digital circuit block, comprising:selecting one a plurality of predetermined digital functions; performing a single register write operation to provide to said programmable digital circuit block a plurality of configuration data corresponding to said selected one of said predetermined digital functions; and configuring said programmable digital circuit block using said configuration data.
- 16. The method as recited in claim 15 wherein said configuring includes configuring said programmable digital circuit block into a serial arrangement.
- 17. The method as recited in claim 15 wherein said configuring includes configuring said programmable digital circuit block into a parallel arrangement.
- 18. The method as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM) a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave.
- 19. The method as recited in claim 15 wherein said predetermined digital functions include a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), and a dead zone delay.
- 20. The method as recited in claim 15 wherein said predetermined digital functions are 8-bit predetermined digital functions.
RELATED U.S. APPLICATION
This patent application is a continuation of application Ser. No. 09/909,045, filed Jul. 18, 2001, now U.S. Pat. No. 6,507,214, entitled “DIGITAL CONFIGURABLE MACRO ARCHITECTURE”, by Snyder, which claims priority to the copending provisional patent application, Serial No. 60/243,708, entitled “Advanced Programmable Microcontroller Device,” with filing date Oct. 26, 2000, and assigned to the assignee of the present application, which are hereby incorporated by reference.
US Referenced Citations (12)
Provisional Applications (1)
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Date |
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60/243708 |
Oct 2000 |
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Continuations (1)
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09/909045 |
Jul 2001 |
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10/272231 |
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