BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a control circuit, and more particularly to a control circuit for resonant power converters.
2. Description of the Related Art
Resonant technology had been developed to achieve high efficiency and low noise power conversion. In recent development, power management is required to achieve better efficiency for both light load and heavy load of power converters. The present invention provides a digital control solution with an embedded microcontroller for resonant power converters to fit advanced power management needs.
BRIEF SUMMARY OF THE INVENTION
An exemplary embodiment of a resonant control circuit for a power converter is provided. The resonant control circuit comprises a microcontroller, a switching-signal timer, a first PWM timer, and a signal detection circuit. The microcontroller has a memory circuit, and the memory circuit comprises a program memory and a data memory. The switching-signal timer generates a first switching signal coupled to switch a transformer. The first PWM timer generates a first PWM signal coupled to control a synchronous rectifying transistor of the power converter for synchronous rectifying. The signal detection circuit is coupled to an output of the power converter for generating a feedback data from a feedback signal. The microcontroller controls the first switching signal by programming the switching-signal timer in accordance with the feedback data. The microcontroller controls the first PWM signal by programming the PWM timer in response to the switching signal.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is an exemplary embodiment of a resonant power converter in accordance with the present invention;
FIG. 2A shows waveforms of switching signals of the resonant power converter in FIG. 1;
FIG. 2B shows waveforms of switching signals, a detection signal, and a PWM signal of the resonant power converter in FIG. 1;
FIG. 3 is an exemplary embodiment of a controller of the resonant power converter in FIG. 1;
FIG. 4 is an exemplary embodiment of a resonant-signal circuit of the controller in FIG. 3;
FIG. 5 is an exemplary embodiment of a PWM circuit of the controller in FIG. 3;
FIG. 6 is an exemplary embodiment of a PWM signal generator of the PWM circuit in FIG. 5;
FIG. 7 is an exemplary embodiment of a protection circuit of the controller in FIG. 3;
FIG. 8 is an exemplary embodiment of a signal detection circuit of the controller in FIG. 3; and
FIG. 9 shows waveforms of switching signals and a switching current of the resonant power converter in FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 is an exemplary embodiment of a resonant power converter in accordance with the present invention. Transistors 20 and 25 switch a transformer 10 through a capacitor 30 and an inductor 35. The capacitor 30 and the inductor 35 develop a resonant tank. The inductor 35 can be a part of the transformer 10, such as the leakage inductance of the transformer 10. Secondary windings of the transformer 10 generate an output voltage VO at a capacitor 40 via rectifiers 55 and 65. Synchronous rectifying transistors 50 and 60 are coupled to the rectifier 55 and 65 respectively for synchronous rectifying. The rectifiers 55 and 65 can be the body diodes of the transistors 50 and 60 respectively. According to the output voltage VO, resistors 71 and 72 forming a voltage divider generate a feedback signal VFB coupled to a controller 100. In accordance with the feedback signal VFB, the controller 100 generates switching signals OA and OB coupled to control the transistors 20 and 30 through a driver transformer 15. The frequency of the switching signals OA and OB will determine the output power of the resonant power converter.
A diode 45 is coupled to the rectifier 55 for generating a detection signal DET1 to the controller 100. A diode 46 is coupled to the rectifier 65 for generating a detection signal DET2 to the controller 100. When the transistor 50 is turned off, a pulled-low state of the detection signal DET1 indicates that the rectifier 55 is still turned on. According to the states of the switching signals OA and OB and/or the detection signals DET1 and DET2, the controller 100 generates signals PWM1 and PWM2 to control the transistors 50 and 60 respectively.
A current transformer 19 is coupled to the transformer 10 for detecting a switching current IP of the transformer 10 and generate a current signal VCS via a high speed bridge-rectifier 80 and a resistor 81. Through a resistor 85 and a capacitor 86, the current signal VCS further generate an average-current signal VOI for over-current protection. The current signal VCS and the average-current signal VOI are coupled to the controller 100. A signal VOV is further coupled to the controller 100 for over-voltage protection. The level of the signal VOV is correlated to the level of the output voltage VO.
FIG. 2A shows the waveforms of the switching signals OA and OB. The on-time of the switching signal OA is represented by TA. The on-time of the switching signal OB is represented by TB. TD represents the dead-time between the switching signals OA and OB. The timing of the on-time TA, the on-time TB, and the dead-time TD is programmable by timers. Therefore, the frequency, the duty-cycle, and the pulse width of the switching signals OA and OB are programmable.
FIG. 2B shows the waveforms of the switching signals OA and OB, the detection signal DET1, and the signal PWM1. When the switching signal OA is “pulled-high” and/or the detection signal DET1 is “pulled-low”, then the signal PWM1 will be generated to turn on the transistor 50 for the synchronous rectifying. TDB represents de-bounce time that makes sure the detection signal DET1 has been pulled low. The pulse width TPWM of the signal PWM1 is programmable by a timer. Another timer will record timing TR that starts from “the turn-off of the signal PWM1” to “the pulled-high of the signal DET1”. It means the timing TR records the period from “the turn-off of the transistor 50” to “the turn-off of the rectifier 55”. The timing TR is utilized to program the pulse width TPWM for optimizing the synchronous rectifying.
FIG. 3 is an exemplary embodiment of the controller 100. It includes a microcontroller (MCU) 110 and a memory circuit (MEMORY) 112 including a program memory and a data memory. An oscillation circuit (OSC) 113 generates a clock signal CK. Through a data bus DATA BUS, the microcontroller 110 controls a resonant-signal circuit (RESONANT) 150 to generate the switching signals OA and OB and an interrupt signal INT. The interrupt signal INT is coupled to interrupt the microcontroller 110 in response to the falling edges of the switching signals OA and OB (showed in FIG. 4). A PWM circuit (PWM) 200 is coupled to generate the signals PWM1 and PWM2 in response to the switching signals OA and OB and/or the detection signals DET1 and DET2. The pulse widths of the signals PWM1 and PWM2 from PWM circuit (PWM) 200 are programmable by the microcontroller 110. A protection circuit (PROTECTION) 300 generates a reset signal RST coupled to turn off the switching signals OA and OB from the resonant-signal circuit (RESONANT) 150 and the signals PWM1 and PWM2 from the PWM circuit (PWM) 200 when the signal VOV is over a threshold or a watchdog timer is overflow. A signal detection circuit (SIGNAL DETECTION) 350 is coupled to convert the feedback signal VFB, the current signal VCS, and the average-current signal VOI to digital data for the microcontroller (MCU) 110.
FIG. 4 is an exemplary embodiment of the resonant-signal circuit 150. The resonant-signal circuit 150 includes a timer A 160 to determine the period of the on-time TA of the switching signal OA (shown in FIG. 2A), a timer B 170 to determine the period of the on-time TB of the switching signal OB, and a timer D 180 to determine the period of the dead-time TD. The timer A 160 and the timer B 170 have 16-bit length data, and they can be programmed through the data bus DATA BUS. The timer D 180 is an 8-bit length timer, and it also can be programmed through the data bus DATA BUS. The output SA of the timer A 160, the output SB of the timer B 170, and the output SD of the timer D 180 are coupled to a logic circuit 190 to generate signals SOA and SOB. An AND gate 191 receives the signal SOA and the reset signal RST from the protection circuit 300 to generate the switching signal OA. An AND gate 192 receives the signal SOB and the reset signal RST to generate the switching signal OB. The falling edges of the switching signals OA and OB will generate the interrupt signal INT through a pulse generation circuit 195.
FIG. 5 is an exemplary embodiment of the PWM circuit 200. The PWM circuit 200 includes a PWM signal generator 230 for generating the signals PWM1 and PWM2 in response to the switching signals OA and OB and/or the detection signals DET1 and DET2. The PWM signal generator 230 also generates trigger signals SD1 and SD2. The trigger signals SD1 and SD2 are correlated to the detection signals DET1 and DET2. A timer (TR1) 210, also called as synchronous rectifying (SR) timer, receives the signal PWM1 through an inverter 211 and further receives the trigger signal SD1. The timer 210 is utilized to record the period (timing) TR (shown in FIG. 2B, also called as SR-margin period) from the time point when the signal PWM1 is turned off (that is the transistor 50 is turned off) to the time point when the trigger signal SD1 has a logic low level (that is the detection signal DET1 is pulled high). A timer (TR2) 220, also called as synchronous rectifying (SR) timer, receives the signal PWM2 through an inverter 221 and further receives the trigger signal SD2. The timer 220 is utilized to record the period (timing, also called as SR-margin period) from the time point when the signal PWM2 is turned off (that is the transistor 60 is turned off) to the time point when the trigger signal SD2 has the logic low level (that the detection signal DET2 is pulled high). The data of the timers 210 and 220 is stored into registers (REG) 215 and 225 respectively. The microcontroller 110 can read the data of the timers 210 and 220 (stored in the registers 215, 225) from the data bus DATA BUS.
FIG. 6 is an exemplary embodiment of the PWM signal generator 230. The PWM signal generator 230 includes a comparator 231 coupled to receive the detection signal DET1. The comparator 231 will generate an output coupled to a de-bounce circuit (TDB1) 235 once the detection signal DET1 is higher or lower than a threshold VT1. The de-bounce circuit 235 will output the trigger signal SD1. The trigger signal SD1 and the switching signal OA are coupled to an AND gate 232, and the output of the AND gate 232 is coupled to a flip-flop 237. Through an AND gate 239, the output of the flip-flop 237 is applied to control the clock signal CK for a timer (PWM1 TIMER) 250. The value of the timer 250 is programmable by the microcontroller 110 through the data bus DATA BUS.
A comparator 241 is coupled to receive the detection signal DET2. The comparator 241 will generate an output coupled to a de-bounce circuit (TDB2) 245 once the detection signal DET2 is higher or lower than the threshold VT1. The de-bounce circuit 245 will output the trigger signal SD2. The trigger signal SD2 and the switching signal OB are coupled to and AND gate 242, and the output of the AND gate 242 is coupled to a flip-flop 247. Through an AND gate 249, the output of the flip-flop 247 is applied to control the clock signal CK for a timer (PWM2 TIMER) 260. The value of the timer 260 is programmable by the microcontroller 110 through the data bus DATA BUS.
The data of a register (PWM_REG) 270 is programmable by the microcontroller 110 via the data bus DATA BUS. When the clock signal CK is enabled for clocking the timer 250, a start signal ST1 will be generated. A digital comparator 255 will coupled to compare the value of the timer 250 and the value of register 270. Once the value of the timer 250 and the value of register 270 are equal, the digital comparator 255 will generate a stop signal SO1. The stop signal SO1 is coupled to reset the flip-flop 237 and stop the clock signal CK being sent into the timer 250 through the AND gate 239. Both the start signal ST1 and the stop signal SO1 are coupled to generate the signal PWM1 through a logic circuit 280 and an AND gate 281.
When the clock signal CK is enabled for clocking the timer 260, a start signal ST2 will be generated. A digital comparator 265 will coupled to compare the value of the timer 260 and the value of register 270. Once the value of the timer 260 and the value of register 270 are equal, the digital comparator 265 will generate a stop signal SO2. The stop signal SO2 is coupled to reset the flip-flop 247 and stop the clock signal CK coupled to the timer 260 through the AND gate 249. Both the start signal ST2 and the stop signal SO2 are coupled to generate the signal PWM2 through the logic circuit 280 and an AND gate 282. The reset signal RST is coupled to the AND gates 281 and 282 to turn off the signals PWM1 and PWM2 once the reset signal RST is enabled for the protection.
FIG. 7 is an exemplary embodiment of the protection circuit 300. A comparator 310 is coupled to receive the signal VOV and compares the signal VOV and a over-voltage threshold VT2 to generate an output signal to a de-bounce circuit (TDB3) 315. The de-bounce time of the de-bounce circuit 315 is around 10 usec. The output of the de-bounce circuit 315 is coupled to a flip-flop 325 via an OR gate 335 for generating the reset signal RST through an inverter 326. Another input of the OR gate 335 is an overflow signal OVF. A watchdog timer (WDT) 330 generates the overflow signal OVF. The watchdog timer 330 is controlled by the microcontroller 110 though the data bus DATA BUS. When the protection is happened by the signal VOV (such as the signal VOV is higher than the over-voltage threshold VT2) or the watchdog timer 330 (such as the watchdog timer 330 is running overflow), the protection state and the reset signal RST will be latched by the flip-flop 325. Only the microcontroller 110 can clear the flip-flop 325 via the data bus DATA BUS, a decoder 340 and an inverter 345, such that the turned-off states of the switching signals OA and OB and the turned-off states of the signals PWM1 and PWM2 are cleared by the microcontroller 110.
FIG. 8 is an exemplary embodiment of the signal detection circuit 350. A decoder 370 coupled to the data bus DATA BUS for generating signals to control a multiplexer (MUX) 360, a sample-and-hold circuit (S/H) 362 and an analog-to-digital converter (A/D) 365. The microcontroller 110 can read the output of the analog-to-digital converter 365 through the data bus DATA BUS. The multiplexer 360 is coupled to receive the feedback signal VFB, the average-current signal VOI, and the current signal VCS. Therefore, the microcontroller 110 can read the information of the feedback signal VFB (the feedback data), the average-current signal VOI, and the current signal VCS.
FIG. 9 shows the waveforms of the switching signals OA and OB and the switching current IP. The switching current IP is the current flowing through the transformer 10 and the current transformer 19. The switching current IP can be converted to the signal VCS. By measuring the current signal VCS (through the signal detection circuit 350) in response to the interrupt signal INT (or in response to the falling edges of the switching signals OA and OB), the microcontroller 110 can detect the level of ΔI. The level of ΔI indicates the margin of the switching current IP before the switching current IP falls to zero current. The level of ΔI is utilized to ensure that the switching of the transistors 20 and 30 achieves zero voltage switching (ZVS). It also can make sure the resonant switching can be operated in inductive-mode. The level of ΔI also indicates the lowest switching frequency that is allowed for controlling the resonant power converter.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20130223111
