Patent Grant
7759921
This invention relates to a digital device and a method of controlling supply voltage in low-power portable devices.
Analog controlled switch-mode power supplies (SMPS) are used in low power devices such as cell phones, portable data assistants, and MP3 players, to transfer variable supply (i.e. battery) voltage to a constant output value. The regulation is performed through the interaction of an analog controller and direct-current to direct-current (DC-DC) switching power converter. The task of the controller is to monitor the output voltage and provide appropriate low-power pulse-width modulated control signals for the switching converter, which efficiently processes power. To allow small weight and size of the overall system, it is usually desirable that the controller produces signals at a high constant frequency (switching frequency fsw) that does not interfere with the proper operation of the supplied device. In the existing portable devices dedicated analog integrated circuits (IC-s) are generally used to perform the control task. The analog controllers are fast and have low-power consumption but also suffer from many problems. They generally require a long and tedious design process and often need to be completely redesigned each time IC implementation technology changes, and as such are not flexible and unsuitable for the integration with fast changing digital hardware on which the majority of portable devices is based. In addition, the analog controllers are sensitive to temperature changes, variations in manufacturing process, and aging.
Digital control of low-power switch SMPS can result in significant improvements of system characteristics. It offers advantages such as simple introduction of advanced control laws and power management techniques, use of automated design tools that enable faster development and implementation, low sensitivity to external influences and parameter variations, realization with a small number of external passive components, and design portability, which allows simple transition from one to another, more advanced, IC implementation technology. All of these are highly desirable features in modern portable applications that need to be implemented with a miniature power-efficient hardware.
Modern tools for automatic digital design allow fast development process and simple transfer of designs from one implementation technology to another. In addition, the digital implementation benefits from superior flexibility. The same hardware can perform many different functions and existing designs can be easily altered to better suit other applications.
The digital hardware also shows lower susceptibility to external influences, such as change of temperature or aging. The operation of a digital system usually remains unchanged in all working conditions.
Moreover, the digital control also allows simple implementation of power savings (management) techniques based on voltage scaling that result in significant extension of the battery life. In those techniques, to allow minimal power consumption, the supply voltage of the device is changed in accordance with its processing load. Using digital hardware, these techniques can be implemented without a significant increase in system complexity. It can be done through simple communication with a digital microprocessor, which is a standard part of most modern portable devices. Implementation of the power savings techniques with analog hardware is a complex task. It requires additional hardware, and could increase power consumption and the size of the device.
Although the abovementioned advantages of the digital control are known, in low-power applications, analog pulse-width modulated (PWM) controllers are almost exclusively used. The main reasons for the sporadic use of digital controllers is their power consumption and much lower switching frequency compared to their analog counterparts. Power consumption of digital hardware is proportional to the product of switching frequency and size of the hardware (on-chip area) and in the existing solutions often exceeds the power consumed by the output load. As a result, overall efficiency of digitally controlled SMPS is poor. The lower switching frequency generally results in a larger, heavier, and more expensive power stage that can negate some or all of the abovementioned advantages of digital control.
The inferior performance of digitally controlled SMPS in low power applications is mainly caused by slow and power inefficient operation of basic functional blocks, digital pulse-width modulator, compensator and analog-to-digital controller. Recent products and publications (References 1-4 below) demonstrate digital controllers with improved performance. They allow introduction of digitally controlled SMPS in larger portable systems, such as laptop computers, and camcorders, but are still not suitable for smaller portable devices. For the targeted applications, they still have high power consumption and operate at relatively low switching frequencies. The maximum frequency of these solutions is between 400 kHz and 1 MHz, significantly lower than the switching frequency of readily available analog controllers that operate at frequencies up to 5 MHz (References 5-6 below). The known digital controllers will also not be able to operate with upcoming SMPS that, in near future, are expected to operate at switching frequencies significantly higher than 10 MHz.
Therefore what is needed is a device and method of digital control of low-power SMPS having low power consumption and being able to operate at switching frequencies even beyond 10 MHz (ultra-high switching frequency).
The present invention advances the art and helps overcome the aforementioned problems by providing a fast, low-power digital SMPS controller that can operate at programmable switching frequencies from 1 to 12 MHz. The solution can also be easily modified to operate at even higher frequencies. Simulations show that it can operate at about 120 MHz with optimization, and a DPWM was constructed that operates at 60 MHz. Implemented with the commonly used FPGA systems 1, the new controller can produce pulse-width modulated signals at frequencies up to 60 MHz with high 9-bit resolution. If on chip implementation is selected, the frequency range can easily be further expanded. The present invention can be implemented with digital logic gates only, or with a combination of digital gates and a minimal number of very simple analog components. In the latter case, the analog components can be used for the further power and size reduction, and can be developed in a small fraction of time needed for conventional analog designs.
One aspect of the present invention is a novel digital controller for low-power DC-DC switch mode power supplies (SMPS) suitable for on-chip implementation and use in portable battery-powered systems. The controller allows operation at ultra high constant switching frequencies and can be implemented with simple low-power digital hardware. These benefits are achieved by combining a newly designed digital pulse width modulator (DPWM), based on the second-order multi-bit sigma-delta (Σ-Δ) principle, with a dual-sampling mode PID compensator. The output voltage is either sampled at a frequency lower than the switching frequency (undersampled) or sampled at the switching rate. In steady-state, undersampling results in reduced power consumption, while during transients, sampling at the switching rate provides fast transient response.
Another aspect of the present invention is a dual sampling/clocking scheme, which is relied on by the DPWM described, but also has application beyond the particular DPWM described. Accordingly, another aspect of the invention is a device and method for controlling a dual sampling/clocking mode.
Yet another aspect of the present invention is a method for digital control of SMPS that enables power efficient operation at constant switching frequencies significantly higher than 10 MHz.
A detailed description of the preferred embodiments is provided herein below by way of example only and with reference to the following drawings, in which:
a shows undesirable low-frequency tones in the output voltage of an experimental switching converter, for the case when a first-order multi-bit sigma-delta DPWM is used. Ch1: the ac component of converter output voltage (scale 100 mV/div); Ch2: pulse width modulated signal.
b demonstrates how the second-order multi-bit sigma delta DPWM eliminates the noise problems in the experimental system. Ch1: the ac component of converter output voltage (scale 100 mV/div); Ch2: pulse width modulated signal (c(t) of
The representative buck converter of
The regulation of the output voltage vout(t) is performed as follows. Analog-to-digital converter (A/D) transforms attenuated analog output voltage Hvout(t) into its digital equivalent Hvout[n]. The attenuation is usually performed to reduce the output voltage to the appropriate value for the A/D. In some cases, when the regulated output voltage is low enough, a direct connection to the input of the A/D is possible. The digital equivalent is then compared with a desired reference value Vref[n] forming an error signal e[n], which is passed to the digital dual-mode compensator and mode control circuit. The compensator processes error signal and creates digital control signal d[n], which is the input for the 2nd order multi-bit DPWM. The DPWM transfers the control value into pulse-width modulated signal c(t) which duty ratio is proportional to d[n].
The control value d[n] depends not only on the error signal e[n] but also on the pervious error and control values e[n−1], e[n−2], and d[n−1], respectively. In general, when the error signal is negative, meaning the output voltage is higher than the reference, the compensator reduces d[n] resulting in a decrease of the output. When the output voltage is lower a reverse action is performed.
Preferably, the controller and switching converter are connected through a gate driver that amplifies low power controller signal to the level appropriate for the power transistor.
Low-Power Ultra-High Frequency Digital Pulse-Width Modulator Based on 2nd-Order Multi-Bit Sigma-Delta Principle
In low-power DC-DC SMPS the digital pulse-width modulator (DPWM) needs to provide not only high frequency signals using minimal amount of power but also should be able to precisely regulate the signal's duty ratio value (i.e. should have high resolution). For the reasons explained in References 8, 9 listed below, the high resolution of the DPWM is necessary for accurate output voltage regulation and operation of the power supply without undesirable “limit-cycle” oscillations at the output.
Design of a high-resolution high-frequency DPWM has proven to be a challenging task (as illustrated in Reference 10 below). Prior art solutions present various architectures that make design tradeoffs between on-chip area and power consumption, or between switching frequency and the resolution of the DPWM. Conventional designs using a counter require a clock signal at a frequency that is in most applications significantly higher than the switching frequency and hence generally exhibit high power dissipation when both high frequency and high resolution are required. Designs that include a ring oscillator (delay cells) and a multiplexer have substantially lower power consumption but generally require a large on-chip area (i.e. large multiplexers) for the creation of high-resolution signals.
Recently presented architectures, such as hybrid, delay-locked loop, and segmented delay-line either combine the two previous concepts or operate with a different arrangement of the delay cells. These solutions demonstrate high-resolution operation (8-10 bits) at frequencies up to 1 MHz and operation with a decreased resolution at higher frequencies. The resolution and maximum frequency of these solutions are limited by the propagation time, i.e. time step, of a delay cell and the number of cells included in the ring.
To improve effective resolution of the DPWM, in accordance with one particular embodiment of the invention, digital dither can be introduced, in accordance with the prior art. However, this implementation requires use of relatively large look-up tables, and requires a relatively long averaging sequence for significant improvement of the effective DPWM resolution. In addition, this implementation introduces large low frequency oscillations at the output and as such has proven to be impractical for low power applications
In several other solutions sigma-delta (Σ-Δ) modulators are used as parts of power digital-to-analog converters, switch-mode amplifiers (as explained in Reference 10) or SMPS (as particularized in Reference 11). In the power amplifiers and digital-to-analog converters, a single bit sigma-delta modulator is usually used. It produces a set of digital ones and zeros in which the average value, over a large number of cycles, is equal to the desired high-resolution input value. This single-bit approach is generally not suitable for low power SMPS. The signal sequence produced by a single-bit Σ-Δ modulator has a variable frequency that can interfere with noise-sensitive battery powered devices. In addition, the variable frequency causes higher current stress on the switching converter, introduces additional losses, and requires significant over design of the expensive power stage. The solutions that combine a lower resolution multi-bit DPWM (core DPWM) and first-order Σ-Δ to achieve constant switching frequency (as shown in Reference 11 below) only partially eliminate the noise problem and usually result in a minor improvement of the effective resolution. In these solutions the 1st order Σ-Δ introduces tones (undesirable low frequency signals) (as described in Reference 12 below) the amplitude of which is undesirably large when the resolution of the core DPWM is low. Moreover, in these solutions, to perform averaging, the compensator is slowed down and dynamic (speed) of the control loop is usually compromised.
2nd Order (Σ-Δ) Multi-Bit Digital Pulse-Width Modulator Architecture
The novel DPWM architecture, which we introduce here, is shown in
In the specific implementation of the present invention, illustrated in
The low-resolution DPWM of the present invention is operable to vary duty ratio of pulse-width modulated signal c(t) between eight possible discrete values (in this example): 0, 0.125, 0.25, 0.375, 0.5, 0.675, 0.75, and 0.875.
The variations are performed over several switching periods to result in an average duty ratio value, which is equal to high resolution digital control command d[n], which in this case is an 8-bit value (see
The averaging is performed by the switching converter itself, i.e. the output LC filter, whose corner frequency fc=1/(2π√LC) is significantly lower than fav=1/Tav, where Tav is the averaging period.
The advantages of the present 2nd order Σ-Δ DPWM over previously proposed 1st order implementations are demonstrated with Table 1 and experimental waveforms of
Comparing the sequences for 1st and 2nd order output signal we can see that that the first order output produces a periodic sequence at a frequency significantly lower than the switching frequency. The periodic sequence, which in this case is characterized with seven successive 0.25 values followed by 0.375, represents a tone, whose frequency, for some inputs, can be lower than the output LC filter corner frequency. As a result undesirable oscillations at the tone frequency are unsuppressed and can occur at the converter output, as shown in the diagram of
In the case of 2nd order Σ-Δ DPWM, as table above shows, that the tones are pushed to higher frequencies (beyond LC coroner frequency) allowing noise elimination and normal operation of the power supply. The noise suppression effect of general second order Σ-Δ modulators is thoroughly described in textbooks (for example in Reference 12) and numerous research papers. The experimental results obtained when the first order Σ-Δ DPWM is replaced with the system of
Programmable Ring-Oscillator Based DPWM
Programmable Digital Delay Cell
The representative programmable digital delay cell of
It should be noted that an alternative implementation using just one 16-to-1 bit multiplexer and a single D flip-flop in between each two taps is also possible. However, the realization of a 16-to-1 multiplexer would require five 4-to-1 multiplexers resulting in much larger on-chip area than the proposed solution.
Programmable Analog Delay Cell
Frequency Synchronization Block
In some applications, it is desirable to have the switching frequency of the SMPS synchronized with an external clock.
The system consists of a “Half+1 Cell” replica of the delay line, four edge-triggered D flip-flops, a combinatorial logic and a 4-bit register (accumulator). For the case when a 3-bit ring based core DPWM is used, the “Half+1 Cells” replica of the delay line has only five delay cells, identical to the eight cells of the DPWM. At a rising edge of an external clock, the start signal is created and passed through the delay line replica, whose 4th and 5th cell (N/2 and N/2+1) are connected to two edge triggered flip-flops. Then, at the immediately following negative edge, a strobe signal is created and a “snapshot” of the states of the two replica's delay cells is taken and processed with a simple digital logic. Two zeroes at the outputs of the snapshot flip-flops indicate slower propagation (i.e. longer switching period) and produce 1 at the output of the digital logic. As a result, the value of frequency control register fsw[3:0] increases and the switching frequency increases accordingly. Two ones at the input of the digital logic indicate operation at a faster switching frequency, result in negative output, and cause a decrease of fsw. It is assumed that half periods of the DPWM and the external clock are equal when the input is 10 and the frequency register remains unchanged.
It should be noted that an ideal external clock with precise 50% duty ratio is assumed. For the case when a non-ideal clock signal is applied, the present circuit needs minor modification. In that case, the delay line needs to be replaced with a “full-length+1” replica and the start and the strobe signal need to be created with two successive edges of the clock signal.
Dual Sampling/Clocking Mode Controller
This section shows a controller suitable for the use with the previously described DPWM as well as with other low-power high-frequency configurations. A block diagram of the controller is given in
The controller operates as follows. The attenuated output voltage of the switching converter Hvout(t) (see
When the error is small, in the range of −3 to +3, the system operates in steady-state mode with the clock (clk 1 of
To improve dynamic characteristics of the system, which are limited by the steady-state mode, a dynamic mode is introduced. The controller enters into the dynamic mode when the hysteretic logic recognizes an absolute error larger than 3. At that moment it changes clock rate of the system, the control law of dual-mode look-up table (LUT) based compensator, and effectively eliminates the influence of the internal feedback of the Σ-Δ DPWM. In this mode, the fast DPWM inside the Σ-Δ DPWM is directly fed by most significant bits of the control input that corresponds to the low-resolution core DPWM input value dtr[n] (See
Dual-Mode Look-Up Table Based Compensator
The dual mode look-up table compensator shown in
In conventional DSP and microprocessor based compensator implementations, digital multipliers are used to compute control value d[n]. Usually, the computation is performed using current value of error signal e[n], previous error values e[n−1], e[n−2], . . . , e[n−k], and previous control output values d[n−1], d[n−2], . . . d[n−m]. A general algorithm for calculation of the new value can be described with the following equation
d[n]=α1d[n−1]+α2d[n−2]+ . . . +αmd[n−m]+β1e[n]+β2e[n−1]+ . . . +βke[n−k]
where, αi and βj are compensator coefficients that shape dynamic performance of the system. The calculation of this type generally requires the use of multipliers, which generally take a large on-chip area and have high power consumption. In low power devices, the amount of power taken by the multipliers is usually intolerably high even when algorithms with minimal number of multiplications are performed, making them unsuitable for the applications of interest.
As an alternative, a solution based on look-up tables (LUTs) has been proposed in the previous art (as described in Reference 3). In the proposed solution a small number of pre-calculated values described with the following equation
d[n]=d[n−1]+ae[n]+be[n−1]+ce[n−2]
is kept in look up tables eliminating need for the power hungry multipliers. As a result the power consumption of the controller is significantly reduced and the realization on relatively small chip area is allowed.
However, the proposed solution suffers from a lack of flexibility and as such is not suitable for the present control method.
The novel solution of
Verification
The operation of the present invention is verified with two realizations utilizing different implementation technologies. First, an all-digital prototype using a low-price FPGA development board was built. Then, an application specific integrated circuit (ASIC) was built. The ASIC utilizes analog delay cells shown in
Using the FPGA system, a DPWM based on the block-diagrams of
Experimental Verification (All-Digital FPGA Implementation)
The results of the verification demonstrated that the architecture of the present invention results in a significant increase of the switching frequencies at which digital controllers can be used. It is reasonable to assume that by transferring this design on an integrated circuit that is faster than the FPGA structure used, pulse width modulated signals at even higher frequencies (in the range of 100 MHz and about 120 MHz with optimization) could be achieved. This is based on implementation of the architecture to an integrated circuit in a manner that is known to those skilled in the art. Simulation results of such on-chip implementation are shown in
Closed Loop Operation
To further verify the operation of the controller, an experimental system based on block diagrams shown in
The buck converter is designed to operate with input voltage that varies from 4 to 10 V, at regulated output of 3.3 V, and to supply up to 1 A of the current at its output. The results of closed loop operation in steady-state mode are shown in
Results of the measurement of the load transient response for the output load changes between 0.1 A and 1 A are shown in
This document describes a digital controller for low-power DC-DC converters operating at ultra high constant switching frequencies. A novel architecture for a digital pulse-width modulator (DPWM) based on multi-bit 2nd order sigma-delta conversion (2nd order Σ-Δ DPWM) is introduced. The 2nd order Σ-Δ DPWM architecture is especially suitable for on-chip implementation. It allows creation of high-resolution high-frequency pulse-width modulated signals, and can be implemented with miniature low-power hardware. The invention also presents a new dual sampling/clocking mode control scheme that allows further reduction in power consumption of digital controller without penalties in the controller dynamic performance. Experimental FPGA-based implementation verifies advantages of the new architecture. Pulse width modulated signals at frequency of 60 MHz are produced and closed loop operation of DC-DC converter operating at 2 MHz is demonstrated.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2483378 | Oct 2004 | CA | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/CA2005/001507 | 10/3/2005 | WO | 00 | 8/19/2008 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2006/037214 | 4/13/2006 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6984967 | Notman | Jan 2006 | B2 |
| 7286009 | Andersen et al. | Oct 2007 | B2 |
| 7449869 | Markowski | Nov 2008 | B2 |
| 7456621 | Leung et al. | Nov 2008 | B2 |
| 7498781 | Canfield et al. | Mar 2009 | B2 |
| Number | Date | Country | |
|---|---|---|---|
| 20080303501 A1 | Dec 2008 | US |
