Patent Application
20160182264
The present invention relates generally to wireless charging and, more particularly, to digital demodulation of backscatter modulated data and decoding of such data.
Backscatter used in conjunction with Binary Amplitude Shift Keying (BASK) modulation is a simple and cost effective approach for communicating data across relatively short distances. This approach relies on inductive coupling of a primary and secondary coil in which current in the secondary coil is BASK modulated. This modulated current affects the loading on the primary coil and therefore a BASK modulated signal is generated across the primary coil.
Demodulation and decoding of BASK modulated differential bi-phase encoded data is typically performed by analog techniques such as envelope detection and envelope amplitude comparison post processing. These techniques are hardware intensive and during operation inductive coupling strengths between the coils may vary, which can affect the decoding accuracy. Also, noise may be induced into either or both of the coils, which can affect the signal amplitude levels thereby causing potential errors that may not be readily identified by analog demodulation and decoding techniques. Therefore, it would be advantageous to address these shortcomings in decoding of BASK modulated data.
The invention, together with objects and advantages thereof, may best be understood by reference to the following description of preferred embodiments together with the accompanying drawings in which:
The detailed description set forth below in connection with the appended drawings is intended as a description of presently preferred embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. In the drawings, like numerals are used to indicate like elements throughout. Furthermore, terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that module, circuit, device components, structures and method steps that comprises a list of elements or steps does not include only those elements but may include other elements or steps not expressly listed or inherent to such module, circuit, device components or steps. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements that comprises the element.
In one embodiment, the present invention provides a BASK demodulator and decoder for generating a plurality of Decoded Demodulated Binary Data Streams from a Binary Amplitude Key Shift Keying modulated signal that is modulated with a carrier frequency. The demodulator and decoder includes an analog to digital converter (ADC) having an analog signal sampling input, a sampling clock input and digital data output. The ADC samples a processed version of the modulated signal provided at the analog signal sampling input and provides digitized values thereof at the digital data output. In operation, a clock signal at the carrier signal is provided at the sampling clock input to synchronise sampling with the carrier signal. Ideally, the synchronised sampling coincides with an occurrence of peak amplitude values of the processed version of the modulated signal. There is a buffer having a buffer input coupled to the digital data output and a buffer output. In operation, the buffer stores the digitized values in a sequence order based on an order in which the peak amplitude values corresponding to the digitized values were sampled. A digital filter has a filter input that is coupled to the buffer output and a filter output. The digital filter is programmed to process the digitized values stored in the buffer using their sequence order to provide at least a first filtered modulated digital signal at the filter output. The demodulator and decoder also includes a data generator having a generator output and a generator input that is coupled to the filter output. The data generator is configured to configured to identify transitions of the first filtered modulated digital signal received at the generator input and based on the transitions generate at least one of the plurality of Decoded Demodulated Binary Data Streams at the generator output.
In another embodiment the present invention provides a method for demodulating a Binary Amplitude Key Shift Keying modulated signal. The method includes sampling peak amplitude values of a processed version of the modulated signal to provide sampled values and digitizing the sampled values to provide digitized values of processed version of the modulated signal. The digitized values are stored in a sequence order based on an order in which the peak amplitude values corresponding to the digitized values were sampled. The method also includes filtering the digitized values using their sequence order to provide at least a first filtered modulated digital signal, and then identifying transitions of the first filtered modulated digital signal. The method then generates at least one of a plurality of Decoded Demodulated Binary Data Streams based on the identifying.
Referring to
In this embodiment the VCO 108 has an output that provides a sinusoidal carrier signal CS to an input of the driver 110. The sinusoidal signal CS has a carrier frequency FC, typically from 110 KHz to 205 KHZ, depending on control signals sent to from the controller 106 to the VCO 108. The controller 106 includes one or more input channels coupled an output port OUT of the demodulator and decoder 112 and the controller 108 has output lines coupled to inputs of the demodulator and decoder 112. The driver 110 includes a power amplifier circuit with output terminals coupled to a primary coil L1, and the primary coil L1 is also coupled to an analog signal input ASI of the demodulator and decoder 112.
The chargeable unit 104 has a secondary coil L2 that can be positioned to be inductively coupled to the primary coil L1. Coupled across output terminals of secondary coil L2 are series connected capacitors C1 and C2. There is also a series coupled transistor TR1 and a capacitor C3 is connected across capacitor C2. Also, connected across capacitor C2 is a bridge rectifier circuit 116 comprising four diodes D1, D2, D3 and D4. Outputs of the bridge rectifier circuit 116 are coupled to a load module 118 and a smoothing capacitor C4 is coupled across the outputs of the bridge rectifier circuit 116. The chargeable unit 104 also has a processor 120 coupled to the load module 118 and an output of the processor 120 is coupled to a gate of the transistor TR1.
The load module 118 includes a chargeable battery, the status of which is monitored by the processor 120. In operation, when the primary and secondary coils L1, L2 are in close proximity and inductively coupled together, the driver 110 provides power to the primary coil L1 at the carrier frequency FC which may vary between 110 KHz to 205 KHZ. Since the secondary coil L2 is inductively coupled to the primary coil, a voltage is induced at the output terminals of secondary coil L2 which provides a charging current to the load module 118. This charging current is rectified by the bridge rectifier circuit 116 and smoothed by the smoothing capacitor C4.
A backscatter BASK modulation technique is used by the system 100 to allow the chargeable unit 104 to communicate with the charging station 102 to typically, at least, provide a current battery charge status of the load module 118 and a suitable charging profile. This backscatter BASK modulation technique is achieved by the processor 120 sending pulsed control signals PCS, representing Data DA, to the gate of the transistor TR1 to selectively connect and disconnect the capacitor C3 across capacitor C2. The Data DA is encoded into differential bi-phase encoded symbols as will be apparent to a person skilled in the art.
The selective connecting and disconnecting of the capacitor C3 across capacitor C2 affects the voltage across the output terminals of secondary coil L2. In this embodiment, the Pulsed Control Signals PCS have a minimum duration of 500 uS which equates to a single Data Bit Duration DBD. The loading on the secondary coil L2 caused by connecting and disconnecting of the capacitor C3 across capacitor C2 affects the voltage across the inductively coupled primary coil L1. As a result of this loading, the voltage at the inductively coupled primary coil L1 varies in a manner dependent on Data DA represented by the Pulsed Control Signals PCS in a differential bi-phase encoded BASK modulated signal MSI. This differential bi-phase encoded BASK modulated signal MSI includes the Carrier Signal CS oscillating at the carrier frequency FC providing encoded data with the single Data Bit Duration DBD of 500 uS (i.e., a differential bi-phase encoded symbol duration).
The demodulator and decoder 112 demodulates and decodes the differential bi-phase encoded BASK modulated signal MSI to decode (replicate) the data DA encoded in the Modulated Signal MSI to generate a plurality of Decoded Demodulated Binary Data Streams DDBDS. The processor 106 may then send control signals to modify the output power of the driver 110 in response to the data DA received Decoded Demodulated Binary Data Streams DDBDS. Once the battery in the load module 118 is fully charged the chargeable unit 104, which can be any portable battery powered device, can be moved away from the charging station as will be apparent to a person skilled in the art.
Referring to
There is also an analog to digital converter (ADC) 206 having an analog signal sampling input 208 coupled to the output 207 of the biasing and filtering preprocessing module 204, a sampling clock input 210 coupled to an output of the processor 202, and digital data output 212. The biasing and filtering preprocessing module 204 couples the analog signal sampling input 208 to the primary coil L1, and the ADC 206 is configured to sample the processed version of the modulated signal MSI provided at the analog signal sampling input 208. This processed version of the modulated signal MSI is provided by the biasing and filtering preprocessing module 204 which is digitized by the ADC 206. This provides digitized values DVAL of the processed version of the modulated signal MSI at the digital data output 212. In operation a clock signal CK at the carrier frequency FC of the carrier signal CS is provided at the sampling clock input 210 to synchronise sampling with the carrier signal. Ideally, this synchronised sampling coincides with the occurrence of peak amplitude values of the processed version of the modulated signal MSI. It will be appreciated that edges of the clock signal CK may be suitably offset from the peak values of the carrier signal CS to allow for inherent delays in the analog to digital converter 206.
The BASK demodulator and decoder 112 includes a buffer module 214 having a buffer input 216 coupled to the digital data output 212, a buffer output 218 and a control input 220 coupled to an output of the processor 202. In operation the buffer module 214 stores the digitized values DVAL from the analog to digital converter 206 in a sequence order SO based on an order in which the peak amplitude values corresponding to the digitized values DVAL were sampled by the ADC 206.
There is also a digital filter 222 having a filter input 224 coupled to the buffer output 218, a filter output 226 and a filter control input 228 coupled to an output of the processor 202. The digital filter 222 is programmed to process the digitized values DVAL stored in the buffer 214 using their sequence order SO to provide at least a first filtered modulated digital signal FFMS and a second filtered modulated digital signal SFMS at the filter output 226 (which are typically filter output ports).
The digital filter 222 is programmed to sequentially select one or more sliding windows comprising the digitized values DVAL in their sequence order SO and sum the digitized values DVAL in each of the windows to provide filtered discrete digital values that form the first filtered modulated digital signal FFMS and the second filtered modulated digital signal SFMS. More specifically, in one example each of the digitized values DVAL that are summed are adjacent in the sequence order SO to provide the first filtered modulated digital signal FFMS as shown in equation 1.
y(n)=Σk=0m-1DVAL(n−k) (1);
where y(n) is a digital filtered value of one of the digitized values DVAL(n) and m is the window size which may be determined by: (FC/(1/DBD))/2. Thus, for a window size of m digitized values DVAL then y(0)=DVAL(0)+DVAL(1)+DVAL(2)+ . . . +Dval(m−1); y(1)=DVAL(1)+DVAL(2)+DVAL(3)+ . . . +Dval(m); and y(2)=DVAL(2)+DVAL(3)+DVAL(4)+ . . . +Dval(m+1) etc.
In contrast, the digital filter 222 calculates difference values between two adjacent windows to provide the second filtered modulated digital signal SFMS as shown in equation 2.
y(n)=Σk=m2m-1DVAL(n−k)−Σk=0m-1DVAL(n−k) (2);
where y(n) is a digital filtered value of one of the digitized values DVAL(n) and m is the window size which may be determined by: (FC/(1/DBD))/2. Thus, for a window size of m digitized values DVAL then y(0)=(DVAL(m)+DVAL(m+1)+DVAL(m+2)+ . . . +Dval(2m−1))−(DVAL(0)+DVAL(1)+DVAL(2)+ . . . +Dval(m−1)); and y(1)=(DVAL(m+1)+DVAL(m+2)+DVAL(m+3)+ . . . +Dval(2m))−(DVAL(1)+DVAL(2)+DVAL(3)+ . . . +Dval(m)) etc.
The demodulator and decoder 112 also comprises a data generator 230 having a generator output OUT (which is the output OUT of the demodulator and decoder 112) coupled to the controller 106. The data generator 230 also has a data generator input 232 coupled to the filter output 226, and a data generator control input 234 coupled to an output of the processor 202. The data generator 230 is configured to identify transitions TR of the first filtered modulated digital signal received at the generator input 232, and based on the transitions generate at least one of the plurality of Decoded Demodulated Binary Data Streams at the generator output OUT.
Referring to
The resistor R3 and capacitor C1 have values that provide a low pass filter to thus remove high frequency noise components from signals received at the analog signal input ASI. The diodes D1 and D2 limit the amplitude values of signals at the preprocessed signal output 207 to the rail values of VCC and GND. Also, the values of the resistors R1, R2 provide the biasing voltage Vbias of any signals provide at the preprocessed signal output 207. In this example Vbias is equal to (VCC/(R1+R2))*R2=VCC/(7.5K+5.11)*5.11K=0.41*VCC.
Referring to
Referring to
Referring to
The data generator 230 is configured to generate channel 1 with the first filtered modulated digital signal FFMS such that after the commencement of a data bit duration DBD only one transition across the mid-point value RMID is detected in the remainder of the data bit duration DBD then, the data generator 230 generates a first binary value (e.g., a logic zero) for the data bit duration DBD. However, if two transitions across the mid-point value RMID are detected in the remainder of the data bit duration DBD, then the data generator 230 generates an opposite second binary value (e.g., a logic one) for the data bit duration DBD. The first and opposite second binary values are then simply provided as one of the Decoded Demodulated Binary Data Streams DDBDS where each binary value has a period of one data bit duration DBD.
The data generator 230 is configured to generate channel 2 with the first filtered modulated digital signal FFMS. The data generator 230 detects the end of the preamble (a sequence of half data bit durations high/low transitions ending in a low logic pulse for a complete data bit duration DBD) thereafter the min (MN) and max (MX) values of the first filtered modulated digital signal FFMS are identified as the transitions TR. If after the commencement of a data bit duration DBD only one min (MN) or one max transition TR is identified in the remainder of the data bit duration DBD, then the data generator 230 generates a first binary value (e.g., a logic zero) for the data bit duration. However, if both a min (MN) and a max (MX) transition TR are detected in the remainder of the data bit duration DBD, then the data generator 230 generates an opposite second binary value (e.g., a logic one) for the data bit duration DBD. The first and opposite second binary values are then simply provided as one of the Decoded Demodulated Binary Data Streams DDBDS where each binary value has a period of one data bit duration DBD.
Referring to
The data generator 230 is configured to generate channel 3 with the second filtered modulated digital signal SFMS such that when after the commencement of a data bit duration DBD only one transition across the mid-point value RMID is detected in the remainder of the data bit duration DBD then, the data generator 230 generates a first binary value (e.g. a logic zero) for the data bit duration DBD. However, if two transitions across the mid-point value RMID are detected in the remainder of the data bit duration DBD, then the data generator 230 generates an opposite second binary value (e.g., a logic one) for the data bit duration DBD. The first and opposite second binary values are then simply provided as one of the Decoded Demodulated Binary Data Streams DDBDS where each binary value has a period of one data bit duration DBD.
The data generator 230 is configured to generate channel 4 with the second filtered modulated digital signal SFMS. The data generator 230 detects the end of the preamble (a sequence of half data bit durations high/low transitions ending in a low logic pulse for a complete data bit duration DBD) thereafter the min (MN) and max (MX) values of the second filtered modulated digital signal SFMS are identified as the transitions TR. If after the commencement of a data bit duration DBD only one min (MN) or one max transition TR is identified in the remainder of the data bit duration DBD, then the data generator 230 generates a first binary value (e.g., a logic zero) for the data bit duration DBD. However, if both a min (MN) and a max (MX) transition TR are detected in the remainder of the data bit duration DBD, then the data generator 230 generates an opposite second binary value (e.g., a logic one) for the data bit duration. The first and opposite second binary values are then simply provided as one of the Decoded Demodulated Binary Data Streams DDBDS where each binary value has a period of one data bit duration DBD.
In operation the controller 106 selectively processes versions of the Decoded Binary Demodulated Data DBDD, provided at the channels 1 to 4, by using check sums to determine the accuracy of the data. This selectively processing can be by simply by in pre-defined order such that channel 1 is selected first and processed. If when error checking, by the controller 106, detects errors in the decoded version, channel 4 is then selected and error checking is performed again. Again if errors are detected channel 2 or 3 may be selected next.
Referring to
There are two encoded logic values in the encoded format 700 in which individual data bit durations that have a continuous binary logic state of zero or one are encoded as a first logic value (BIT=0) which is a logic value 0. In contrast, individual data bit durations that have more than one binary logic state of both zero and one are encoded as a second logic value (BIT=1) which is a logic value 1. Thus, the data bit durations that have more than one binary logic state spend 50% of a bit duration at logic state 1 and 50% of a bit duration at logic state 0.
Referring to
There are two encoded logic values in the coded format 800 in which individual data bit durations that have a continuous binary logic state of zero or one are encoded as a first logic value (BIT=1) which is a logic value 1. In contrast, individual data bit durations that have more than one binary logic state of both zero and one are encoded as a second logic value (BIT=0) which is a logic value 0. Thus, the data bit durations that have more than one binary logic state spend 50% of a bit duration at logic state 1 and 50% of a bit duration at logic state 0.
At a filtering block 950, the digital filter 222 performs filtering the digitized values DVAL using their sequence order SO to provide at least the first filtered modulated digital signal FFMS. The filtering sequentially selects windows comprising the digitized values DVAL in their sequence order SO. The filtering sums the digitized values DVAL in each of the windows to provide the filtered discrete digital values that form the first filtered modulated digital signal FFMS, and the second filtered modulated digital signal SFMS. Each of the digitized values DVAL that are summed are adjacent in the sequence order SO to provide the first filtered modulated digital signal and the filtering calculates difference values between two adjacent windows to provide the second filtered modulated digital signal.
At An identifying block 960 the a data generator 230 identifies the transitions TR as described above and a generating block 970 generates the least one of a plurality of Decoded Demodulated Binary Data Streams DDBDS based on an outcome of the identifying block 960 as described above.
As will be apparent to a person skilled in the art, blocks 950 to 970 also perform operations on the second filtered modulated digital signal SFMS to generate one or more Decoded Demodulated Binary Data Streams DDBDS.
Advantageously, the present invention at least alleviates the expense of analog decoders and the potential errors that may occur when demodulating and decoding varying signal amplitudes in backscatter modulated data. These varying signal amplitudes are typically caused by variations in inductive coupling strengths of the coils L1, L2 or noise that is induced into the coils L1, L2.
The description of the preferred embodiments of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiment disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410858362.4 | Dec 2014 | CN | national |
