Patent Application
20080240220
The invention relates to a digital filter and to a method for filtering.
Today, digital filters are widely used.
It is an object of the invention to provide an efficient digital filter that requires a minimum of components and/or hardware requirements.
This object is solved by a digital filter and method for filtering according to claims 1 and 21, respectively.
Further details of the invention will become apparent from a consideration of the drawings and ensuing description.
The FIGURE shows a digital filter according to an embodiment of the invention.
In the following, embodiments of the invention are described. It is important to note that all described embodiments in the following may be combined in any way, i.e. there is no limitation that certain described embodiments may not be combined with others.
The FIGURE shows a digital filter 100 comprising a sample and hold unit 102, multiplier M1, an adder A1, a first switch S1, a zero storage 104, a second buffer D2, a first buffer D1, and a second switch S2.
An input signal x(n) may e.g. be a digital signal comprising samples x0 x1, x2, . . .
Input signal x(n) is multiplied with a filter coefficient signal 114 by multiplier M1. The filter coefficient signal 114 comprises the filter coefficients h0, h1, . . . , hN in a predetermined periodical order. In each period of said periodical order, the filter coefficients are arranged in the following order:
Thus, in each or at least one period, first all even filter coefficients h0, h2, . . . , hN−2 occur, and subsequently, all uneven filter coefficients, h1, h3, . . . , hN−1.
The filter is operated at a clock rate that is higher than the sampling rate fs of input signal x(n). In general, the clock rate should be greater than or equal to
N·fs,
wherein N denotes the order of the filter and fs denotes the sampling rate of the input signal x(n).
Multiplier M1 is controlled such that one input sample xi is multiplied with all even filter coefficients h0, h2, . . . , hN−2, and that a subsequent input sample xi+1 is multiplied with all uneven filter coefficients h1, h3, . . . , hN−1. In this example, xi denotes an even input sample, e.g. x0, x2, x4, . . . , and xi+1 denotes an uneven input sample, e.g. x1, x3, x5, . . . .
Thus, intermediate signal 112 generated by multiplier M1 corresponds to products of even filter coefficients h0, h2, . . . , hN−2 and even input samples x0, x2, x4, . . . and products of uneven filter coefficients h1, h3, . . . , hN−1 and uneven input samples x1, x3, x5 . . . .
Filter coefficient signal 114 may be determined by any suitable circuit, i.e. it may not be necessary that filter coefficient signal 114 is determined as shown, i.e. based on using the first buffer D1 and second switch S2. Any other suitable circuit or method may be used to provide a filter coefficient signal having the above described properties.
However, in the example of the FIGURE, filter coefficient signal 114 is determined by loading the above-mentioned order of the filter coefficients into first buffer D1 having a size of N. This may e.g. be done during an initialization phase by switching second switch S2 to position S21 for the first N clock signals of the digital filter. After N cycles of the clock rate, second switch S2 will be switched to position S20. Thus, after N clock cycles the predetermined order of filter coefficients, h0, h2, . . . , hN−2, h1, h3, . . . , hN−1 is loaded into first buffer D1 and a periodical order is realized, wherein during each period the above defined predetermined order of filter coefficients is output via filter coefficient signal 114.
The circuit 118 for generating filter coefficient signal 114 may also be referred to as second ring buffer 118.
Intermediate signal 112 is further processed by adder A1.
Adder A1 adds said intermediate signal 112 and a first switch output signal 109, which is the output signal of first switch S1. First switch output signal 109 is equal to a second buffer output signal 108 if first switch S1 is in position S10. Second buffer output signal 108 is the output signal of second buffer D2. If first switch S1 is in position S11, then first switch output signal 109 corresponds to a zero signal 106 provided by zero storage 104.
Second buffer D2 has a size of N/2 and, thus, second buffer output signal 108 corresponds to a time delayed version of intermediate output signal 110 of adder A1.
The first switch S1 is always in position S10 except for each processing of filter coefficient hN−1. In other words, if filter coefficient hN−1 is multiplied by multiplier M1 and the resulting intermediate signal 112 is added by adder A1, then at this point in time, first switch output signal 109 will be set to zero by switching first switch S1 to position S11.
Second buffer D2 and first switch S1 may be referred to as first ring buffer 120.
Sample and hold unit 102 is controlled to sample and hold intermediate output signal 110, wherein a taking a sample and holding this sample takes place when coefficient h1 has been multiplied with its corresponding input sample and added with its corresponding sample of first switch output signal 109. In other words, each time filter coefficient h1 has been multiplied by multiplier M1 and a corresponding intermediate signal 112 as well as a corresponding intermediate output signal 110 has been generated, the respective sample of intermediate output signal 110 is output as the value for the next output sample of output signal y(m).
Thus, two input samples xi, xi+1, result in one output sample, and, therefore, the sampling rate of output signal y(m) is half of the sampling rate of input signal x(n).
First and second buffer D1, D2 may be realized e.g. based on a flip flop, RAM, ROM and/or any other suitable storage.
The following gives a further description of the FIGURE:
In digital signal processing sampling rate decimation is often needed to reduce the effort of processing a signal. To decimate a signal by a factor of 2 you must delete the signal components, which lies above 1/2 of the sampling rate of the input signal. After this it is allowed by Shannon's law to delete every 2nd sample.
In digital receivers often FIR filters are used. When these filters have to be realized on an ASIC it is wishful to make them as small as possible to reduce costs. That means that they should be realized with as few elements as possible.
Here a digital FIR filter realization is shown that consists of only one multiplier. The reduction down to only one multiplier is obtained by running the filter with a higher clock rate and changing the coefficient at the multiplier each clock cycle.
The filter is based on only one multiplier to realize an FIR filter of order N. This can be done as the filter runs with a higher clock rate. The clockrate has to be at least N*fs (N is the filterorder, fs is the sampling rate) to ensure enough time to process all coefficients.
To provide the right samples at the right time two ring buffers 118, 120 are used. The 1st ring buffer 120 contains the product of the signal samples with the filter coefficients, the 2nd ring buffer 118 contains the filter coefficients in the order h0, h2, . . . , hN−2, h1, h2, . . . , hN−1. This order is loaded with switch setting S21 into the coefficient ring buffer once at start up and then it runs in circle with switch setting S20. The size of the filter coefficient ring buffer 118 is N. The order of the 1st ring buffer 120 is N/2. In case N is odd the size is ceiled to the next integer. The switch setting of S1 is always S10 except for the calculation of filter coefficient hN−1.
Thus the 1st ring buffer 120 acts as an integrator but has never to be resetted. At startup the content of the 1st ring buffer 120 should be initialized to zero. If the first ring buffer 120 is not initialized properly, only the frirst N/2 output samples may be wrong, i.e. all following samples are output correctly even without any initialization.
The FIGURE shows a block diagram of the filter structure for this filter.
Each input sample must be valid at the multiplyer M1 to be processed with N/2 filter coeffients. First equal numbered input sample are processed with equal numbered filter coefficients x0*h0, x0*h2, . . . x0*hN−2. After this odd numbered input sample are processed with odd numbered filter coefficients x1*h1, x1*h3, . . . x1*hN−1. In case N is odd the size of the odd numbered filter coefficients is one less than the size of the equal numbered filter coefficients.
Two input samples give one output samples. The ith outputsample is valid after the coefficient h1 is multiplied with its corresponding input sample and added with its corresponding value of 1st ringbuffer 120. At this time the signal “enable” is valid.
The system is a realization of an decimation by factor 2 with polyphase FIR filter which is reduced in size, e.g. a realization with as few elements as possible. So the realization on an ASIC is smaller and may be cheaper. Only one multiplier is necessary because of running the filter at a higher clock rate, and the memory size of the sample buffer for the filter convolution is halved.
This structure may also be applied in cases of decimation by factor 4, 8, . . . 2x. In this cases the coefficients have to be reordered and the size of the buffer D1 shrinks by the decimation factor.
For a decimation by factor 4 the order of the coefficients is
In this case the size of buffer D1 is equal to N/4.
For a decimation by factor 8 the order of the coefficients is
In this case the size of buffer D1 is equal to N/8.
It should be noted that the above explained filter may also be realized by respective method steps. Such a method may then be executed based on a computer program product including computer program instructions that cause a computer to execute the method.
| Number | Date | Country | Kind |
|---|---|---|---|
| 07 006 795.4 | Mar 2007 | EP | regional |
