The present invention relates to a digital filter used in signal processing in a variety of fields, and more particularly to an infinite impulse response (IIR) filter and a finite impulse response (FIR) filter that achieve miniaturization and speedup, and a signal processing device including feedback processing.
Nowadays, an IIR digital filter is one of arithmetic units used in digital signal processing in various fields. Digital filters generally include finite impulse response (FIR) filters and infinite impulse response (IIR) filters. IIR filters can be of a lower order than FIR filters to attain equivalent characteristics and thus permit circuit miniaturization. In IIR filters, however, the number of bits for an operation must be sufficiently large.
Various patent applications have so far proposed configurations of IIR digital filters, including Patent Documents 1, 2 and 3, for example.
Among several known types of configurations of IIR digital filters,
The delay circuits 3 provide a time lag of one sample time, the multiplier circuits 2 multiply the outputs of the delay circuits 3 by coefficients, and the adder circuits 1 sum the outputs of the multiplier circuits 2.
The coefficients in the multiplier circuits 2 may be changed, to permit implementation of various types of filters (LPF, HPF, BPF and BRF).
In design of an IIR digital filter, it is necessary to consider the number of bits for an operation required to satisfy the characteristics, the stability of the feedback system and the like.
However, in conventional digital filters such as IIR digital filters, the feedback processing requires performing a multiplication and several additions in one sample (one clock cycle). This causes a problem of preventing speedup of the circuit operation.
Another problem is that as the order of a digital filter becomes higher, the numbers of multiplier circuits and adder circuits increase and this increases the circuit scale.
To solve the above problems, an object of the present invention is providing a digital filter capable of achieving speedup of the circuit operation and reduction of the circuit scale, and a synthesizing device, synthesizing program and synthesizing program recording medium for such a digital filter.
To attain the above object, according to the present invention, a digital filter is composed of, not a plurality of multiplier circuits and a plurality of adder circuits, but one multi-input multiplier/adder circuit having the same functions as these circuits.
Specifically, the digital filter of the present invention includes: a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample; a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and supplying the summed result to the shift register; a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.
In the digital filter described above, the first multi-input multiplier/adder circuit may include: a partial product generation circuit for receiving the plurality of output signals of the shift register and multiplying the plurality of output signals of the shift register by respective coefficients to generate a plurality of partial products; and a multi-input adder circuit permitting pipelining for increasing the processing speed, the multi-input adder circuit receiving the input signal and outputs of the partial product generation circuit and summing all of the received signals.
In the digital filter described above, the second multi-input multiplier/adder circuit may include: a partial product generation circuit for receiving the plurality of output signals of the shift register and multiplying the plurality of output signals of the shift register by respective coefficients to generate a plurality of partial products; and a multi-input adder circuit permitting pipelining for increasing the processing speed, the multi-input adder circuit receiving outputs of the partial product generation circuit and summing all of the received signals.
Alternatively, the digital filter of the present invention includes: a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample; and a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and outputting the summed result as the output of the digital filter.
In the digital filter described above, the first multi-input multiplier/adder circuit may include: a partial product generation circuit for receiving the plurality of output signals of the shift register and multiplying the plurality of output signals of the shift register by respective coefficients to generate a plurality of partial products; and a multi-input adder circuit permitting pipelining for increasing the processing speed, the multi-input adder circuit receiving the input signal and outputs of the partial product generation circuit and summing all of the received signals.
In the digital filter described above, the first and second multi-input multiplier/adder circuits may receive multiplication coefficients externally.
In the digital filter described above, in the shift register, the plurality of output signals may be selected based on an external control signal.
In the digital filter described above, in the shift register, the plurality of output signals may be selected based on an external control signal.
Alternatively the digital filter of the present invention includes: a shift register receiving two signals and having two groups of a plurality of registers for storing data, the shift register shifting data in the plurality of registers of each of the two groups every sample; a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and two groups of a plurality of output signals of the shift register, multiplying the two groups of the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and outputting the summed result to the shift register as the first input, and also determining whether or not round-up is involved in rounding processing from the summed result obtained by multiplying the two groups of the plurality of output signals of the shift register by respective coefficients and summing all of the multiplied results and the input signal, and outputting the determined result to the shift register as the second input; a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.
Alternatively, the digital filter of the present invention includes: a shift register receiving two signals and having two groups of a plurality of registers for storing data, the shift register shifting data in the plurality of registers of each of the two groups every sample; and a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and two groups of a plurality of output signals of the shift register, multiplying the two groups of the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and outputting the summed result to the shift register as the first input, and also determining whether or not round-up is involved in rounding processing from the summed result obtained by multiplying the two groups of the plurality of output signals of the shift register by respective coefficients and summing all of the multiplied results and the input signal, and outputting the determined result to the shift register as the second input;
The digital filter described above may further include: an input control circuit for controlling the input signal based on an external input control signal so as to perform predetermined processing and outputting the controlled signal to the first multi-input multiplier/adder circuit, wherein the first multi-input multiplier/adder circuit receives multiplication coefficients externally, and the second multi-input multiplier/adder circuit also receives multiplication coefficients externally.
In the digital filter described above, the input control circuit may include: a bit shift circuit for performing bit shift processing for the input signal based on the external input control signal.
In the digital filter described above, the input control circuit may include: a plurality of bit shift circuits for performing bit shift processing of shifting the input signal by different numbers of bits; and a selector for selecting the outputs of the plurality of bit shift circuits based on the external input control signal.
The signal processing device of the present invention includes the digital filter described above.
The digital filter synthesizing device of the present invention synthesizes a digital filter from: a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample; a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and supplying the summed result to the shift register; and a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.
The digital filter synthesizing program of the present invention is a program for allowing a computer to synthesize a digital filter, including the steps of: synthesizing a shift register having a plurality of registers for storing data, the shift register shifting data in the plurality of registers every sample; synthesizing a first multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the first multi-input multiplier/adder circuit receiving an input signal and a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results and the input signal, and supplying the summed result to the shift register; and synthesizing a second multi-input multiplier/adder circuit permitting pipelining for increasing the processing speed, the second multi-input multiplier/adder circuit receiving a plurality of output signals of the shift register, multiplying the plurality of output signals of the shift register by respective coefficients, summing all of the multiplied results, and outputting the summed result as the output of the digital filter.
The digital filter synthesizing program recording medium of the present invention has the digital filter synthesizing program described above stored therein.
As described above, in the digital filter of the present invention, which uses a multi-input multiplier/adder circuit as a component, the circuit size can be reduced. Moreover, since the multi-input multiplier/adder circuit permits pipelining for speedup, filter processing can be performed at high speed.
In particular, according to the present invention, since multiplication coefficients are received externally, the filter characteristics can be changed, and thus a digital filter having desired characteristics can be easily obtained.
According to the present invention, some arbitrary output signals can be selected from a plurality of output signals of the shift register. Hence, the filter characteristics can be changed, and thus a small-size, high-speed digital filter having desired characteristics can be obtained.
According to the present invention, round-up in a rounding operation is performed, not at the time of output of multi-input addition, but at the time of multi-input multiplication after feedback. Hence, a small-size digital filter with further high speed can be obtained.
According to the present invention, the input control circuit can perform given processing such as bit shifting, for example, for the input signal. Hence, even when the place of the LSB is different among multiplication coefficients inputted externally, a correct operation can be performed, and thus a desired high-accuracy digital filter can be implemented.
In the synthesizing device and synthesizing program for the digital filter and the recording medium of the synthesizing program, a small-size, high-speed digital filter as described above can be synthesized.
As described above, according to the present invention, with use of a multi-input multiplier/adder circuit as a component of a digital filter, size reduction can be achieved. Also, since pipelining for increasing the processing speed is permitted, a high-speed digital filter can be implemented.
In particular, according to the present invention, round-up in a rounding operation is performed, not at the time of output of multi-input addition, but at the time of multi-input multiplication and addition after feedback. Hence, a digital filter with further high speed can be obtained.
a) is a view showing another example of an IIR digital filter is permitting pipelining, and
Hereinafter, embodiments of the present invention will be described with reference to the relevant drawings.
An IIR digital filter of Embodiment 1 of the present invention will be described with reference to
The transfer function of an IIR digital filter is generally represented by:
The configuration of
The IIR digital filter has a feedback loop as shown in
The IIR digital filter of
Also, with use of the multi-input multiplier/adder circuits 4 and 5 that perform multiplications of a plurality of inputs and all additions, not using a plurality of multiplier circuits and a plurality of adder circuits as in the conventional IIR digital filter, the circuit scale can be reduced. Reduction in circuit scale can also be attained by providing only one shift register 6 for sharing.
The partial product generation circuit 7 of each of the multi-input multiplier/adder circuits 4 and 5 multiplies a plurality of inputs by respective coefficients to generate partial products. The partial product generation circuit 7 is configured to calculate partial products by one-bit multiplication, which is equal to execution of AND in bit operation. The multi-input adder circuit 8 of each of the multi-input multiplier/adder circuits 4 and 5 is a circuit that receives a plurality of partial product results from the partial product generation circuit 7 and sums up these inputs, and may be configured of a Wallace tree adder circuit.
The multi-input multiplier/adder circuits 4 and 5 shown in
The first-order transfer function of an IIR digital filter is represented by:
The circuit of
[Equation 4]
1−a1·Z−1 (4)
The resultant transfer function is represented by
The expression of the denominator of the above transfer function has a term of Z−2 and no more has the term of Z−1. This indicates that two-stage pipelining can be adopted for multiplication and addition in the feedback loop. The processing speed can therefore be increased.
a) is a view showing another example of an IIR digital filter permitting pipelining. In
The circuit of
[Equation 6]
1−a1·Z−1+a2·Z−2 (6)
The resultant transfer function is represented by
The expression of the denominator of the above transfer function no more has the term of Z−1 and has a term of Z−2. This indicates that two-stage pipelining can be adopted for multiplication and addition in the feedback loop. The processing speed can therefore be increased.
The IIR digital filters of
The IIR digital filter of
Although the multi-input multiplier/adder circuit 5 shown in
The IIR digital filter of
The IIR digital filter of
The IIR digital filters described in this embodiment can be used for digital signal processing devices in a variety of fields.
The IIR digital filters were described in this embodiment. It is however needless to mention that the present invention is applicable to FIR digital filters and other filters including feedback processing and also usable for other signal processing devices.
Thus, in this embodiment, with use of the multi-input multiplier/adder circuit, the circuit size can be reduced, and also pipelining for speedup can be adopted. Hence, a small-size, high-speed IIR digital filter can be implemented.
Next, an IIR digital filter of Embodiment 2 of the present invention will be described with reference to
The basic circuit configuration of
In addition, the multi-input multiplier/adder circuits 4 and 5 shown in
With the above configuration, the characteristics of the filter can be changed to desired ones. Also, with use of the multi-input multiplier/adder circuits, the circuit size can be reduced, and pipelining for speedup can be adopted. Hence, a small-size high-speed IIR digital filter can be implemented.
An IIR digital filter of Embodiment 3 of the present invention will be described with reference to
The basic circuit configuration of
In this embodiment, with the capability of external control of the combination of outputs of each group from the shift register 6a, the characteristics of the filter can be changed to desirable ones.
Also, with the capability of control of the combination of outputs of each group from the shift register 6a, the circuit configuration can be changed to one permitting pipelining for increasing the circuit processing speed.
The shift register 6a receives the output of the multi-input multiplier/adder circuit 4 shown in
With the above configuration, with use of the multi-input multiplier/adder circuits 4 and 5, the circuit size can be reduced, and also pipelining for speedup can be adopted. Hence, a small-size, high-speed IIR digital filter can be implemented.
An IIR digital filter of Embodiment 4 of the present invention will be described with reference to
In the feedback processing for calculation of the denominator term of the transfer function of the IIR digital filter, processing of cutting a low-order bit is normally necessary in the addition at the final stage. For this processing, various rounding methods such as round-down, round-up and round-off are adopted. When round-up (adding 1) is involved in rounding processing, the operation time for the rounding processing will be long if the round-up is necessary after addition at the final stage. Since round-up is processing of adding 1 (one increment), involving carrying from a low-order bit toward a higher-order bit, the operation time will be long.
The IIR digital filter of
In
In this embodiment, although the number of partial products increases compared with the IIR digital filter of Embodiment 1, the round-up processing involves no carrying. Hence, the operation time can be made shorter than when round-up for rounding processing is performed after addition at the final stage.
In the IIR digital filter of
With the above configuration, the round-up operation time can be shortened. Moreover, as already described, with the multi-input multiplier/adder circuits 4a and 5, the circuit size can be reduced, and pipelining for speedup can be adopted. Hence, a small-size, high-speed IIR digital filter can be implemented.
An IIR digital filter of Embodiment 5 of the present invention will be described with reference to
The basic circuit confirmation of
With the capability of external supply of coefficients for multiplication, the characteristics of the filter can be changed to desired ones.
In the external supply of coefficients for multiplication, if the position of the fixed decimal point is different among coefficients, the place of the least significant bit (LSB) will be different among the coefficients when the bit width of the coefficients is fixed. In this case, a correct operation will not be performed with a configuration like that in
The plurality of bit shift circuits 12a, 12b, 12N are circuits for bit-shifting the input signal by respective bit shift amounts. The bit shift amounts are amounts corresponding to the places of the LSBs of various coefficients inputted into the partial product generation circuit 7a in
With the above configuration, the characteristics of the filter can be changed to desirable ones. Moreover, as already described, with the multi-input multiplier/adder circuits, the circuit size can be reduced, and pipelining for speedup can be adopted. Hence, a small-size, high-speed IIR digital filter can be implemented.
While the configuration of the IIR digital filter was discussed above, the present invention also includes a synthesizing device for synthesizing an IIR digital filter having such a configuration. Moreover, the present invention includes, not only the IIR digital filter physically having such a configuration, but also a digital filter synthesizing program for generating such a configuration and a recording medium having such a synthesizing program recorded thereon.
As described above, the digital filter of the present invention, which uses a multi-input multiplier/adder circuit permitting pipelining, can achieve size reduction and speedup. Hence, the inventive digital filter is usable as an IIR digital filter, for example, in various types of digital signal processing, and is applicable to optical information recording devices, communication and other uses, and arithmetic devices for all types of digital signal processing.
Number | Date | Country | Kind |
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2006-215782 | Aug 2006 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2007/055542 | 3/19/2007 | WO | 00 | 2/4/2009 |