The present invention relates to a digital filter and specifically to a digital filter capable of processing data on a plurality of input channels.
Among high-precision AD converters, a ΔΣ AD converter is currently preferred as an AD converter for industrial applications. In a case of AD conversion of sensor signals, for example, the AD converter may be required to perform conversion of a plurality of inputs from the sensor. In an example application, a pressure sensor measures a differential pressure, a static pressure, and a temperature to adjust the properties of the sensor by performing an internal arithmetic operation. At this time, it is desirably required that the respective sensor outputs be obtained simultaneously. Accordingly, a plurality of ΔΣ AD converters each constituted by a ΔΣ modulator 100 and a digital filter 101 are provided in the prior art, as illustrated in
The digital filter 101 (LPF: Low Pass Filter) used in the ΔΣ AD converter is also known by the name of decimation filter. As the decimation filter, a SINC filter having a simple internal configuration is preferably used. The SINC filter can be expressed by the transfer function (1−z−N)/(1−z−1). By increasing the order of the ΔΣ modulator used in the ΔΣ AD converter, an increased effect of noise shaping can be achieved. It is well known that the order of the decimation filter (SINC filter) in the subsequent stage needs to be made higher than the order of the ΔΣ modulator.
Now, an AD converter using a second-order ΔΣ modulator, for example, is considered. As the SINC filter, a third-order filter is necessary, as illustrated in
In the configuration illustrated in
Accordingly, a register that corresponds to the bit width of data is necessary for a digital filter. The circuit scale of an addition circuit and a subtraction circuit used to add and subtract data within the register becomes larger as the bit width increases. In industrial applications, high bit resolution and high precision are much desired, and therefore, the output from a digital filter often ranges from 16 bits to 24 bits. Accordingly, the circuit scale increases. Further, if a plurality of AD converters are provided for a plurality of inputs, as illustrated in
Regarding a multi-input ΔΣ modulator that processes a plurality of inputs, a configuration with which the circuit scale and cost are reduced is proposed in Japanese Patent No. 4171222; however, a method for reducing the circuit scale and cost of a multi-input digital filter is not known.
A technique in which a plurality of AD converters are provided for a plurality of inputs is not desirable in terms of the cost and the substrate size. In the case where a plurality of AD converters are formed on a single silicon chip, the chip area increases, which leads to an increase in the unit price of the chip, and therefore, a reduction of the circuit scale and cost is desired. As described above, for a multi-input ΔΣ modulator, a configuration with which the circuit scale and cost are reduced is proposed in Japanese Patent No. 4171222; however, a method for reducing the circuit scale and cost of a multi-input digital filter is not known. Note that the issue of reducing the circuit scale and cost arises not only in an AD converter but also in any field in which a multi-input digital filter is used.
The present invention has been made to address the above-described issue, and an object thereof is to reduce the circuit scale and cost of a digital filter capable of processing data on a plurality of input channels.
A digital filter according to the present invention includes: a plurality of integration calculation units that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels (M is an integer equal to or larger than two) that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit that operates in accordance with a clock having a frequency fD×M for performing sampling on each of the channels at a frequency equal to a sampling frequency fD=fs/N (N is an integer equal to or larger than two), decimates data at the sampling frequency fs input from an integration calculation unit in a last stage among the integration calculation units at the sampling frequency fD, and delays data obtained as a result of decimation by (M−1) samples; and a plurality of difference calculation units that operate in accordance with the clock having the frequency fD×M for performing sampling on each of the channels at the frequency equal to the sampling frequency fD, are cascade-connected to an output of the frequency conversion unit, and each subtract, from data input thereto, data M samples before.
A digital filter according to the present invention includes: a multiplexer that is fed pieces of data on M channels (M is an integer equal to or larger than two) at a sampling frequency fs, and generates time-division-multiplexed data formed of the pieces of data on the M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to the sampling frequency fs; a plurality of integration calculation units that are cascade-connected to an output of the multiplexer, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit that operates in accordance with a clock having a frequency fD×M for performing sampling on each of the channels at a frequency equal to a sampling frequency fD=fs/N (N is an integer equal to or larger than two), decimates data at the sampling frequency fs input from an integration calculation unit in a last stage among the integration calculation units at the sampling frequency fD, and delays data obtained as a result of decimation by (M−1) samples; and a plurality of difference calculation units that operate in accordance with the clock having the frequency fD×M for performing sampling on each of the channels at the frequency equal to the sampling frequency fD, are cascade-connected to an output of the frequency conversion unit, and each subtract, from data input thereto, data M samples before.
According to the present invention, in response to input of time-division-multiplexed data formed of pieces of data on M channels that are time-division multiplexed, each of the integration calculation units integrates data input thereto for every M samples, the frequency conversion unit decimates, at the sampling frequency fD, data at the sampling frequency fs and delays data obtained as a result of decimation by (M−1) samples, and each of the difference calculation units subtracts, from data input thereto, data M samples before. Accordingly, unlike the prior art, it is possible to process inputs from M channels without a need to provide M digital filters, and to reduce the circuit scale and cost of the digital filter.
Further, according to the present invention, the multiplexer can be provided at the input of the digital filter to respond to a case where pieces of data on M channels are simultaneously input.
[First Embodiment]
Hereinafter, embodiments of the present invention are described with reference to the drawings.
The digital filter according to this embodiment is fed data formed of pieces of data on M channels that are time-division multiplexed, as illustrated in
The frequency conversion unit 11 operates in accordance with the clock having the frequency fD×M for performing sampling on each of the channels at the frequency equal to the sampling frequency fD=fs/N (where N, which is the frequency ratio for down-sampling, is an integer equal to or larger than two), decimates data at the sampling frequency fs input from the integration calculation unit 10 in the last stage at the sampling frequency fD, and delays data at the sampling frequency fD obtained as a result of decimation by (M−1) samples.
The flip-flop 17 in the first stage retains and outputs, for each clock having the frequency fD×M, data at the sampling frequency fs input from the integration calculation unit 10. The flip-flop 17 in the first stage operates in accordance with the clock having the frequency fD×M. Regarding the pieces of data on the respective channel, the pieces of data, which occur at the sampling frequency fs, are decimated at the sampling frequency fD.
Each of the flip-flops 17 other than the flip-flop 17 in the first stage retains and outputs, for each clock having the frequency fD×M, data at the sampling frequency fD×M input from the flip-flop 17 in the preceding stage to thereby delay the input data by one sample (by the cycle of the clock having the frequency fD×M). Time-division-multiplexed data output from the frequency conversion unit 11 is as illustrated in
As described above, in this embodiment, in order to process input time-division-multiplexed data formed of pieces of data on M channels that are time-division multiplexed, the M delay units 14 and the M delay units 15, which correspond to the number of channels M, are respectively provided in each of the integration calculation units 10 and in each of the difference calculation units 12 that constitute the digital filter. Further, in contrast to the frequency conversion unit 202 according to the prior art, which is implemented by using a single flip-flop, the frequency conversion unit 11 is constituted by the M flip-flops 17, which correspond to the number of channels M. Accordingly, unlike the prior art, it is possible to process inputs from M channels without a need to provide M digital filters, and to reduce the circuit scale and cost of the digital filter.
In the case where the plurality of digital filters 101 are provided as in the prior art illustrated in
Table 1 shows the circuit scale (combination result of FPGA (Field Programmable Gate Array)) according to the prior art and that according to this embodiment, for example. The example shown in Table 1 assumes the number of input channels to be four. That is, in the case of the prior art, four digital filters are provided. It is found that the circuit scale can be significantly reduced with this embodiment compared to the prior art.
Note that this embodiment is applicable not only to a decimation filter provided in the stage subsequent to the multi-input ΔΣ modulator proposed in Japanese Patent No. 4171222 but also to any digital filter to which time-division-multiplexed data is input.
[Second Embodiment]
The first embodiment assumes that time-division-multiplexed data is input to the digital filter; however, time-division-multiplexed data may be generated within a digital filter.
The multiplexer 18 is fed pieces of data on M channels at the sampling frequency fs and outputs the pieces of data on the M channels by sequentially selecting the channels one by one in synchronization with the clock having the frequency fs×M to thereby generate time-division-multiplexed data formed of the pieces of data on the M channels that are time-division multiplexed. As described in the first embodiment, the pieces of data on the respective channels are updated at a rate equal to the sampling frequency fs.
The remaining components are as described in the first embodiment.
Accordingly, time-division-multiplexed data can be input to the integration calculation units 10 of the digital filter in this embodiment, and therefore, an effect similar to that of the first embodiment can be achieved even if pieces of data on M channels are simultaneously input.
The first embodiment and the second embodiment do not respectively mention the bit width of signal lines from the input to the output of the digital filter illustrated in FIG. 1 and the bit width of signal lines from the input to the output of the digital filter illustrated in
The present invention is applicable to a digital filter.
10 . . . integration calculation unit, 11 . . . frequency conversion unit, 12 . . . difference calculation unit, 13 . . . addition unit, 14, 15 . . . delay unit, 16 . . . subtraction unit, 17 . . . flip-flop, 18 . . . multiplexer.
Number | Date | Country | Kind |
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2014-158463 | Aug 2014 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP2015/070238 | 7/15/2015 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2016/021382 | 2/11/2016 | WO | A |
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Combined Chinese Office Action and Search Report dated Aug. 3, 2018 in Chinese Patent Application No. 201580041167.5 (with English translation of Category of Cited Documents), 7 pages. |
International Search Report dated Sep. 8, 2015 in PCT/JP2015/070238 filed Jul. 15, 2015. |
Number | Date | Country | |
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20170222627 A1 | Aug 2017 | US |