Patent Application
20080074512
The foregoing aspects and many of the attendant advantages of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The digital image sensor has a high operating speed and is easily integrated to implement various image application products. The objects of the present invention is to eliminate the noise of an analog sensor circuit inside a digital image sensor and simplify the complex design of an analog/digital and raise the performance of the digital image sensor, reduce its cost and shorten its development time.
In the prior art, the analog sensor circuit inside the digital image sensor utilizes a correlated double sampling (CDS) circuit to cancel noise from outside and integrates a circuit-manufacturing process. The application field includes all necessary photoelectric elements to a read static graphic and dynamic image process device, such as scanners, mobile phones with cameras, micro-cameras, or monitors. In the SOC, the correlated double sampling circuit inside of the digital image sensor can obtain good output signal quality. However, the output signal readout is affected by random noise and the design of the integrated circuit because it utilizes an analog signal process.
Reference is made to
The digital reset noise signals are stored on a first memory unit 24 and the digital image signals are stored on a second memory unit 26. The first memory unit 24 or the second memory unit 26 could be a section of a memory. Herein, the memory 24,26 may be a register or a non-volatile memory. The first memory unit 24 outputs the digital reset noise signals and the second memory unit 26 outputs the digital image signals. A digital logic correcting circuit 28 receives the digital reset noise signals and the digital image signals for executing a signal correcting process and outputs at least one image sensor signal to a digital process unit 30.
Reference is made to
The sample-to-hold analog signals waveform is obtained through the sample-to-hold switch S1 to charge/discharge the sample capacitance C1.
The sample-to-hold switch S1 is turned off momentarily and obtains at least one analog reset noise signal 42. The analog reset noise signals 42 are transmitted to the analog-to-digital conversion circuit 22 for converting at least one digital reset noise signal 46. The digital reset noise signals 46 are stored on the first memory unit 24 via a first readout switch S2 being turned on and off. The sample-to-hold switch S1 is turned off so it is in a stable condition so that the sample capacitance C1 is finished charging and obtains at least one analog image signal 44. The analog image signals 44 are transmitted to the analog-to-digital conversion circuit 22 for converting at least one digital image signal 48. The digital image signals 48 are stored on the second memory unit 26 via a second readout switch S3 being turned on and off. The digital image signal 48 includes the digital reset noise signals 46.
The digital reset noise signals 46 and digital image signals 48 transmit to the digital logic correcting circuit 28. The digital logic correcting circuit 28 generates at least one image sensor signal through a third readout switch S4, then the digital logic correcting circuit 28 output end can catch clearly the image sensor signals 50. The digital logic correcting circuit 28 shown in this embodiment is a subtractor. However, the digital logic correcting circuit 28 is not limited to this kind. The digital logic correcting circuit 28 includes any digital logic circuit that is capable of achieving cancellation of the digital reset noise signals.
However, the image sensor signals 50 can also operate during the same time cycle. That means that the digital logic correcting circuit 28 execute and digitize the digital image signals 48 of the first time cycle and the digital reset noise signals 46 of the first time cycle for outputting the image sensor signals 50 directly, as is shown in
Reference is made to
The present invention samples the entire digital signals multiple times. The digital image sensor outputs a first digital signal, wherein the first digital signal includes the noise signal of a sensor signal circuit and other signals (such as offset, noise . . . etc). In addition, the real circuit sensor signal outputs a second digital signal. The first digital signal and the second digital signal write to a memory. The digital logic circuit executes the digital correcting process for the first digital signal and the second digital signal and outputs a clear image sensor signal.
The analog signal converts to the digital signal and writes to memory. It then compares the digital signal after it has been converted and the original digital image signal to cancel the KTC noise. This simple digital manner is used to replace the correlated double sampling circuit in the prior art. The present invention reduces the size of the circuit area, lowers power consumption, improves operation speed, improves image quality and can be integrated on the SOC easily.
Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are embraced within the scope of the invention as defined in the appended claims.
