Claims
- 1. A skewed NOR rising logic device for rapidly propagating a rising edge of an output signal, comprising:
a fast NOR gate rising having a large p/n channel width ratio for receiving a first input signal and a second input signal and rapidly propagating a rising edge of said output signal in response to a falling edge on both of said first input signal and said second input signal; a pull-down reset network connected in parallel with said fast NOR gate rising for resetting said output signal after said rising edge of said output signal has been propagated; and a feedback delay circuit connected in parallel with said pull-down reset network for delaying and returning said output signal back to an input of said pull-down reset network.
- 2. The skewed NOR rising logic device of claim 1, wherein said large p/n channel width ratio ranges from about 5 to about 200.
- 3. The skewed NOR rising logic device of claim 1, wherein said pull-down reset network comprises:
combinational logic having a plurality of inputs and an output; and a big NMOS transistor having a wide n-channel at least 10 μm across, a gate node connected to said output of said combinational logic, a drain node connected to said output signal and a source node connected to ground potential.
- 4. The skewed NOR rising logic device of claim 3, wherein said combinational logic performs a logical sum of products function.
- 5. The skewed NOR rising logic device of claim 3, wherein said combinational logic comprises:
a first NAND gate having a first input connected to said first input signal and a second input connected to an output of said feedback delay circuit; a second NAND gate having a first input connected to said second input signal and a second input connected to said output of said feedback delay circuit; and a third NAND gate having a first input connected to an output of said first NAND gate, a second input connected to an output of said second NAND gate and an output connected to said gate node of said big NMOS transistor.
- 6. The skewed NOR rising logic device of claim 1, wherein said feedback delay circuit comprises four inverters connected in series.
- 7. A skewed NAND rising logic device for rapidly propagating a rising edge of an output signal, comprising:
a fast NAND gate rising having a large p/n channel width ratio for receiving both a first input signal and a second input signal and rapidly propagating a rising edge of said output signal in response to falling edges on either said first input signal or said second input signal; a pull-down reset network connected in parallel with said fast NAND gate rising for resetting said output signal after said rising edge of said output signal has been propagated; and a feedback delay circuit connected in parallel with said pull-down reset network for delaying and returning said output signal to an input of said pull-down reset network.
- 8. The skewed NAND rising logic device of claim 7, wherein said large p/n channel width ratio ranges from about 5 to about 200.
- 9. The skewed NAND rising logic device of claim 7, wherein said pull-down reset network comprises:
combinational logic having a plurality of inputs and an output; and a big NMOS transistor having a wide n-channel at least 10 μm across, a gate node connected to said output of said combinational logic, a drain node connected to said output signal and a source node connected to ground potential.
- 10. The skewed NAND rising logic device of claim 9, wherein said combinational logic performs a logical AND function.
- 11. The skewed NAND rising logic device of claim 9, wherein said combinational logic comprises:
a 3-input NAND gate having a first input connected to said first input signal, a second input connected to said second input signal and a third input connected to an output of said feedback delay circuit; and an inverter having input connected to an output of said 3-input NAND gate and an output connected to said gate node of said big NMOS transistor.
- 12. The skewed NAND rising logic device of claim 7, wherein said feedback delay circuit comprises four inverters connected in series.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No. 09/922,027, filed Aug. 3, 2001, pending.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09922027 |
Aug 2001 |
US |
Child |
10336359 |
Jan 2003 |
US |