Claims
- 1. A downward pulse stretcher circuit for widening a downward pulse comprising:
a skewed inverter rising logic device for receiving a downward pulse input signal, said downward pulse input signal having a first pulse width and transmitting an intermediate pulse signal; and a skewed inverter falling logic device for receiving said intermediate pulse signal and outputting a downward pulse output signal having a second pulse width, said second pulse width being wider than said first pulse width.
- 2. A downward pulse stretcher module for selectively widening a downward pulse input signal comprising a selectable number n of downward pulse stretcher circuits connected in series, each downward pulse stretcher circuit comprising:
a skewed inverter rising logic device for receiving a downward pulse input signal, said downward pulse input signal having a first pulse width and transmitting an intermediate pulse signal; and a skewed inverter falling logic device for receiving said intermediate pulse signal and outputting a downward pulse output signal having a second pulse width, said second pulse width being wider than said first pulse width.
- 3. An upward pulse stretcher circuit for widening an upward pulse comprising:
a skewed inverter falling logic device for receiving an upward pulse input signal, said upward pulse input signal having a first pulse width and transmitting an intermediate pulse signal; and a skewed inverter rising logic device for receiving said intermediate pulse signal and outputting an upward pulse output signal having a second pulse width, said second pulse width being wider than said first pulse width.
- 4. An upward pulse stretcher module for selectively widening an upward pulse input signal comprising a selectable number n of upward pulse stretcher circuits, each upward pulse stretcher circuit comprising:
a skewed inverter falling logic device for receiving an upward pulse input signal, said upward pulse input signal having a first pulse width and transmitting an intermediate pulse signal; and a skewed inverter rising logic device for receiving said intermediate pulse signal and outputting an upward pulse output signal having a second pulse width, said second pulse width being wider than said first pulse width.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No. 09/922,027, filed Aug. 3, 2001, pending.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09922027 |
Aug 2001 |
US |
Child |
10336386 |
Jan 2003 |
US |