Claims
- 1. A skewed inverter falling logic device for rapidly propagating a falling edge of an output signal comprising:
a fast inverter falling having a large n/p channel width ratio for receiving an input signal and rapidly propagating a falling edge onto said output signal in response to receiving a rising edge on said input signal; a pull-up reset network connected in parallel to said fast inverter falling for resetting said output signal after said falling edge has been propagated onto said output signal; and a feedback delay circuit connected in parallel with said pull-up reset network for delaying and returning said output signal to said pull-up reset network.
- 2. The skewed inverter falling logic device of claim 1, wherein said large n/p channel width ratio ranges from about 5 to about 200.
- 3. The skewed inverter falling logic device of claim 1, wherein said pull-up reset network includes:
combinational logic having a plurality of inputs and an output; and a big PMOS transistor having a wide p-channel greater than 10 μm across, a gate node driven by said output of said combinational logic, a source node connected to a supply voltage and a drain node connected to said output signal.
- 4. The skewed inverter falling logic device of claim 3, wherein said combinational logic includes:
a NOR gate having a first input connected to an output of said feedback delay circuit and a second input connected to said input signal; and an inverter having an input connected to an output of said NOR gate and an output driving said gate node of said big PMOS transistor.
- 5. The skewed inverter falling logic device of claim 3, wherein said combinational logic includes:
a first inverter having an input connected to an output of said feedback delay circuit; a second inverter having an input connected to said input signal; a NAND gate having a first input connected to an output of said first inverter, a second input connected to an output of said second inverter and an output driving said gate node of said big PMOS transistor.
- 6. The skewed inverter falling logic device of claim 3, wherein said combinational logic includes:
an OR gate having a first input connected to an output of said feedback delay circuit and a second input connected to said input signal; and a delay element having an input connected to an output of said OR gate and an output driving said gate node of said big PMOS transistor.
- 7. The skewed inverter falling logic device of claim 3, wherein said combinational logic includes:
an OR gate having a first input connected to an output of said feedback delay circuit and a second input connected to said input signal; and a buffer having an input connected to an output of said OR gate and an output driving said gate node of said big PMOS transistor.
- 8. The skewed inverter falling logic device of claim 1, wherein said feedback delay circuit comprises four inverters connected in series.
- 9. The skewed inverter falling logic device of claim 1, wherein said feedback delay circuit comprises four buffers connected in series.
- 10. The skewed inverter falling logic device of claim 1, wherein said feedback delay circuit comprises two buffers and two inverters connected in series.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No. 09/922,027, filed Aug. 3, 2001, pending.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09922027 |
Aug 2001 |
US |
Child |
10336502 |
Jan 2003 |
US |