Claims
- 1. A skewed buffer falling logic device for rapidly propagating a falling edge of an output signal comprising:
a fast inverter rising having a large p/n channel width ratio for receiving a falling edge of an input signal and rapidly propagating a rising edge of an intermediate signal in response thereto; a fast inverter falling having a large n/p channel width ratio and in series with said fast inverter rising for receiving said rapidly propagated rising edge of said intermediate signal and rapidly propagated falling edge of said output signal; a reset network coupled to said fast inverter rising and said fast inverter falling for resetting output signals of said fast inverter rising and said fast inverter falling after said falling edge of said output signal has been rapidly propagated; and a feedback delay circuit operably coupled between an output of said fast inverter falling and an input of said reset network for propagating said output signal to said reset network.
- 2. The skewed buffer falling logic device of claim 1, wherein said large p/n channel width ratio ranges from about 5 to about 200.
- 3. The skewed buffer falling logic device of claim 1, wherein said large n/p channel width ratio ranges from about 5 to about 200.
- 4. The skewed buffer falling logic device of claim 1, wherein said reset network comprises:
combinational logic for receiving said input signal; a big NMOS pull-down transistor having a wide n-channel at least 10 μm across, a gate node connected to an output of said combinational logic, a drain node connected to said intermediate signal and a source node connected to ground potential; an inverter having input connected to said gate node of said big NMOS pull-down transistor; and a big PMOS pull-up transistor having a wide p-channel at least 10 μm across, a gate node driven by said inverter, a source node connected to a supply voltage and a drain node connected to said output signal.
- 5. The skewed buffer falling logic device of claim 4, wherein said combinational logic performs a logical AND function.
- 6. The skewed buffer falling logic device of claim 4, wherein said combinational logic comprises:
a NAND gate with a first input connected to said input signal and a second input connected to an output of said feedback delay circuit; and a second inverter having an input connected to an output of said NAND gate and an output connected to said gate node of said big NMOS pull-down transistor.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of application Ser. No. 09/922,027, filed Aug. 3, 2001, pending.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09922027 |
Aug 2001 |
US |
Child |
10336355 |
Jan 2003 |
US |