Digital logical sequence controller

Abstract

A sequence controller of the digital logical circuit type, comprising a sequence program part and a processing circuit, wherein the desired sequence instruction is read from the sequence program part, and the sequence is processed and controlled by the processing circuit. A certain definite level is set at a branch point in an equivalent sequential circuit according to the path along which a signal of the sequential circuit is transmitted. This level and the on-off state of the branch point are stored in a memory. The given data are processed and controlled through the sequence program part and the memory.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to sequence controllers of the digital logical circuit type, in which the desired sequence instruction is read from its sequence program part, and the sequence is processed and controlled in its processing circuit.

2. Description of the Prior Art

Being indispensable in the present-day industrialized society, the sequence control technique is widely used in the field of industrial process control, such as power plant and substation control, conveyor system control, machine tool control, assembly line control in the automotive plant, and rolling line control. For these controls, the contact relay sequence control has long been used. This type of sequence control, however, is inconvenient for applications where design modifications are often made on a control system, resulting in degradation of reliability. Recently, the controlled objectives have become much more sophisticated which has necessitated the use of an increasing number of relays, with the result that the logical design has become intricate and the approach to higher speed control has become more difficult.

One solution to this problem in the prior art is the sequence controller with computer-like control functions adapted to sequence controls, in which a program (i.e., a pattern of sequence control operation) is stored in a core memory by way of the keyboard according to a predetermined specific format, the process state is sampled at certain time intervals and compared with the stored data, and an output is generated according to the result.

This sequence controller operates in general on flow-chart system or Boolean algebraic system (conversion system) through programming. When a relay sequence is programmed for a computer, the necessary logical operation is expressed in terms of Boolean algebra, which is programmed and stored in a core memory of the sequence controller. This Boolean algebraic system offers high processing efficiency.

This programming control will be described by way of example with reference to FIGS. 1 through 3. A sequence diagram as shown in FIG. 1 may be expressed by Boolean algebraic equations as follows.

Y.sub.1 = (X.sub.1 + X.sub.3).sup.. X.sub.2 = X.sub.1 .sup.. X.sub.2 + X.sub.3 .sup.. X.sub.2 ( 1) y.sub.2 = x.sub.4 .sup.. x.sub.5 + x.sub.6 ( 2) where X.sub.1 to X.sub.6 stand for input contacts, among which X.sub., X.sub.3, X.sub.4 and X.sub.5 are make-contacts which close the individual circuits when the coil is excited, and X.sub.2 and X.sub.6 are break-contacts which open the individual circuits when the coil is excited; and Y.sub.1 and Y.sub.2 denote output relays.

FIG. 2 is a block diagram showing a conventional digital logical circuit type sequence controller with functions equivalent to those of the above-mentioned relay sequence circuit. In FIG. 2, X.sub.1, X.sub.2, X.sub.3, . . . denote contacts of external inputs, and the numeral 1 represents an input selection circuit which selects the necessary input contact and supplies datum of the state of the selected input contact to a logical processing circuit 2 which is capable of performing a given sequence processing. The numeral 3 denotes an output control circuit which holds the specific output relays Y.sub.1 and Y.sub.2 in on or off state according to the processed result reached by the processing circuit 2. The numeral 4 represents a sequence program storage circuit which stores sequence programs and reads them in sequence and supplies the read program to the processing circuit 2. An example of this processing circuit is illustrated in block form in FIG. 3, in which FF.sub.1, FF.sub.2 and FF.sub.3 denote flip-flop circuits, AND a logical AND circuit, OR a logical OR circuit, and G.sub.1 to G.sub.5 gates. This circuit performs processing as summarized below in reference to Y.sub.1 as in Eq. (1).

Memory Address Sequence Instruction Processing______________________________________1 LOAD X.sub.1 1 X.sub.1 .fwdarw.FF.sub.1 2 FF.sub.1 .fwdarw.FF.sub.2 3 O.fwdarw.FF.sub.32 AND X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 2 FF.sub.1. FF.sub.2 .fwdarw.FF.sub.23 OR X.sub.3 1 X.sub.3 .fwdarw.FF.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 3 FF.sub.1 .fwdarw.FF.sub.24 AND X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 2 FF.sub.1. FF.sub.2 .fwdarw.FF.sub.25 SET Y.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 3 FF.sub.3 .fwdarw.OUT Y.sub.1______________________________________ (Note: The numerals 1 , 2 , and 3 indicate the timing sequence for the processing.)

When a sequence instruction LOAD X.sub.1 at memory address 1 is read from a memory in the sequence program storage circuit 4, this instruction is decoded and the state of input contact X.sub.1 is stored in the flip-flop FF.sub.1. Then the gates G.sub.1 and G.sub.3 are opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2, and the binary code "0" is stored as an initial set signal in the flip-flop FF.sub.3. Then, when another sequence instruction AND X.sub.2 at address 2 is read from a memory in the sequence program storage circuit 4, the state of complement X.sub.2 of input contact X.sub.2 is stored in the flip-flop FF.sub.1, and the gate G.sub.2 is opened whereby the flip-flops FF.sub.1 and FF.sub.2 undergo AND logic and the result is stored in the flip-flop FF.sub.2. The state of input contact X.sub.3 is stored in the flip-flop FF.sub.1 by another sequence instruction OR X.sub.3. Then the gate G.sub.4 is opened whereby the flip-flops FF.sub.2 and FF.sub.3 undergo OR logic, and the result is transferred to the flip-flop FF.sub.3. After this step, the gate G.sub.1 is opened whereby the datum stored in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2. When an instruction AND X.sub.2 at address 4 is read, the same processing as performed by the instruction at address 2 is carried out. Then, when an instruction SET Y.sub.1 at address 5 comes in, the gate G.sub.4 is opened whereby the flip-flops FF.sub.2 and FF.sub.3 undergo OR logic, and the result is transferred to the flip-flop FF.sub.3. After this step, the gate G.sub.5 is opened to allow the datum in the flip-flop FF.sub.3 to be delivered to the output relay Y.sub.1 through the output control circuit 3.

Thus, the Boolean algebraic equation, X.sub.1 .sup.. X.sub.2 + X.sub.3 .sup.. X.sub.2 = Y.sub.1, is executed by the sequence instructions at addresses 1 to 5. In the same manner, Boolean algebraic equations expressed by polynomials of AND and OR can be converted into sequence instructions one after another. The sequence instructions are read one after another from the memory of the sequence program storage circuit 4 and executed repeatedly at high speed. Hence the sequence controller shown in FIG. 2 performs functions equivalent to those of the relay sequence shown in FIG. 1. When the relay sequence forms a loop as shown in FIG. 4, this sequence may be expressed in Boolean algebra as follows.

Y.sub.1 = X.sub.1 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.3 .sup.. X.sub.2 + X.sub.4 .sup.. X.sub.5 X.sub.6 + X.sub.1 .sup.. X.sub.3 .sup.. X.sub.5 .sup.. X.sub.6 ( 3) y.sub.2 = x.sub.4 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.3 .sup.. x.sub.5 + x.sub.1 .sup.. x.sub.2 .sup.. x.sub.6 + x.sub.4 .sup.. x.sub.3 .sup.. x.sub.2 .sup.. x.sub.6 ( 4) because all the loops are to be considered, these Boolean equations are inevitably complicated. If the relay sequence comprises intricate loops, it will become extremely difficult to convert all the logical paths into Boolean equations, and a considerable amount of effort must be made to build a complete sequence program.

SUMMARY OF THE INVENTION

An object of the invention is to provide an improved sequence controller free of the prior art drawbacks.

Another object of the invention is to provide a sequence controller with which a sequence program can readily be constructed.

Still another object of the present invention is to provide a sequence controller which is readily adaptable to a variety of sequence control applications.

A further object of the invention is to provide a sequence controller which meets the above objects yet is low in cost.

Other objects will appear hereinafter.

These and other objects are achieved in accordance with the present invention which utilizes a sequence controller of the digital logical circuit type capable of operation in which a necessary sequence instruction is read from the sequence program storage and the sequence is processed by the processing circuit; and which includes a certain definite level set at a branch point in an equivalent sequence circuit according to the path along which the signal of the sequence circuit is transmitted. This level and the on-off state of the branch point are stored in a memory, and given data are processed through the sequence program storage and the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a relay sequence,

FIG. 2 is a block diagram showing an example of a conventional sequence controller,

FIG. 3 is a block diagram of a processing circuit used with the sequence controller shown in FIG. 2,

FIG. 4 is a diagram showing an example of a relay sequence comprising complicated loops,

FIG. 5 is a block diagram showing a sequence controller according to the invention, and

FIG. 6 is a block diagram showing a processing circuit used with the sequence controller shown in FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the invention will be described by referring to FIG. 5. Like constituent elements are indicated by the indentical symbols in FIGS. 2 and 5. In FIG. 5, the numeral 5 denotes a memory which stores the on-off state of a branch relay point i.e., a branch point where an input contact is connected to another input contact or to an output relay contact on a sequence diagram, and which also stores a level corresponding to the number of relay points through which a signal passes so as to turn on one relay point. FIG. 6 shows in block form a processing circuit 2 as in FIG. 5. Like constituent elements are indicated by the identical references in FIGS. 3 and 6. In FIG. 6, LR.sub.1, LR.sub.2 and LR.sub.3 denote level registers indicating levels at the relay points, COMP.sub.1 denotes a comparator which compares two levels with each other and generates an output of the larger level, COMP.sub.2 denotes a comparator which compares two levels with each other and generates an output of the smaller level, COMP.sub.3 denotes a comparator and adder which compares two levels with each other and generates an output of the smaller level plus 1, and Ga to Ge denote gates of level data. The symbol MAX represents the maximum number of levels which can be stored in the level register LR.sub.3.

The operation of this sequence controller will be described below by referring to the sequence diagram shown in FIG. 4. The relay sequence may be expressed in terms of Boolean algebra as follows.

P.sub.1 = X.sub.1 + X.sub.3 .sup.. P.sub.3 + X.sub.2 .sup.. P.sub.2 (5) p.sub.2 = x.sub.2 .sup.. p.sub.1 + x.sub.6 .sup.. p.sub.4 (6) p.sub.3 = x.sub.4 + x.sub.3 .sup.. p.sub.1 + x.sub.5 .sup.. p.sub.4 (7) p.sub.4 = x.sub.5 .sup.. p.sub.3 + x.sub.6 .sup.. p.sub.2 (8) y.sub.1 = p.sub.2 (9) y.sub.2 = p.sub.4 (10) where P.sub.1, P.sub.2, P.sub.3 and P.sub.4 represent relay points (branch points) at which input contacts X.sub.1 to X.sub.6 and/or relay contacts Y.sub.1 and Y.sub.2 are connected to each other.

The on-off states of the relay points P.sub.1 to P.sub.4 are stored in a memory 5 whereby these relay points may be regarded to be equivalent to the input contacts. Then, assume that the input contact X.sub.1 turns on whereby the relay point P.sub.1 turns on, and the input contact X.sub.3 turns on whereby the relay point P.sub.3 turns on, and then X.sub.1 turns off. Theoretically, under this condition, the relay point P.sub.1 assumes on-state depending on the condition of X.sub.3 P.sub.3, and the relay point P.sub.3 remains in on-state depending on the condition of X.sub.3 P.sub.1, as opposed to the practically desired condition where both P.sub.1 and P.sub.3 are in off-state. This makes it impossible to indicate any off-state on a practical relay sequence diagram. To solve this problem, levels are set at the individual relay points P.sub.1 through P.sub.4, so that one level is higher by 1 than another as a signal proceeds from one relay point to another. By so setting the levels, a relay point where the level is low cannot be turned on from a relay point where the level is high. By this arrangement, the input contact X.sub.1 turns on whereby the relay point P.sub.1 turns on (level 1), and the input contact X.sub.3 turns on whereby the relay point P.sub.3 turns on (level 2). After this step, when the input contact X.sub.1 turns off, the relay point P.sub.1 (level 1) turns off since the condition of X.sub.3 P.sub.3 is level 2. Accordingly, the relay point P.sub.3 turns off. Thus the on and off states correspond to the actual sequence diagram. (Note: The input contacts X.sub.1, X.sub.2, . . . always stand at level 0.)

To illustrate the invention, the operations of this relay sequence are summarized below in terms of Boolean algebra, Eq. (5), P.sub.1 = X.sub.1 + X.sub.3 .sup.. P.sub.3 + X.sub.2 .sup.. P.sub.2.

__________________________________________________________________________Memory SequenceAddress Instruction Processing__________________________________________________________________________1 LOAD X.sub.1 1 X.sub.1 .fwdarw.FF.sub.1 1 L(X.sub.1) .fwdarw.LR.sub.1 2 FF.sub.1 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub.2 3 0.fwdarw.FF.sub.3 3 MAX.fwdarw.LR.sub.32 OR X.sub.3 1 X.sub.3 .fwdarw.FF.sub.1 1 L(X.sub.3).fwdarw.LR.sub.1 2 FF.sub.2 +FF.sub.3 .fwdarw.FF.sub.3 2 LR.sub.2 .fwdarw.LR.sub.3 only when FF.sub.2 = 1 and LR.sub.2 < LR.sub.3 3 FF.sub.1 .fwdarw.FF.sub.2 3 LR.sub.1 .fwdarw.LR.sub.23 AND P.sub.3 1 P.sub.3 .fwdarw.FF.sub.1 1 L(P.sub.3).fwdarw.LR.sub.1 2 FF.sub.1.FF.sub.2 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub.2 when LR.sub.1 > LR.sub.24 OR X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 1 L(X.sub.2).fwdarw.LR.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 2 LR.sub.2 .fwdarw.LR.sub.3 only when FF.sub.2 = 1 and LR.sub.2 < LR.sub.3 3 FF.sub.1 .fwdarw.FF.sub.2 3 LR.sub.1 .fwdarw.LR.sub.25 AND P.sub.2 1 P.sub.2 .fwdarw.FF.sub.1 1 L(P.sub.2).fwdarw.LR.sub.1 2 FF.sub.1 .FF.sub.2 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub.2 when LR.sub.1 > LR.sub.26 SET P.sub.1 1 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 1 LR.sub.2 .fwdarw.LR.sub.3 only when FF.sub.2 = 1 and LR.sub.2 < LR.sub.32 FF.sub.3 .fwdarw.OUT P.sub.1 2 LR.sub.3 + 1.fwdarw.L(P.sub.1) whenwhen L(P.sub.1) .gtoreq. LR.sub.3 L(P.sub.1) .gtoreq. LR.sub.30.fwdarw.OUT P.sub.1 MAX.fwdarw.L(P.sub.1) whenwhen L(P.sub.1) < LR.sub.3 L(P.sub.1) < LR.sub.3__________________________________________________________________________ (Note: The numerals 1 , 2 , and 3 indicate the timing sequence for the processing, and X.sub.1, X.sub.2, .....always stand at level 0.)

When a sequence instruction LOAD X.sub.1 at address 1 is read from a memory in the sequence program part 4, this instruction is decoded, and the state of input contact X.sub.1 is stored in the flip-flop FF.sub.1. Then the gate G.sub.1 is opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2, and the binary code 0 is stored as an initial set in the flip-flop FF.sub.3. On the other hand, the level 0 of the contact X.sub.1 is registered in the level register LR.sub.1, and the gate Ga is opened whereby the data in the level register LR.sub.1 is transferred to the level register LR.sub.2. The level register LR.sub.3 is initially set to a maximum value MAX. Then, when another sequence instruction OR X.sub.3 at address 2 is read from the memory in the sequence program part 4, the state of input contact X.sub.3 is stored in the flip-flop FF.sub.1, the gate G.sub.4 is opened, and a logic OR combination of flip-flops FF.sub.2 and FF.sub.3 by OR circuit OR is stored in the flip-flop FF.sub.3. Then the gate G.sub.1 is opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2. The level 0 of input contact X.sub.3 is stored in the level register LR.sub.1. The gate Gd opens only when the flip-flop FF.sub.2 is on (i.e., X.sub.1 is on). If the level of the level register LR.sub.2 is smaller than that of the level register LR.sub.3, the comparator COMP.sub.2 generates an output of data in the level register LR.sub.2, which is stored in the level register LR.sub.3. Then the gate Ga is opened whereby the data in the level register LR.sub.1 is transferred to the level register LR.sub.2. After this step, another sequence instruction AND P.sub.3 at address 3 is given whereby the state of relay point P.sub.3 is read from the memory 5. This data is stored in the flip-flop FF.sub.1. Then the gate G.sub.2 is opened whereby a logic AND combination of flip-flops FF.sub.1 and FF.sub.2 by AND circuit is stored in the flip-flop FF.sub.2. The level of relay point P.sub.3 which is stored in the memory 5 is registered in the level register LR.sub.1. When the level of the level register LR.sub.1 is larger than that of the level register LR.sub.2, the comparator COMP.sub.1 generates an output of data in the level register LR.sub.1, which is stored in the level register LR.sub.2 through the gate Gb. Then, by another sequence instruction OR X.sub.2 at address 4, the state of input contact X.sub.2 is stored in the flip-flop FF.sub.1. The gate G.sub.4 is opened and an OR logic combination of flip-flops FF.sub.1 and FF.sub.3 by OR circuit is stored in the flip-flop FF.sub.3. After this step, the gate G.sub.1 is opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2. On the other hand, the level 0 of input contact X.sub.2 is registered in the level register LR.sub.1. When the flip-flop FF.sub.2 is on (i.e., both P.sub.3 and X.sub.3 are on), the gate Gd opens. Thus, if the level of the level register LR.sub.2 is smaller than that of the level register LR.sub.3, the comparator COMP.sub.2 generates an output of data in the level register LR.sub.2, which is stored in the level register LR.sub.3. Then the gate Ga is opened whereby the data in the level register LR.sub.1 is transferred to the level register LR.sub.2. Next, by another sequence instruction AND P.sub.2 at address 5, the state of the relay point P.sub.2 is read from the memory 5, which is stored in the flip-flop FF.sub.1. The gate G.sub.2 is opened and a logical AND combination of flip-flops FF.sub.1 and FF.sub.2 by AND circuit is stored in the flip-flop FF.sub.2. While the level of the relay point P.sub.2 which is stored in the memory 5 is read and registered in the level register LR.sub.1, the gate Gb is opened and if the level of the level register LR.sub.1 is larger than that of the level register LR.sub.2, the data in the level register LR.sub.1 is transferred to the level register LR.sub.2. Then by another sequence instruction SET P.sub.1 at address 6, the gate G.sub.4 opens and a logical OR combination of flip-flops FF.sub.2 and FF.sub.3 by OR circuit is transferred to the flip-flops FF.sub.3. On the other hand, the gate Gd is opened only when the flip-flop FF.sub.2 is on (i.e., both P.sub.2 and X.sub.2 are on). If the level of the level register LR.sub.2 is smaller than that of the level register LR.sub.3, the comparator COMP.sub.2 generates an output of data in the level register LR.sub.2, which is stored in the level register LR.sub.3. Then the level of the relay point P.sub.1 is read from the memory 5. This level is compared with the level of the level register LR.sub.3 by the comparator COMP.sub.3. When the level of the relay point P.sub.1 is larger than or equal to that of the level register LR.sub.3, the gate G.sub.5 is opened whereby the data in the flip-flop FF.sub.3 is stored in the memory 5. When the level of the relay point P.sub.1 is smaller than that of the level register LR.sub.3, the binary code 0 is stored in the P.sub.1 memory part. Then the level of the relay point P.sub.1 is read from the memory 5. This level is compared with the level of the level register LR.sub.3 by the comparator COMP.sub.3. When the level of the relay point P.sub.1 is larger than or equal to that of the level register LR.sub.3, the gate Ge is opened, and 1 is added to the data in the level register LR.sub.3. The result of data is stored in the P.sub.1 memory part of the memory 5. When the level of the relay point P.sub.1 is smaller than that of the level register LR.sub.3, the P.sub.1 memory part of the memory 5 is set to a maximum level value MAX. In the above manner, the Boolean algebraic equation, P.sub.1 = X.sub.1 + X.sub.3 .sup.. P.sub.3 + X.sub.2 .sup.. P.sub.2, is executed by the sequence instructions at addresses 1 to 6.

The operation of the relay sequence will further be described in terms of Boolean Eq. (6), P.sub.2 = X.sub.2 .sup.. P.sub.1 + X.sub.6 .sup.. P.sub.4 as summarized below.

__________________________________________________________________________Memory SequenceAddress Instruction Processing__________________________________________________________________________7 LOAD X.sub.2 1 X.sub.2 .fwdarw.FF.sub.1 1 L(X.sub.2).fwdarw.LR.sub.1 2 FF.sub.1 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub.2 3 0.fwdarw.FF.sub.3 3 MAX.fwdarw.LR.sub.38 AND P.sub.1 1 P.sub.1 .fwdarw.FF.sub.1 1 L(P.sub.1).fwdarw.LR.sub.1 2 FF.sub.1.FF.sub.2 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub.2 when LR.sub.1 > LR.sub.29 OR X.sub.6 1 X.sub.6 .fwdarw.FF.sub.1 1 L(X.sub.6).fwdarw.LR.sub.1 2 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 2 LR.sub.2 .fwdarw.LR.sub.3 only when FF.sub.2 = 1, and LR.sub.2 < LR.sub.3 3 FF.sub.1 .fwdarw.FF.sub.2 3 LR.sub.1 .fwdarw.LR.sub.210 AND P.sub.4 1 P.sub.4 .fwdarw.FF.sub.1 1 L(P.sub.4).fwdarw.LR.sub.1 2 FF.sub.1 .FF.sub.2 .fwdarw.FF.sub.2 2 LR.sub.1 .fwdarw.LR.sub. 2 when LR.sub.1 > LR.sub.211 SET P.sub.2 1 FF.sub.2 + FF.sub.3 .fwdarw.FF.sub.3 1 LR.sub.2 .fwdarw.LR.sub.3 only when FF.sub.2 = 1 and LR.sub.2 < LR.sub.3 2 FF.sub.3 .fwdarw.OUT P.sub.2 2 LR.sub.3 + 1.fwdarw.L(P.sub.2) when when L(P.sub.2) .gtoreq. LR.sub.3 L(P.sub.2) .gtoreq. LR.sub.3 0.fwdarw.OUT P.sub.2 MAX.fwdarw.L(P.sub.2) when when L(P.sub.2) < LR.sub.3 L(P.sub.2) < LR.sub.3__________________________________________________________________________

More specifically, when a sequence instruction LOAD X.sub.2 at address 7 is read from a memory in the sequence program part 4, this instruction is decoded and the state of input contact X.sub.2 is stored in the flip-flop FF.sub.1. Then the gate G.sub.1 is opened whereby the data in the flip-flop FF.sub.1 is stored in the flip-flop FF.sub.2, and the binary code 0 is stored in the flip-flop FF.sub.3. On the other hand, the level 0 of the contact X.sub.2 is registered in the level register LR.sub.1. When the gate Ga opens, the data in the level register LR.sub.1 is transferred to the level register LR.sub.2. The level register LR.sub.3 is set to a maximum level value. Then, by another sequence instruction AND P.sub.1 at address 8, the state of the relay point P.sub.1 is read from the memory 5 and stored in the flip-flop FF.sub.1. The gate G.sub.2 opens and a logical AND combination of flip-flops FF.sub.1 and FF.sub.2 by AND circuit is stored in the flip-flop FF.sub.2. The level of the relay point P.sub.1 which is stored in the memory 5 is registered in the level register LR.sub.1. When the level of the level register LR.sub.1 is larger than that of the level register LR.sub.2, the comparator COMP.sub.1 generates an output of data in the level register LR.sub.1. Then the gate Gb is opened and this data is stored in the level register LR.sub.2. After this set, the state of input contact X.sub.6 is stored in the flip-flop FF.sub.1 by another sequence instruction OR X.sub.6 at address 9. Then the gate G.sub.4 is opened and a logical OR combination of flip-flops FF.sub.2 and FF.sub.3 by OR circuit is stored in the flip-flop FF.sub.3. The gate G.sub.1 is opened whereby the data in the flip-flop FF.sub.1 is transferred to the flip-flop FF.sub.2. The level 0 of the input contact X.sub.6 is stored in the level register LR.sub.1. The gate Ga opens only when the flip-flop FF.sub.2 is on. If the level of the level register LR.sub.2 is smaller than that of the level register LR.sub.3, the comparator COMP.sub.2 generates an output of data in the level register LR.sub.2, which is transferred to the level register LR.sub.3. Then the gate Ga is opened and the data in the level register LR.sub.1 is transferred to the level register LR.sub.2.

After this step, the state of the relay point P.sub.4 is read from the memory 5 by another sequence instruction AND P.sub.4 at address 10. This data is stored in the flip-flop FF.sub.1. Then the gate G.sub.2 is opened and a logical AND combination of flip-flops FF.sub.1 and FF.sub.2 by AND circuit is stored in the flip-flop FF.sub.2. The level of the relay point P.sub.4 which is stored in the memory 5 is read and stored in the level register LR.sub.1. The gate Gb is thereby opened, and when the level of the level register LR.sub.1 is larger than that of the level register LR.sub.2, the data in the level register LR.sub.1 is transferred to the level register LR.sub.2.

The gate G.sub.4 is opened by another sequence instruction SET P.sub.2 at address 11, and a logical OR combination of flip-flops FF.sub.2 and FF.sub.3 by OR circuit is transferred to the flip-flop FF.sub.3. The gate Gd is opened only when the flip-flop FF.sub.2 is on. When the level of the level register LR.sub.2 is smaller than that of the level register LR.sub.3, the comparator COMP.sub.2 generates an output of data in the level register LR.sub.2, which is stored in the level register LR.sub.3. Then, this level is compared with the level of the relay point P.sub.2 by the comparator COMP.sub.3. When the level of the relay point P.sub.2 is larger than or equal to that of the level register LR.sub.3, the gate G.sub.5 opens whereby the data in the flip-flop FF.sub.3 is stored in the P.sub.2 memory part of the memory 5. When the level of the relay point P.sub.2 is smaller than that of the level register LR.sub.3, the binary code 0 is stored in the P.sub.2 memory part. When the level of the relay point P.sub.2 is larger than or equal to that of the level register LR.sub.3, the gate Ge opens and 1 is added to the data in the level register LR.sub.3. The resultant data is stored in the P.sub.2 memory part of the memory 5. When the level of the relay point P.sub.2 is smaller than that of the level register LR.sub.3, the P.sub.2 memory part of the memory 5 is set to a maximum level value MAX. In the above manner, the Boolean equation, P.sub.2 = X.sub.2 .sup.. P.sub.1 + X.sub.6 .sup.. P.sub.4, is executed on the sequence instructions at addresses 7 to 11.

In the same manner as above, Boolean Eqs. (7) to (10) can be converted respectively into sequence programs.

Because this sequence program is executed repeatedly at high speed, the sequence controller shown in FIG. 5 performs functions equivalent to those of the relay sequence shown in FIG. 4.

According to the invention, as has been described above, the branch points where input contacts and/or relay contacts on a sequence diagram are connected to each other are used as relay points. The on and off states of these relay points and the levels corresponding to the number of relay points by way of which one relay point is turned on are stored in a memory and a given data is processed according to the level. Accordingly, the sequence program can be set up exactly according to Boolean algebraic equations using relay points. Because these Boolean equations can be easily derived, this sequence controller can provide a sequence program quickly and accurately. In other words, the sequence controller of this invention can readily be adapted to a wide variety of sequence control applications.

While one preferred embodiment of the invention has been described and illustrated in detail, it is to be clearly understood that this should not be construed as necessarily limiting the scope of the invention, since it is apparent that many changes can be made to the disclosed principles by those skilled in the art in order to suit particular applications.

Claims

1. A sequence controller comprising:

an input selection circuit;

a logical processing circuit;

an output control circuit;

a sequence program storage circuit;

a memory circuit;

means connecting a plurality of input contacts to the input selection circuit;

means connecting the input selection circuit to the logical processing circuit;

means connecting the logical processing circuit and the memory circuit;

means connecting the memory circuit and the logical processing circuit to the output control circuit;

means connecting the sequence program storage circuit to the logical processing circuit;

means connecting a plurality of output relays to the output control circuit to be controlled thereby;

the sequence program storage circuit storing a relay sequence having branch points;

the level of each branch point and its on-off state being stored in the memory circuit;

whereby data from the plurality of input contacts is processed in accordance with the relay sequence stored in the sequence program storage circuit to control the output relays.

2. A sequence controller as claimed in claim 2 wherein the logical processing circuit comprises:

a logical processing part for performing logical operations in accordance with a Boolean algebraic equation and

a level processing part for processing the levels of the branch points.

3. A sequence controller as claimed in claim 2 wherein the logical processing part comprises:

a first memory circuit for temporarily storing input data,

a second memory circuit for temporarily storing data stored in the first memory circuit,

an AND circuit for performing AND logic on the data stored in the first and second memory circuits and supplying the resultant data to the second memory circuit,

a third memory circuit for receiving and storing an initial set signal and

an OR circuit for performing OR logic on the data stored in the second and third memory circuits and supplying the resultant data to the third memory circuit to be derived as an output.

4. A sequence controller as claimed in claim 2 wherein the level processing part comprises:

a first level register for temporarily storing an input level,

a second level register for receiving and temporarily storing the level stored in the first level register,

a first comparator for comparing the level of the first level register with the level of the second level register and supplying the larger level to the second level register,

a third level register for receiving and storing an initial set signal,

a second comparator for comparing the level stored in the second level register with the level stored in the third level register and supplying the smaller level to the third level register, and

a third comparator for comparing the level stored in the third level register with the level of a branch point stored in the memory means and generating an output signal representing the smaller level plus one.

5. A sequence controller as claimed in claim 2 wherein the logical processing part comprises:

first, second, third and fourth gates,

a first flip-flop for temporarily storing input data,

a second flip-flop for receiving the output of the first flip-flop through the first gate,

an AND element for performing AND logic on the output of the first flip-flop and the output of the second flip-flop and supplying the resultant data to the second flip-flop through the second gate,

a third flip-flop for receiving an initial set signal through the third gate,

an OR element for performing OR logic on the output of the second flip-flop and the output of the third flip-flop and supplying the resultant data to the third flip-flop through the fourth gate,

and wherein the level processing part comprises:

fifth, sixth, seventh and eighth gates,

a first level register for temporarily storing an input level,

a second level register for receiving the output of the first level register through the fifth gate,

a first comparator for comparing the output of the first level register with the level of the second level register and supplying the larger level to the second level register through the sixth gate,

a third level register for receiving an initial set signal through the seventh gate,

a second comparator for comparing the output of the second level register with the output of the third level register and supplying the smaller level to the third level register through the eighth gate,

a third comparator for comparing the output of the third level register with the output of a branch point level stored in the memory circuit and generating an output signal representing the smaller level plus one

whereby the output of the third flip-flop of the logical processing part and the output of the third comparator of the level processing part are stored in the memory circuit.