Patent Application
20070008040
This application claims the benefit of the priority date of German application DE 10 2005 030 356.0, filed on Jun. 29, 2005, the contents of which are herein incorporated by reference in their entirety.
The invention relates to a digital phase locked loop, to a method for controlling a digital phase locked loop, and to a method for generating an oscillator signal.
Increasing miniaturization in the field of mobile radio, in particular in mobile communication devices, is resulting in the development of radiofrequency assemblies with a very high integration density. Many of the radiofrequency assemblies required have, in the meantime, been produced in the form of integrated circuits in semiconductors using different process technologies. In this case, easy portability of the various radiofrequency assemblies to ever finer semiconductor structures is increasingly strived for, a process which is referred to as “shrinking”. A reduction in the space used by the integrated circuits as a result of such porting enables a higher yield during production and a lower power consumption during operation of the integrated circuits.
Typical radiofrequency assemblies which are manufactured in the form of integrated circuits are, inter alia, phase locked loops (PLLs), voltage-controlled or digitally controllable oscillators (VCOs, DCOs) and power amplifier assemblies. Some of these assemblies have already been implemented in a single semiconductor body.
Implementing the assemblies using purely digital circuits is expedient especially from the point of view of easy portability to new manufacturing technologies and the higher integration density required. On the one hand, digital circuits can be easily adapted to new manufacturing technologies on account of their signal processing and, on the other hand, can be calibrated in a simpler manner in order to compensate for manufacturing tolerances. In addition, in contrast to component groups for analog signal processing, porting purely digital circuits to new or more finely patterned semiconductors does not require any complex adaptation to the new process technology.
In this respect, stabilizing a so-called digitally controlled oscillator in a completely digital manner using a digital phase locked loop has recently proven to be suitable. The term “digital phase locked loop” is understood below as meaning a phase locked loop in which the control signal which is used to set the digitally controlled oscillator is generated using digital signal processing. In the case of conventional digital phase locked loops, a so-called digital phase detector can be used to stabilize the digitally controllable oscillator.
In this case, the digital phase detector digitizes the difference between the phase of a reference signal and the phase of the feedback oscillator signal. In the case of the feedback oscillator signal being at a frequency that is not an integer multiple of the reference frequency, the resultant phase error signal forms a beat and is detected by a plurality of quantization stages in the digital phase detector. As a result, good control and thus good stabilization of the oscillator can be achieved.
However, in the case of frequency synthesis in which the frequency of the feedback oscillator signal corresponds to an integer multiple of the frequency of the reference signal, the error signal is essentially constant and there is no beat. As a result, the phase error signal is processed using only a single quantization stage in the digital phase detector. Under unfavorable circumstances, this may result in a linearity problem and may impair the stability behavior of the control loop.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
In one embodiment of the invention, a digital phase locked loop comprises a digital phase detector having a feedback input, a reference input and an actuating output. The digital phase detector is configured to compare the phases of signals that are applied to the input and supply an actuating signal that is derived from the phase difference to the actuating output. A digital filter is coupled to the actuating output of the digital phase detector. The actuating input of an oscillator that can be tuned to discrete values is connected to an output of the digital filter. The oscillator is configured to supply a radiofrequency signal whose frequency depends on an actuating word that is supplied to the actuating input. The digital phase locked loop also comprises a feedback path having a frequency divider which has an actuating input for setting its divider ratio. The input of the frequency divider is connected to the output of the oscillator, and the output of the frequency divider is connected to the feedback input of the digital phase detector. Provision is also made of a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word comprising the data word to the actuating input of the frequency divider.
According to one embodiment of the invention, the data word that is constantly supplied over a particular period of time is configured so that the frequency setting word generated by the sigma-delta modulator is not constant during this period of time but rather changes between at least two different values. The data word is therefore configured so that the sigma-delta modulator always generates jitter in the frequency setting word during operation, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time. In other words, in one embodiment the data word which is supplied to the sigma-delta modulator is configured in such a manner that precisely defined jitter is introduced into the frequency setting word. A frequency change in the signal that is applied to the feedback input of the phase detector is thus also generated.
The precisely defined jitter or additional jitter within the frequency setting word prevents a signal which is applied to the feedback input of the phase detector from being temporally constant over a relatively long period of time and the phase detector thus no longer generates a beat in the case of an integer multiple of the frequency of the reference signal. In other words, as a result of the invention, the phase detector generates an error signal which is not constant over time and is thus processed using a plurality of quantization stages in the phase detector.
The result is that a digital phase locked loop in accordance with the invention has sufficient stability even in the case of output frequencies that correspond to an integer multiple of a reference frequency.
In order to control a digital phase detector, a frequency setting word is thus supplied to a frequency divider in a feedback path of the digital phase locked loop, the setting word changing over between at least two values. This prevents the feedback signal being at a frequency that is constant over a relatively long period of time.
The invention will be explained in more detail below using a plurality of exemplary embodiments and with reference to the figures. Functionally similar and operatively similar components bear the same reference symbols.
In the figures:
The digital phase detector 1 has a reference input 11 and a feedback input 12. The output 13 of the digital phase detector 1 is connected to an input 21 of the digital filter 2. The output 22 of the digital filter 2 is connected to the actuating input 31 of the controllable oscillator 3. The output signal from the controllable oscillator 3 at the output 32 of the latter is, on the one hand, supplied to the output 7 of the digital phase locked loop and, on the other hand, is applied to the input 41 of a frequency divider 4 in a feedback path of the control loop.
The frequency divider 4 is, in one example, in the form of a multimodulus divider and comprises a control input 42 for setting a divider factor Ni. The frequency divider 4 uses the oscillator signal which is supplied to the input and is at a first frequency f1 to generate a frequency-divided output signal at a second frequency f2. The ratio between the input frequency f1 and the output frequency f2 is set using the divider factor which is supplied to the control input 42. The frequency f2 of the divided output signal results from the ratio between the frequency f1 of the supplied oscillator signal and the divider factor Ni. The signal DIV (whose frequency has been divided in this manner) at the output 43 of the frequency divider circuit 4 is supplied to the feedback input 12 of the digital phase detector.
In comparison with a purely analog implementation of a control loop or a mixed analog/digital implementation, a phase difference between the reference signal at the reference input 11 and the feedback signal at the feedback input 12 of the phase detector must be converted, with sufficient accuracy, into a digital control word in the digital phase locked loop illustrated.
In one embodiment of the invention, the phase detector of the digital phase locked loop has a plurality of inverters which are connected in series. A first inverter is connected to the feedback input of the digital phase detector. Provision is also made of a plurality of flip-flop circuits which are connected in series and the clock inputs of which are coupled to the reference input of the digital phase detector.
In one aspect of this embodiment, a data input of each of the series-connected flip-flop circuits is connected to a respective inverter output of the multiplicity of series-connected inverters.
In one embodiment of the invention, a decoder circuit is provided in the digital phase detector, wherein the decoder circuit is configured to supply an actuating pulse to the actuating output of the digital phase detector. In this case, the actuating pulse is configured from a delay between the occurrence of a clock edge of a signal at the feedback input of the digital phase detector and the occurrence of a clock edge of a signal at the reference input of the digital phase detector.
The digital control loop also comprises a number of flip-flop circuits F1, F2, F3, F4 to Fm. A clock signal input C1 of each of the flip-flop circuits F1, F2, F3 to Fm is connected to the reference input 11 configured to receive the reference signal REF. In this embodiment, the reference signal REF is used as a clock signal to drive the individual flip-flop circuits. The data input 1D of each flip-flop is also connected to the output of a corresponding inverter circuit of the inverters I1, I2 to Im. The data input 1D of the first flip-flop F1 is thus connected to the data output of the first inverter I1. In a corresponding manner, the first data input 1D of the second flip-flop F2 is coupled to the output of the second inverter, the data input 1D of the third flip-flop F3 is coupled to the output of the third inverter I3, etc.
A decoder circuit 15 is additionally provided in the digital phase detector. The inputs 150, 151, 152 to 15m of the decoder circuit are connected, on the input side, to data outputs of the flip-flop circuits F1, F2, F3 to Fm. However, provision is made in this case for the inverted output
During operation, the phase detector measures the fractional component of a delay between the reference signal at the reference input 11 and the next rising edge of the feedback clock signal at the input 12. The minimum resolution which can be achieved in this case corresponds to a delay of an individual inverter of the inverters I1, I2 to Im in the chain. The clock signal at the input 12 is passed through the individual inverters in the chain. The resultant delay is then sampled with the clock signal and supplied in the form of a thermometer code. This thermometer code is applied to the inputs 150, 151 to 15m of the decoder circuit, is converted into an actuating signal by the latter and is supplied to the output 13.
The phase detector thus generates a digitally coded word or a binary discrete-time output signal as the phase error signal. In this case, the phase error signal sweeps over a plurality of quantization stages in the phase detector and a step-shaped dependence of the phase error signal on the phase error thus results.
The transmission response of the digital loop filter is determined using the individual coefficients and the quotients formed from the latter. As a result, the bandwidth of the digital loop filter may be changed on the basis of the coefficients, for example.
The input 21 of the loop filter 2 is connected to the first multiplier 23a, the output of which for its part is connected to the output 22 of the loop filter via a first summation unit 25a. Two further signal paths having the multipliers 23b, 24a and the summation unit 25b and having the multipliers 23c, 24b and the summation unit 25c are provided parallel to this signal path. In this case, the input of the multiplier 23b is connected to the input 21 of the filter 2 via a first delay element 26a and the multiplier 24a is connected to the output 22 of the filter 2 via a delay element 27a. The input of the multiplier 23c leads to the input of the multiplier 23b via an upstream delay element 26b. The output of the summation unit 25c whose inputs are connected to the outputs of the multipliers 23c and 24b is connected to the summation unit 25b. The output signals from the multipliers 23b, 24a are in turn supplied to said summation unit 25b which supplies them as a sum to the element 25a of the first path in the digital filter.
In another embodiment, the sigma-delta modulator comprises a cascaded sigma-delta converter having a data input for supplying the first component. The sigma-delta converter also contains a data output which is connected to a first input of a summing element. The second component of the data word is supplied to a second input of the summing element. The output of the summing element forms the actuating output of the sigma-delta modulator.
In this example, a first data word N0 which represents an integer component is supplied to the subinput 51a of the modulator 5a. A second subinput 51b is used to supply a fractional component K of the frequency word. In addition, the sigma-delta modulator 5 has a clock signal input 51c for supplying a clock signal clk. The subinput 51b is connected to the first modulator stage of the MASH modulator 5a.
Specifically, the subinput 51b is connected to a first accumulator 52a. The output of the accumulator 52a is in turn coupled to a first input of a second accumulator 52b whose output is connected to the third modulator stage of the MASH modulator 5a. The output u+v of the first accumulator 52a is also fed back to its second input v via a delay element 53a. In a corresponding manner, identically configured feedback is also provided in the second stage in the second summation unit 52b and in the third stage in the third summation unit 52c.
The accumulators 52a to 52c of the individual modulator stages of the MASH modulator 5a each have an overflow output which is connected to an input of a respective summation unit 55a and 55b in a feedback path. In this case, the overflow signal c2 from the second accumulator 52b is supplied, together with the overflow signal c3 from the third accumulator 52c, to the summation unit 55b. At the same time, the overflow signal c3 is supplied as a negative value to the summation unit 55b via a delay element 56b.
The output of the summation unit 55b is connected to an input of the first summation unit 55a. The latter adds the overflow signal c1 from the summation unit 52a to the result supplied by the summation unit 55b. In a corresponding manner, provision is also made here again of a delay element 56a whose input is connected to the output of the summation unit 55b and whose output is connected to the summation unit 55a. The result Nmod,i from the summation unit 55a, in which the errors have been reduced, is added to the integer component N0 and is used as a channel word Ni for setting the frequency divider 4.
During operation, the MASH modulator 5a illustrated introduces precisely defined jitter into the digital phase locked loop. The latter prevents an average divider factor that would divide the frequency of the oscillator signal in such a manner that the phase detector 1 is supplied with a frequency-divided signal which corresponds to a multiple of the reference signal. This excludes frequency division in the frequency divider, which divides the frequency of the feedback oscillator signal in such a manner that the frequency of the divided signal corresponds to a multiple of the reference frequency or is the same as the reference frequency.
In one embodiment of the invention, the data word supplied comprises a first component and a second component. In this case, the first component has a bit length having a number of bits. A last bit of the number of bits contains the value 1. The first component thus comprises a partial data word which contains the value 1 in its least significant bit. Configuring and supplying the second component to the sigma-delta modulator 5 thus generates, during operation of the digital phase locked loop, a frequency setting word which, on account of the special configuration of the first component, switches back and forth between at least two values. In this case, the changeover frequency between these two values is dependent on the bit length of the first component supplied.
The fractional component K of the channel word D itself has a bit width n. A channel word K[n] having a width of 8 bits (n=0, . . . , 7) can assume 256 different values. In order to ensure that the phase detector has sufficient accuracy for determining the phase error, the fractional component K of the channel word always has the value 1 for the least significant bit. Therefore: K[0]=1. This stipulation ensures that the MASH modulator 5a always generates an output signal Nmod,i which is different from zero.
Even in the case of a purely integer divider factor, the MASH modulator 5a adds the signal Nmod,i which is different from zero to the integer component N0. As a result, the divider factor Ni changes periodically, as a result of which the frequency of the feedback signal which is applied to the input 12 of the phase detector 1 is likewise changed. This results in a temporally changing value of the phase difference between the phase of the reference signal and the feedback signal. Since a plurality of quantization stages within the phase detector 1 detect this beat, a stable control signal can thus be generated again.
The sigma-delta modulator applies jitter to the phase error, which jitter should generally be greater than a quantization stage of the phase detector. This results, on average over time, in smoothing of the transfer function of the digital phase detector.
The signal output of the first frequency divider stage 441 is connected to the signal input of the second frequency divider stage 442 whose signal output is connected to the signal input of the third frequency divider stage 443 etc. The output of the last frequency divider stage 445 is marked with the reference symbol FDiv4b. The signal outputs are also connected to the taps O0 to O4. The frequency-divided signal may be tapped off at said taps and routed out of the frequency divider circuit.
The output of a respective logic AND gate 447, 448, 449, 410 and 411 is also coupled to each changeover input MOD of the frequency divider stages 441 to 445 for supplying a changeover signal. The AND gates 447 to 411 each have two inputs. The first inputs of the AND gates are respectively connected to one of the connections C0 to C4 for connection to a respective control output of a decoder circuit which is not shown in any more detail and, for its part, is supplied with the frequency word Ni from the MASH modulator 5a. The respective second inputs of the AND gates 447 to 410 are respectively connected to an output of further logic AND gates 412, 413, 414 and 415. The second input of the AND gate 411 is connected to the output of an inverter 416 whose input is connected to the signal output FDiv4b of the frequency divider 445 at the output end.
The AND gates 412 to 415 also each have two inputs. The respective first input of the AND gates 412 to 415 is in the form of an inverting input and is respectively connected to the output of the associated frequency divider 441 to 444. The second input of the AND gates 412 to 415 is respectively connected to the output of the AND gate 413 to 415 which is associated with the downstream frequency divider stage 442 to 445 and, in the case of the gate 415, to the output of the inverter 416. The outputs of the AND gates 412 to 415 and the output of the inverter 416 form a respective tap node for tapping off an output signal from the frequency-dividing circuit arrangement, which tap nodes are denoted using FDiv0, FDiv1 to FDiv4a in the present case.
The signal output FDiv0 is used in the present case as the output of the frequency divider circuit 4, at which a signal whose frequency has been divided down with respect to the input signal frequency f1 can be discharged. This makes it possible for the divider circuit to precisely indicate the delay between the nth input edge and the divider output edge triggered thereby. The use of the 1/2/3 divider stages 444, 445 allows the lower limit of the adjustable divider range to be extended. It goes without saying that the frequency divider illustrated may be extended by additional divider stages, with the result that the divider range can be extended. The frequency channel word which has been conditioned and supplied by the MASH modulator 5a is in turn applied to the control connections C0 to C4.
In a symmetrical manner, a respective first connection of the second pair of transistors EV2 is connected to a current source IB and to the supply potential VDD so as to form a common node. The control connections of the two transistors of the second damping reduction amplifier EV2 are likewise connected to the second connection of the respective other transistor so as to form a cross-coupling. Output taps 32 are additionally provided in the resonant circuit, at which the output signal from the digitally adjustable oscillator 3 can be tapped off.
During operation, the digital setting signal is supplied to the control input 31. Said setting signal switches some varactors of the frequency-determining array AV into the resonant circuit, with the result that the output frequency of the entire oscillator circuit is changed.
Introducing precisely defined jitter thus avoids a stability problem in the present digital phase locked loop on account of the phase detector being controlled using only one quantization stage. In this case, precisely defined jitter is introduced by supplying a frequency word to a sigma-delta modulator which uses it to generate the frequency setting word Ni for setting the divider ratio in the divider circuit 4. The frequency word K supplied represents a fractional component of the channel setting word. The embodiment illustrated enables simple implementation, there being no need for any additional compensation for the loop filter parameters of the loop filter 2, for example. Very high temporal resolution is simultaneously achieved using the phase detector.
While the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE102005030356.0 | Jun 2005 | DE | national |
