TECHNICAL FIELD
This disclosure relates to phase locked loops (PLLs).
BACKGROUND
Rapid advances in electronics and communication technologies, driven by immense customer demand, have resulted in the widespread adoption of an extensive variety of electronic devices. These devices often rely for proper operation on sophisticated frequency synthesizers, clock recovery circuits, jitter and noise reduction circuits and other types of circuits that are sometimes implemented with phase locked loops (PLLs). Improvements in PLLs will further enhance the performance of electronic devices.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an example of a PLL.
FIG. 2 is an example of a hybrid 2nd-order delta sigma phase/frequency detector.
FIG. 3 is an example of a normalized discrete-time delta sigma detector model.
FIG. 4 shows an example of a fine resolution encoder.
FIG. 5 is an example of a digital loop filter and hybrid digital (HD) PLL dynamic control.
FIG. 6 shows selected WLAN 802.11ac channels between 4915 and 5825 MHz.
FIG. 7 shows example phase noise profiles.
FIG. 8 shows coarse resolution HDPLL phase noise performance.
FIG. 9 shows fine resolution HDPLL phase noise performance.
FIG. 10 shows HDPLL root-mean-square (RMS) phase error performance.
FIG. 11 shows an example of dynamic element matching used in connection with a Digital to Analog Converter (DAC) in a detector such as that of FIG. 2.
FIG. 12 shows another example PLL.
DETAILED DESCRIPTION
FIG. 1 shows an example of a PLL 100. The PLL 100 includes independent frequency-locking and phase-locking operational modes. In addition, the PLL 100 includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (DS) phase/frequency detector 102 (“detector 102”). The detector 102 may be implemented, for example, using a continuous-time 1st-order DS Analog to Digital Converter (ADC) 104, enhanced to 2nd-order via, e.g., closed loop frequency detection.
The PLL 100 and its component parts may be implemented in other ways and may vary in performance characteristics from implementation to implementation. For example, FIG. 12 shows another example PLL 1200. In the example of FIG. 12, a hybrid DS phase/frequency detector 1202 is present, and includes a DS ADC 1204 which is not necessarily 1st-order. As another example, in some implementations, an ADC with Dynamic Element Matching (DEM) may be used, while in other implementations, the DEM is omitted.
The PLL 100 includes a fine resolution (FineRes) encoder 106 for encoding the DS ADC output. The fine resolution encoding facilitates true multi-bit phase/frequency error digitization with drastically reduced DS quantization noise. A phase/frequency detector (PFD) charge pump (CP) 108 drives the ADC 104, and a multi-modulus divider (MMD) 110 is present in the feedback path from the digital loop filter.
The PLL 100 also includes coarse and fine resolution detection modes that facilitate fast acquisition and spur-free tracking operation. A fully digital loop filter 112 may be implemented in the PLL 100 and may control the digitally control oscillator (DCO) 114. Note that the PLL 100 has a bandwidth determined by the loop filter coefficients independent of the DS phase/frequency detector parameters (e.g., CP current Icp and the 1st-order DS ADC integrating capacitor Cint).
The PLL 100 operates on the differential phase/frequency error of its output clock signal Fout with respect to the input reference clock signal 122, Fref. The output frequency of the PLL output clock 124, Fout, reflects the targeted channel frequency upon phase/frequency lock. The detector 102 provides a digital estimate of the PLL output frequency the PLL 100 may compare to a digital word (e.g., a channel indicator 116) that specifies the targeted channel frequency for the PLL 100 to produce. The digital frequency error information (Dfe) 118 is accumulated (e.g., integrated) to provide the digital phase error information (Dphie) 120. The PLL 100 controls the phase/frequency of the DCO 114 responsive to the digital phase error information, e.g., to try to eliminate the error. A phase lock enable signal 126 may be provided to selectively enable or disable the operation of the accumulation and filter operations of the PLL 100.
Note that the loop filter configuration is independent of the fine resolution encoder 106. Without the fine resolution encoder 106, the loop filter may instead be characterized by a low bandwidth and high rejection (that may result in less stable output) so that distortion due to the coarse resolution quantization is adequately filtered. The fine resolution encoder 106 thus allows for more flexible PLL dynamic control.
FIG. 2 is an example of a hybrid 2nd-order delta sigma phase/frequency detector (“detector”) 200 that may be used in the PLL 100, and also shows in more detail the ADC 104. The voltage developed across Cint reflects the phase error between the reference clock (Fref) and the divided local oscillator (LO) clock (Fmmd) on the divider output 210. The negative feedback loop around Cint dynamically conditions charge accumulation and in the absence of overloading the detector self-calibrates Direct Current (DC) offsets. The closed loop noise shaping functionality of the detector 200 allows for low Icp consumption and therefore relaxed CP phase noise performance. These advantages directly translate to small Cint values, e.g., a few pico Farad (pF), with Cint a function of Icp and Fref, e.g., Cint˜f(Icp/Fref). In some analog CP-PLLs, the loop filter shunt capacitance is required to be large (on the order of hundreds of pF). This is because the loop bandwidth is a small fraction of Fref for adequate suppression of high-frequency DS quantization noise. However, in the PLL 100, the purpose of Cint is for detector gain normalization, and therefore is not subject to the same value requirements as in analog CP-PLLs.
The flash ADC 204 and current-mode DAC 206 of the ADC 104 is digitally reconfigurable to support single-bit or multi-bit resolution via dynamic control of the number of active quantization levels, allowing for fast frequency acquisition and spur-free tracking operation. In that regard, the PLL 100 may include a resolution control input 208 that specifies, e.g., the number of quantization levels that the ADC 104 will generate. As a specific example, the resolution control input 208 may be provided to both the flash ADC 204 and the current-mode DAC 206 to configure them for the number of quantization levels desired. A controller may use the resolution control input 208 to place the PLL 100 into single-bit or three level quantization mode for coarse resolution operation of the PLL 100, while the controller may cause multi-bit quantization for fine resolution operation of the PLL 100. The controller may switch to fine resolution operation on an application specific basis, and as one example the switch to fine resolution may depend upon the time for the frequency error to settle to within a predefined margin. To the extent that there are mismatches in the flash ADC 204 and current-mode DAC 206 characteristics, those mismatches may be randomized via the closed-loop noise shaping functionality of the detector 200, thereby alleviating any need for dynamic element matching (DEM). However, as noted below with respect to FIG. 11, DEM may also be included.
FIG. 3 is an example of a normalized discrete-time delta sigma detector model 300. The MMD 110 divides FLO by a sequence of integer factors of the form:
N
int+{ . . . ,−1,0,1, . . . }
and thereby achieves a long-term average fractional N value, where:
N=N
int
+N
frac
=F
LO
/F
ref and Nfracε[0,1) or [−½,½).
The mean value of the detector output Bout 302 is preferably Nfrac in order to minimize the frequency error between Fref and Fmmd=FLO/(Nint+Nfrac). The fractional division control results in Nfrac cycle-to-cycle period variations of Fmmd, which entail a Nfrac LO cycles normalized differential frequency Delta fin input 304 to the DS detector.
Delta fin (Nfrac) 304 and the induced 1st-order DS ADC quantization noise Qn 306 are transferred to the detector output 302 as:
B
out
=N
frac+(1−z1)2Qn
Note that the induced quantization noise undergoes 2nd-order noise shaping.
In FIG. 3, the z-domain transfer function 308 represents the sampled physical integration of frequency error reflected on the pulse-width modulated CP output current (hence ←CP), in response to the previous (equation 310) output sample of the DS ADC output fed to the MMD control (hence ←MMD), and the equation 312 represents first-order noise shaping functionality of the DS ADC.
FIG. 4 shows an example of a fine resolution encoder circuit 400 that may be used in the PLL 100. For integer only MMD control a suitable coarse quantization step for the 1st-order DS ADC is D=1 and a mid-tread three-level quantizer {−1,0,1} may suffice to produce the Nfrac values. Additional levels may not improve performance because it may be difficult or impossible to further reduce the induced quantization noise power (which is on the order of Delta2/12 in this implementation example).
FIG. 4 also illustrates the difference between coarse resolution encoding 406 and fine resolution encoding 408. The ADC resolution can be increased to support multi-bit (fine) resolution (i.e., Delta (D)<1) when integer only MMD control is maintained. The PLL 100 may achieve increased ADC resolution with concurrent re-encoding of the ADC output. The re-encoding may be, for example, to integer only valued control through dither Digital Signal Processing (DSP) operations, such as a digital Multi-Stage Noise Shaping (MASH) (e.g., a MASH-III) DS modulator implemented with the dither DSP 402. Preferably, the modulator does not degrade the 2nd-order DS noise shaping characteristics of the detector 102. The detector capability to dynamically self-calibrate DC offsets allows the 1st-order DS ADC quantizer input voltage to be maintained at a predetermined DC level after proper digital output offsetting. The digital offset input 404 provides better control for preventing quantizer overloading and maintaining uniform ADC operation across all channels (i.e., all Nfrac values).
FIG. 5 is an example of a digital loop filter 500 for the dynamic control of the hybrid digital (HD) PLL. The digital loop filter 500 is one possible implementation of the loop filter 112, with reference again to FIG. 1. The digital loop filter 500 may include proportional-plus-Integral (P+I) control for type-II operation, e.g., so that the phase error between the output clock signal and the reference clock signal is approximately zero, combined with cascaded single-pole IIR filters 502 that facilitate achieving high rejection of the DS detector quantization noise. The HDPLL loop gain may be normalized via the gain normalization (Gnorm) factor 508. The gain normalization factor 508 may decouple the HDPLL dynamic operation from process, voltage, temperature (PVT) dependent parameters such as the DCO gain. The PLL 100 may implement filter coefficients (e.g., 504, 506) that are powers of two, and therefore facilitate digital hardware implementation, e.g., as digital bit-shifting operations. None of the factors, including the gain normalization factor Gnorm 508, need to be a power of two, however. The digitally intensive HDPLL dynamic control facilitates on-demand bandwidth control, sometimes referred to as gear shifting. The dynamic control also effectively addresses parasitic spurious noise, e.g., injected via the power supplies or coupling between the DCO and the crystal (Xtal) reference.
FIG. 6 shows examples of channel frequencies 600 in MHz that the PLL 100 may generate. One specific example is 4915 MHz (4.915 GHz). Note that the PLL 100 may generate any desired output frequencies, including those shown in FIG. 6. The output frequencies may vary widely according the particular system (e.g., a 3G or 4G cellular phone, or a Bluetooth transceiver) in which the PLL 100 is present.
FIG. 7 shows the phase noise profiles 700 for the PLL 100. The dataset is for 5.825 GHz. The dataset shows the phase noise profile for the DCO 114, the charge pump 108 and MMD 110, compared to a reference.
Fine resolution encoding may generally refer to a quantization step D less than 1. The PLL 100 uses quantization steps less than one (D<1) together with the fine resolution encoder 106 to interface the fractional valued DS ADC output with the MMD 110. The quantization step may be set according to a targeted PLL performance. Accordingly, even low-level fractional quantization may be sufficient for a target performance level, and finer grained fractional quantization may be implemented to reach higher target performance levels.
FIG. 8 shows 3-level {−1, 0, 1} coarse resolution HDPLL phase noise performance 800 for a 5 GHz spectrum. Note the DS detector output variance 802, and the HDPLL output variance 804. FIG. 9 shows 16-level fine resolution HDPLL phase noise performance 900, also for the 5 GHz spectrum. Note the significantly reduced and spurious tones-free DS detector output variance 902, and the HDPLL output variance 904.
FIG. 10 shows HDPLL root-mean-square (RMS) phase error performance 1000. The phase error performance 1002 for coarse resolution operation mode is shown. Also shown is the phase error performance 1004 for fine resolution operation mode. Fine resolution mode exhibits significantly reduced RMS phase error across all of the channels of interest.
FIG. 11 shows an example of a detector 1100 that uses optional dynamic element matching in connection with a Digital to Analog Converter (DAC). In particular, the dynamic element matching circuitry 1102 is associated with (e.g., incorporated into) the current-mode DAC 206. In the DAC 206 a series of unit current sources may generate the analog output. However, due to the normal variations in the fabrication processes, each unit current source is not exactly the same, and each may vary slightly from each other current source. The dynamic element matching circuitry 1102 may be present to help eliminate the mismatches as a source of error. The dynamic element matching circuitry 1102 may implement, for example, the randomized use of the unit current sources in order to make the error resulting from their mismatches appear to be pseudorandom noise (e.g., white noise) that is uncorrelated with the input.
Various implementations of the PLL 100 have been specifically described. However, many other implementations are also possible.
Patent Application
20140354335
