Patent Application
20240396192
The present invention relates to a digital phase shifter.
Priority is claimed on Japanese Patent Application No. 2022-024214, filed Feb. 18, 2022, and Japanese Patent Application No. 2022-147145, filed Sep. 15, 2022, the contents of which are incorporated herein by reference.
In the following Non-Patent Document 1, a digitally controlled phase shift circuit (a digital phase shift circuit) targeting microwaves, quasi-millimeter waves, or millimeter waves is disclosed. As shown in
This digital phase shift circuit switches the operation mode between a low-delay mode and a high-delay mode by switching a return current flowing through the two inner lines or the two outer lines due to the transmission of signal waves in the signal line in accordance with the opening/closing of the two NMOS switches. That is, in the digital phase shift circuit, the operation mode becomes the low-delay mode when the return current flows through the two inner lines and the operation mode becomes the high-delay mode when the return current flows through the two outer lines.
The above-described digital phase shift circuit supplies a signal wave with a predetermined phase shift amount to a circuit (a subsequent-stage circuit) connected to a subsequent stage thereof. In the above-described digital phase shift circuit, because an input reflection coefficient and an output reflection coefficient are different when the same real load is applied to an input and an output, the fluctuation of the phase shift amount may increase due to impedance mismatch. Also, when a circuit (an adjacent circuit) having a real load is connected to an output stage, because the digital phase shift circuit has complex impedance, the adjacent circuit or the entire phase shift circuit including the adjacent circuit may not be able to exhibit the desired performance.
The present invention has been made in view of the above-described circumstances and an objective of the present invention is to provide a digital phase shifter capable of limiting fluctuations in a phase shift amount when a specific real load larger than a real load connected to an input stage is connected to an output stage.
A digital phase shifter of a first aspect of the present invention for achieving the above-described objective includes: a digital phase shift circuit including at least a signal line, two inner lines provided separately at predetermined distances on both sides of the signal line, two outer lines provided outside of the two inner lines, a first ground conductor connected to one end of each of the two inner lines and the two outer lines, a second ground conductor connected to the other end of each of the two outer lines, and two electronic switches, one thereof being provided between the other end of one of the two inner lines and the second ground conductor, the other thereof being provided between the other end of the other of the two inner lines and the second ground conductor, the first ground conductor being configured of a plurality of conductive layers; and an output circuit including an output signal line connected to the signal line and configured to increase output impedance as compared with that of an input matching load connected to an input stage of the digital phase shift circuit.
A second aspect of the present invention is that in the above-described first aspect, the output signal line and an output ground layer obtained by extending one conductive layer of the first ground conductor configured of the plurality of conductive layers form a microstrip line.
A third aspect of the present invention is that in the above-described first or second aspect, a line width of the output signal line is narrower than a line width of the signal line.
A fourth aspect of the present invention is that in any one of the above-described first to third aspects, the output circuit includes ground lines for the signal line provided on both sides of the output signal line.
A fifth aspect of the present invention is that in any one of the above-described first to fourth aspects, each of the distances is set to be less than 10 μm.
A sixth aspect of the present invention is that in any one of the above-described first to fifth aspects, the digital phase shift circuit includes a capacitor having one end connected to the signal line and the other end connected to at least one of the first ground conductor and the second ground conductor.
A seventh aspect of the present invention is that the digital phase shifter of the above-described sixth aspect includes an electronic switch for the capacitor between a lower electrode of the capacitor and at least one of the first ground conductor and the second ground conductor.
An eighth aspect of the present invention is that in any one of the above-described first to seventh aspects, the output circuit includes a short stub connected to the output signal line.
A ninth aspect of the present invention is that in the above-described eighth aspect, the output circuit includes a ground line for the stub provided to surround a signal line of the short stub.
A tenth aspect of the present invention is that the digital phase shifter of the above-described ninth aspect includes a third ground conductor connecting one end of one of the inner lines and one end of one of the outer lines, the one of the inner lines and the one of the outer lines being located on a side where the short stub extends, and the third ground conductor forming a part of the ground line for the stub.
An eleventh aspect of the present invention is that the digital phase shifter of the above-described tenth aspect includes a ground layer provided to cover upper parts of the short stub and the third ground conductor.
A twelfth aspect of the present invention is that in any one of the above-described eighth to eleventh aspects, digital phase shift circuits including the digital phase shift circuit are connected in cascade in a multirow state, the output circuit is provided in a subsequent stage of the digital phase shift circuit located in a last stage, and the short stub is arranged between rows of the digital phase shift circuits.
A thirteenth aspect of the present invention is that in any one of the above-described second to twelfth aspects, a notch is formed in at least a part of the output ground layer below the output signal line.
According to the present invention, it is possible to provide a digital phase shifter capable of limiting fluctuations in a phase shift amount when a specific real load larger than an input matching load connected to an input stage is connected to an output stage.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described. A digital phase shifter A1 according to the first embodiment is a high-frequency circuit that inputs high-frequency signals such as microwaves, quasi-millimeter waves, millimeter waves or the like and externally outputs a plurality of high-frequency signals that are phase-shifted by a predetermined phase shift amount.
As shown in
As shown in the drawing, the digital phase shifter A1 is made by linearly connecting the digital phase shift circuits Y1 to Y8 of eight stages (a plurality of stages) and the output circuit Z in cascade. In such a digital phase shifter A1, a high-frequency signal input from the other end (a left end) of the first digital phase shift circuit Y1 is sequentially phase-shifted by a predetermined phase shift amount by each of the digital phase shift circuits Y1 to Y8 and the phase-shifted high-frequency signal is externally output from one end (a right end) of the output circuit Z.
The eight (a plurality of) digital phase shift circuits Y1 to Y8 are unitary phase shift units constituting the digital phase shifter A1 and are linearly connected in cascade in the order of first digital phase shift circuit Y1→second digital phase shift circuit Y2→ . . . →eighth digital phase shift circuit Y8 as shown in the drawing. The digital phase shift circuits Y1 to Y8 have functions substantially similar to those of the digitally controlled phase shift circuit disclosed in Non-Patent Document 1.
That is, the digital phase shift circuits Y1 to Y8 are delay circuits, each of which delays the input high-frequency signal by a preset phase shift amount and outputs the delayed high-frequency signal to the adjacent digital phase shift circuit or the output circuit Z.
As indicated by representative reference sign Y in
The signal line 1 is a linear strip-shaped conductor extending in a predetermined direction as shown in
This signal line 1 electrically has inductance L1 as a distributed circuit constant. The inductance L1 is parasitic inductance having a magnitude corresponding to a shape of the signal line 1, such as the length of the signal line 1, and the like. Also, the signal line 1 has capacitance C1 as a distributed circuit constant electrically. The capacitance C1 is parasitic capacitance between the signal line and the inner lines and between the signal line and the outer lines or between silicon substrates.
The two inner lines 2a and 2b are linear strip-shaped conductors provided on both sides of the signal line 1. Between the two inner lines 2a and 2b, the first inner line 2a is arranged at an interval of a predetermined distance M on one side of the signal line 1 (the right side in
The second inner line 2b is arranged at an interval of a predetermined distance M on the other side of the signal line 1 (the left side in
Here, the distance M between the signal line 1 and the first inner line 2a and the distance M between the signal line 1 and the second inner line 2b are set to a manufacturing limit or to be close to the manufacturing limit. The distance M is, for example, less than 10 μm, more preferably 2 μm or less.
The first outer line 3a is a linear strip-shaped conductor provided outside of the first inner line 2a on the one side of the above-described signal line 1. That is, the first outer line 3a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is provided at a position farther from the signal line 1 than the first inner line 2a on the one side of the signal line 1.
Also, the first outer line 3a is provided parallel to the signal line 1 at an interval of a predetermined distance from the signal line 1 in a right direction in a state in which the first inner line 2a is interposed therebetween as shown in the drawing. That is, the first outer line 3a extends in a direction that is the same as the extension direction of the signal line 1 similarly to the first inner line 2a and the second inner line 2b described above.
The second outer line 3b is a linear strip-shaped conductor provided outside of the second inner line 2b on the other side of the signal line 1, i.e., in a left direction different from that of the first outer line 3a. That is, the second outer line 3b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is provided at a position farther from the signal line 1 than the second inner line 2b on the other side of the signal line 1.
Also, the second outer line 3b is provided parallel to the signal line 1 at an interval of a predetermined distance from the signal line 1 in a state in which the second inner line 2b is interposed therebetween as shown in the drawing. That is, the second outer line 3b extends in a direction that is the same as the extension direction of the signal line 1 similarly to the first inner line 2a, the second inner line 2b, and the first outer line 3a.
The first ground conductor 4a is a linear strip-shaped conductor provided on one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the first ground conductor 4a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length, and is electrically grounded.
Also, the first ground conductor 4a is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b extending in the same direction. That is, the first ground conductor 4a is provided to extend in the left and right directions at the one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Furthermore, the first ground conductor 4a is provided downward at an interval of a predetermined distance from the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, a certain distance is provided in the upward/downward direction between the first ground conductor 4a and an end of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the length of the first ground conductor 4a is set such that one end in the left and right directions (the right end in
The second ground conductor 4b is a linear strip-shaped conductor provided on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the second ground conductor 4b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is electrically grounded.
Also, the second ground conductor 4b is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b extending in the same direction. That is, the second ground conductor 4b is provided extending in the left and right directions on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Further, the second ground conductor 4b is provided downward at an interval of a predetermined distance from the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, a certain distance is provided in the upward/downward direction between the second ground conductor 4b and an end of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the length of the second ground conductor 4b is set such that one end in the left and right directions (the right end in
The capacitor 5 has parallel flat plates in which the upper electrode is connected to the signal line 1 via the seventh connection conductor 6g and the lower electrode is connected to the second ground conductor 4b via the fourth electronic switch 7d. The capacitor 5 has capacitance Ca corresponding to a facing area of the parallel flat plates. That is, the capacitance Ca has a circuit constant provided between the signal line 1 and the second ground conductor 4b. Also, the capacitor 5 may be formed in a comb shape rather than the parallel flat plates.
The first connection conductor 6a is a conductor that electrically and mechanically connects one end of the first inner line 2a and the first ground conductor 4a. That is, the first connection conductor 6a is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the first inner line 2a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a. Also, the first connection conductor 6a connects the first ground conductor 4a formed in a multilayer structure between the first inner line 2a and the first outer line 3a.
The second connection conductor 6b is a conductor that electrically and mechanically connects one end of the second inner line 2b and the first ground conductor 4a. That is, the second connection conductor 6b is a conductor extending in the upward/downward direction similarly to the first connection conductor 6a and has one end (an upper end) connected to the lower surface of the second inner line 2b and the other end (a lower end) connected to the upper surface of the first ground conductor 4a. Also, the second connection conductor 6b connects the first ground conductor 4a formed in a multilayer structure between the second inner line 2b and the second outer line 3b.
The third connection conductor 6c is a conductor that electrically and mechanically connects one end of the first outer line 3a and the first ground conductor 4a. That is, the third connection conductor 6c is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface at one end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a. Also, the third connection conductor 6c connects the first ground conductor 4a formed in a multilayer structure between the first inner line 2a and the first outer line 3a.
The fourth connection conductor 6d is a conductor that electrically and mechanically connects the other end of the first outer line 3a and the second ground conductor 4b. That is, the fourth connection conductor 6d is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface at the other end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.
The fifth connection conductor 6e is a conductor that electrically and mechanically connects one end of the second outer line 3b and the first ground conductor 4a. That is, the fifth connection conductor 6e is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface at one end of the second outer line 3b and the other end (a lower end) connected to the upper surface of the first ground conductor 4a. Also, the fifth connection conductor 6e connects the first ground conductor 4a formed in a multilayer structure between the second inner line 2b and the second outer line 3b.
The sixth connection conductor 6f is a conductor that electrically and mechanically connects the other end of the second outer line 3b and the second ground conductor 4b. That is, the sixth connection conductor 6f is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface at the other end of the second outer line 3b and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.
The seventh connection conductor 6g is a conductor that electrically and mechanically connects one end of the signal line 1 and the upper electrode of the capacitor 5. That is, the seventh connection conductor 6g is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the one end of the signal line 1 and the other end (a lower end) connected to the lower electrode (the upper surface) of the capacitor 5.
The first electronic switch 7a is a transistor that connects the other end of the first inner line 2a to the second ground conductor 4b such that it can be freely opened and closed. The first electronic switch 7a is, for example, a MOS-type FET as shown in the drawing, and has a drain terminal connected to the other end of the first inner line 2a, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
The first electronic switch 7a switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the first electronic switch 7a turns ON/OFF a connection between the other end of the first inner line 2a and the second ground conductor 4b through the switch controller 8.
The second electronic switch 7b is a transistor that connects the other end of the second inner line 2b and the second ground conductor 4b such that it can be freely opened and closed. The second electronic switch 7b is a MOS-type FET similar to the first electronic switch 7a and has a drain terminal connected to the other end of the second inner line 2b, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
The second electronic switch 7b switches a conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the second electronic switch 7b turns ON/OFF a connection between the other end of the second inner line 2b and the second ground conductor 4b through the switch controller 8.
The third electronic switch 7c is a transistor that connects one end of the signal line 1 and the second ground conductor 4b such that it can be freely opened and closed. The third electronic switch 7c is a MOS-type FET similar to the first electronic switch 7a and the second electronic switch 7b described above and has a drain terminal connected to one end of the signal line 1, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
This third electronic switch 7c switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the third electronic switch 7c turns ON/OFF a connection between one end of the signal line 1 and the second ground conductor 4b through the switch controller 8.
The fourth electronic switch 7d is a transistor that connects the lower electrode of the capacitor 5 and the second ground conductor 4b such that it can be freely opened and closed. The fourth electronic switch 7d is a MOS-type FET similar to the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c described above, and has a drain terminal connected to the lower electrode of the capacitor 5, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
The fourth electronic switch 7d switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the fourth electronic switch 7d turns ON/OFF a connection between the lower electrode of the capacitor 5 and the second ground conductor 4b through the switch controller 8. Also, the fourth electronic switch 7d corresponds to the electronic switch for the capacitor in the present invention.
The switch controller 8 is a control circuit that controls the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d described above. The switch controller 8 includes four output ports and individually outputs gate signals from the output ports to the gate terminals of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d. That is, the switch controller 8 controls the ON/OFF operations of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d through the above-described gate signals.
Here, a schematic diagram in which the digital phase shift circuit Y is obliquely viewed such that the mechanical structure of the digital phase shift circuit Y (i.e., the digital phase shift circuits Y1 to Y8) is easily understood is shown in
For example, in the digital phase shift circuit Y (i.e., the digital phase shift circuits Y1 to Y8), the signal line 1, the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b are formed in the first conductive layer, and the first ground conductor 4a and the second ground conductor 4b are formed in the second conductive layer (the lower layer) facing the first conductive layer in a state in which an insulating layer is sandwiched between the first conductive layer and the second conductive layer.
The component of the first conductive layer, the component of the second conductive layer, the capacitor 5, and the first to fourth electronic switches 7a to 7d are connected to each other through vias (through holes). That is, these vias are buried inside of an insulating layer and function as the first connection conductor 6a, the second connection conductor 6b, the third connection conductor 6c, the fourth connection conductor 6d, the fifth connection conductor 6e, the sixth connection conductor 6f, and the seventh connection conductor 6g.
The output circuit Z is a high-frequency circuit adjacent to the right side of the eighth digital phase shift circuit Y8 and receives a high-frequency signal from the eighth digital phase shift circuit Y8 to externally output the high-frequency signal. The output circuit Z is configured to increase output impedance of the digital phase shifter A1 as compared with that of an input matching load connected to an input stage of the digital phase shifter A1.
The output circuit Z includes a single output signal line 9, a short stub 10, and an output ground line 11, as shown in
The output signal line 9 is a linear strip-shaped conductor having a certain width, a certain thickness, and a predetermined length and extending in a predetermined direction. The width of the output signal line 9 is the same as the width of the signal line 1 in the eighth digital phase shift circuit Y8 as an example.
Also, the output signal line 9 has an input end (a left end) connected to an output end (a right end) of the signal line 1 in the eighth digital phase shift circuit Y8. The output signal line 9 transmits a high-frequency signal input from the eighth digital phase shift circuit Y8 to the input end (left end) to externally output the high-frequency signal from the output end (the right end). That is, a signal current of a high-frequency signal flows from the input end (the left end) to the output end (the right end) in the output signal line 9. The output signal line 9 is formed in the first conductive layer similarly to the signal line 1 (see parts (a) and (b) of
The short stub 10 is provided to branch from the output signal line 9 and is a line with a tip as a ground end. That is, the short stub 10 is formed of the first conductive layer, branches from an intermediate portion of the output signal line 9 in a direction perpendicular to an extension direction of the output signal line 9, and has a shape that bends from the intermediate portion thereof in the extension direction of the output signal line 9 as shown in
In the short stub 10, a specification is set to transform the output impedance of the entire digital phase shift circuits Y1 to Y8 connected in cascade represented as a complex number into real impedance. That is, a shape such as the length of the short stub 10 or the like is set to transform the output impedance of the entire digital phase shift circuits Y1 to Y8 connected in cascade into the real impedance.
Also, the stub in the high-frequency circuit is a well-known circuit element. As a general stub, an open stub having an open tip is known in addition to the short stub 10 as in the present embodiment.
The output ground line 11 is a ground line provided to surround both sides of the output signal line 9 and the signal line of the short stub 10 described above and is electrically grounded. As shown in
Among these individual ground lines 11a to 11c and 11e to 11h, the first to third individual ground lines 11a to 11c are ground lines (ground lines for the signal line) formed on the left and right of and below the output signal line 9. Also, the fourth to seventh individual ground lines 11e to 11h are ground lines (ground lines for the stub) that surround the signal line of the short stub 10 from the left and right thereof, above and below.
Among the first to third individual ground lines 11a to 11c, the first individual ground line 11a is a ground line for covering a lower part of the output signal line 9 as shown in part (a) of
The first individual ground line 11a has a function of shielding electromagnetic waves radiated downward from the output signal line 9. Also, the first individual ground line 11a is an output ground layer parallel opposed to the output signal line 9 and having a larger area than the output signal line 9. The first individual ground line 11a and the output signal line 9 have a function of increasing the output impedance of the digital phase shifter A1 as compared with that of the input matching load connected to the input stage of the digital phase shifter A1.
The second individual ground line 11b is a ground line covering the left side of the output signal line 9 as shown in part (a) of
As shown in part (a) of
Also, among the fourth to seventh individual ground lines 11e to 11h, the fourth individual ground line 11e is a ground line covering the lower part of the short stub 10 as shown in part (c) of
The fifth individual ground line 11f is a ground line covering the right side of the short stub 10 as shown in part (c) of
The sixth individual ground line 11g is a ground line covering the left side of the short stub 10 as shown in part (c) of
The seventh individual ground line 11h is a ground line covering the upper part of the short stub 10 as shown in part (c) of
As shown in
Further, for the output circuit Z, the output signal line 9 is connected to the signal line 1 of the eighth digital phase shift circuit Y8 and the output ground line 11 is electrically connected to the first ground conductor 4a of the eighth digital phase shift circuit Y8.
Next, the operation of the digital phase shifter A1 according to the first embodiment will be described in detail.
Each of the digital phase shift circuits Y1 to Y8 in the digital phase shifter A1 can switch the operation mode in accordance with the conductive states of the first electronic switch 7a, the second electronic switch 7b, and the fourth electronic switch 7d.
That is, in the operation mode of each of the digital phase shift circuits Y1 to Y8, there are a low-delay mode in which only the first electronic switch 7a and the second electronic switch 7b are set in the ON state by the switch controller 8 and a high-delay mode in which only the fourth electronic switch 7d is set in the ON state by the switch controller 8 in the same way.
In the low-delay mode, the switch controller 8 sets the first electronic switch 7a and the second electronic switch 7b in the ON state and sets the fourth electronic switch 7d in the OFF state. That is, in the low-delay mode, a first phase difference θL less than a second phase difference OH in the high-delay mode is caused by a first propagation delay time TL until the high-frequency signal propagates from the input end (the other end) of the signal line 1 to the output end (the one end) thereof.
This low-delay mode will be described in more detail. The first inner line 2a is in a state in which the other end thereof is connected to the second ground conductor 4b by setting the first electronic switch 7a in the ON state. That is, the first inner line 2a forms a first current-carrying path along which an electric current can flow between the one end and the other end of the first inner line 2a by connecting the one end of the first inner line 2a to the first ground conductor 4a via the first connection conductor 6a all the time and connecting the other end of the first inner line 2a to the second ground conductor 4b via the first electronic switch 7a.
On the other hand, the second inner line 2b is in a state in which the other end thereof is connected to the second ground conductor 4b by setting the second electronic switch 7b in the ON state. That is, the second inner line 2b forms a second current-carrying path along which an electric current can flow between the one end and the other end of the second inner line 2b by connecting one end of the second inner line 2b to the first ground conductor 4a via the second connection conductor 6b all the time and connecting the other end of the second inner line 2b to the second ground conductor 4b via the second electronic switch 7b.
Also, when a signal current flows from the input end to the output end through the signal line 1 in a state in which both ends of the first inner line 2a and the second inner line 2b are connected, a return current of the signal current from one end to the other end flows through the first inner line 2a and the second inner line 2b due to the propagation.
That is, a first return current flows through the first inner line 2a forming the first current-carrying path in a direction opposite to a current-carrying direction of the signal current in a current-carrying process for the signal current in the signal line 1. Also, a second return current flows through the second inner line 2b forming the second current-carrying path in a direction opposite to a current-carrying direction of the signal current in a current-carrying process for the signal current in the signal line 1, i.e., in a direction that is the same as a direction of the first return current.
Here, both the first return current flowing through the first inner line 2a and the second return current flowing through the second inner line 2b are in a direction opposite to a current-carrying direction of the signal current. Therefore, the first return current and the second return current act to reduce inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first inner line 2a and between the signal line 1 and the second inner line 2b. When a reduced amount of the inductance L1 is ΔLs, the effective inductance Lm of the signal line 1 is (L1-ΔLs).
Also, the signal line 1 has capacitance C1 as parasitic capacitance as described above. In the low-delay mode, because the fourth electronic switch 7d is set in the OFF state, the capacitor 5 is not connected between the signal line 1 and the second ground conductor 4b. That is, the capacitance Ca of the capacitor 5 does not affect the high-frequency signal propagating through the signal line 1. Therefore, the first propagation delay time TL proportional to (Lm×C1)1/2 acts on the high-frequency signal propagating through the signal line 1.
Also, the high-frequency signal at the output end (the other end) of the signal line 1 becomes a signal obtained by delaying a phase of a high-frequency signal at the input end (the one end) of the signal line 1 by a first phase difference θL due to the first propagation delay time TL. That is, in the low-delay mode, the inductance L1 of the signal line 1 is reduced to the inductance Lm by the first return current and the second return current, and therefore the original propagation delay time of the signal line 1 is reduced. As a result, the first phase difference θL smaller than the original phase difference of the signal line 1 is implemented.
Here, in the low-delay mode, the loss of the signal line 1 is intentionally increased by setting the third electronic switch 7c in the ON state. The purpose of the loss imposition is to bring the output amplitude of the high-frequency signal in the low-delay mode close to the output amplitude of the high-frequency signal in the high-delay mode. Also, the third electronic switch 7c is not an essential component and may be deleted.
That is, the loss of the high-frequency signal in the low-delay mode is clearly less than the loss of the high-frequency signal in the high-delay mode. This loss difference causes an amplitude difference of the high-frequency signal output from the digital phase shift circuit Y when the operation mode is switched between the low-delay mode and the high-delay mode. In this situation, in the digital phase shift circuit Y, the above-described amplitude difference is eliminated by setting the third electronic switch 7c in the ON state in the low-delay mode.
On the other hand, in the high-delay mode, the switch controller 8 sets the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c in the OFF state and sets the fourth electronic switch 7d in the ON state. That is, in the high-delay mode, a second phase difference OH larger than the first phase difference θL in the low-delay mode is caused by a second propagation delay time TH until the high-frequency signal propagates from the input end (the one end) of the signal line 1 to the output end (the other end) thereof.
In this high-delay mode, because the first electronic switch 7a and the second electronic switch 7b are set in the OFF state, the first current-carrying path is not formed on the first inner line 2a and the second current-carrying path is not formed on the second inner line 2b. Therefore, the first return current flowing through the first inner line 2a becomes significantly small and the second return current flowing through the second inner line 2b becomes significantly small.
On the other hand, the first outer line 3a has one end connected to the first ground conductor 4a via the third connection conductor 6c and the other end connected to the second ground conductor 4b via the fourth connection conductor 6d. That is, a third current-carrying path along which an electric current can flow between the one end and the other end of the first outer line 3a is formed in advance on the first outer line 3a.
Therefore, in the high-delay mode, a third return current flows from one end of the first outer line 3a to the other end thereof due to the signal current in the signal line 1. This third return current is in a direction opposite to the current-carrying direction of the signal current in the signal line 1. Therefore, the third return current can reduce the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first outer line 3a.
Also, the second outer line 3b has one end connected to the first ground conductor 4a via the fifth connection conductor 6e and the other end connected to the second ground conductor 4b via the sixth connection conductor 6f. That is, a fourth current-carrying path along which an electric current can flow between the one end and the other end of the second outer line 3b is formed in advance on the second outer line 3b.
Therefore, in the high-delay mode, a fourth return current flows from the one end of the second outer line 3b to the other end thereof due to the signal current in the signal line 1. This fourth return current is in a direction opposite to the current-carrying direction of the signal current in the signal line 1. Therefore, the fourth return current can reduce the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the second outer line 3b.
Here, a distance between the signal line 1 and the first outer line 3a and a distance between the signal line 1 and the second outer line 3b are greater than a distance between the signal line 1 and the first inner line 2a and a distance between the signal line 1 and the second inner line 2b. Therefore, the third return current and the fourth return current have a smaller effect of reducing the inductance L1 than the first return current and the second return current. When the reduced amount of the inductance L1 due to the third return current and the fourth return current is ΔLh, the effective inductance Lp of the signal line 1 is (L1-ΔLh).
On the other hand, the signal line 1 has capacitance C1 as parasitic capacitance. Also, in the high-delay mode, because the fourth electronic switch 7d is set in the ON state, the capacitor 5 is connected between the signal line 1 and the second ground conductor 4b. That is, the signal line 1 has capacitance Cb obtained by summing the capacitance Ca of the capacitor 5 and the capacitance C1 (parasitic capacitance). Therefore, the second propagation delay time TH proportional to (Lp×Cb)1/2 acts on the high-frequency signal propagating through the signal line 1.
Also, the high-frequency signal at the output end (the other end) of the signal line 1 becomes a signal obtained by delaying a phase of the high-frequency signal at the input end of the signal line 1 by the second phase difference OH due to this second propagation delay time TH. That is, in the high-delay mode, the second phase difference OH greater than the first phase difference θL of the low-delay mode is implemented by weakly reducing the inductance L1 of the signal line 1 to the inductance Lp using the third and fourth return currents and setting the fourth electronic switch 7d in the ON state.
Also, in the high-delay mode, the third electronic switch 7c is set in the OFF state. That is, in the high-delay mode, no action is taken to intentionally increase the loss of the signal line 1. As a result, the loss of the high-frequency signal in the high-delay mode approaches the loss of the high-frequency signal in the low-delay mode.
In the digital phase shifter A1 according to the first embodiment, the output circuit Z is connected to a subsequent stage of the eighth digital phase shift circuit Y8. The output impedance of the digital phase shift circuits Y1 to Y8 connected in cascade has a predetermined magnitude (absolute value) and imaginary impedance, but the output circuit Z increases the output impedance of the digital phase shifter A1 as compared with that of the input matching load connected to the input stage of the digital phase shifter A1 and transforms the output impedance into real impedance.
That is, because the output circuit Z constitutes a microstrip line composed of the output signal line 9 and the first individual ground line 11a, the output impedance of the digital phase shifter A1 is increased as compared with that of an input matching load connected to the input stage of the digital phase shifter A1. Also, because the output circuit Z includes the short stub 10 connected to the output signal line 9, the output impedance (complex impedance) of the digital phase shifter A1 is transformed into real impedance.
According to the first embodiment, when a specific real load greater than the input matching load connected to the input stage is connected to the output stage, it is possible to provide a digital phase shifter A1 capable of limiting fluctuations in the phase shift amount.
Also, the digital phase shifter A1 according to the first embodiment enables the size of the capacitor 5 to be reduced because the distance M between the signal line 1 and the first inner line 2a and the distance M between the signal line 1 and the second inner line 2b are set to a manufacturing limit or to be close to the manufacturing limit. The size of the upper electrode of the capacitor 5 is, for example, less than or equal to the width of the signal line 1.
Therefore, according to the first embodiment, miniaturization of the digital phase shifter A1 can be implemented. Also, according to the first embodiment, because a capacitance value Ca of the capacitor 5 can be decreased by reducing the size of the capacitor 5, it is possible to reduce the loss of a signal (a high-frequency signal).
Next, a second embodiment of the present invention will be described with reference to
In the modified output circuit ZA, the output signal line 9 of the output circuit Z is replaced with a modified output signal line 9A, and the short stub 10 is replaced with a modified short stub 10A. In the modified output signal line 9A, a line width W9 is set to be narrower than a line width W1 of a signal line 1. That is, in the modified output signal line 9A, a flow path cross-sectional area through which the signal current flows is set to be smaller than a flow path cross-sectional area of the signal line 1. The modified output signal line 9A increases the output impedance of the digital phase shifter A2.
Here, a first ground conductor 4a has a multilayer structure as described in the first embodiment. Because the line width W9 of the modified output signal line 9A is set to be narrower than the line width W1 of the signal line 1, a first individual ground line 11a in the second embodiment is connected to an upper conductive layer above the first individual ground line 11a in the first embodiment. That is, the first individual ground line 11a in the second embodiment is arranged closer to the modified output signal line 9A.
According to the digital phase shifter A2 according to the second embodiment, because the modified output circuit ZA is included, the output impedance of the digital phase shifter A2 is increased as compared with that of the input matching load connected to the input stage of the digital phase shifter A2 and the output impedance of the digital phase shifter A2 can be transformed into real impedance. That is, according to the second embodiment, when a specific real load greater than the input matching load connected to the input stage is connected to an output stage, it is possible to provide the digital phase shifter A2 capable of limiting fluctuations in a phase shift amount.
Also, according to the digital phase shifter A2 according to the second embodiment, because a distance M between the signal line 1 and the first inner line 2a and a distance M between the signal line 1 and the second inner line 2b are set to a manufacturing limit or to be close to the manufacturing limit, the miniaturization of the digital phase shifter A2 can be implemented and the loss of a signal (a high-frequency signal) can be reduced.
Next, a third embodiment of the present invention will be described with reference to
The modified digital phase shift circuit YAs is obtained by adding two ground conductors 15 (a third ground conductor 15a and a fourth ground conductor 15b) to the digital phase shift circuit Y8. The ground conductor 15 is formed in the same layer (the first conductive layer) as a signal line 1, a first inner line 2a, a second inner line 2b, a first outer line 3a, and a second outer line 3b. The ground conductor 15 is formed to overlap a first ground conductor 4a when viewed in an upward/downward direction.
One end of the third ground conductor 15a is connected to one end of the first inner line 2a and the other end of the third ground conductor 15a is connected to one end of the first outer line 3a. That is, the third ground conductor 15a connects the one end of the first inner line 2a and the one end of the first outer line 3a. One end of the fourth ground conductor 15b is connected to one end of the second inner line 2b and the other end of the fourth ground conductor 15b is connected to one end of the second outer line 3b. That is, the fourth ground conductor 15b connects the one end of the second inner line 2b and the one end of the second outer line 3b.
Also, as described above, the ground conductor 15 is formed to overlap the first ground conductor 4a when viewed in the upward/downward direction. Also, the third ground conductor 15a is electrically connected to the first ground conductor 4a via the first inner line 2a and the first outer line 3a and a first connection conductor 6a and a third connection conductor 6c. The fourth ground conductor 15b is electrically connected to the first ground conductor 4a via the second inner line 2b and the second outer line 3b and a second connection conductor 6b and a fifth connection conductor 6e. For this reason, the ground conductor 15 can also be said to be one conductive layer of the first ground conductor 4a.
In the modified output circuit ZB, the second individual ground line 11b of the modified output circuit ZA is replaced with an eighth individual ground line 11j, the third individual ground line 11c is replaced with a ninth individual ground line 11k, and a connection conductor 111 is added. Also, in the modified output circuit ZB, the connection position of the sixth individual ground line 11g is changed.
A line width of the eighth individual ground line 11j is set to be narrower than a line width of the second individual ground line 11b and the eighth individual ground line 11j is arranged closer to the modified output signal line 9A. That is, a distance between the eighth individual ground line 11j and the modified output signal line 9A is less than a distance between the second individual ground line 11b and the modified output signal line 9A shown in
A line width of the ninth individual ground line 11k is set to be narrower than a line width of the third individual ground line 11c and the ninth individual ground line 11k is arranged closer to the modified output signal line 9A. That is, a distance between the ninth individual ground line 11k and the modified output signal line 9A is less than a distance between the third individual ground line 11c and the modified output signal line 9A shown in
The connection conductor 111 is a line provided on one end side of the second inner line 2b in the modified digital phase shift circuit YAs and extends from one end of the second inner line 2b in a left direction. The connection conductor 111 is connected to the second inner line 2b and the fourth ground conductor 15b of the modified digital phase shift circuit YA8. Also, the connection conductor 111 is connected to the ninth individual ground line 11k. That is, the connection conductor 111 electrically connects the second inner line 2b and the fourth ground conductor 15b of the modified digital phase shift circuit YAs and the ninth individual ground line 11k.
The sixth individual ground line 11g is connected to one end of the first outer line 3a in the modified digital phase shift circuit YA8. In the second embodiment, as shown in
According to the digital phase shifter A3 according to the third embodiment, because the modified output circuit ZB is provided, the output impedance of the digital phase shifter A3 is increased as compared with that of the input matching load connected to the input stage of the digital phase shifter A3 and the output impedance of the digital phase shifter A3 can be transformed into real impedance. That is, according to the third embodiment, when a specific real load greater than the input matching load connected to the input stage is connected to an output stage, it is possible to provide the digital phase shifter A3 capable of limiting fluctuations in a phase shift amount.
Also, according to the digital phase shifter A3 according to the third embodiment, as in the digital phase shifter A2 according to the second embodiment, a distance M between the signal line 1 and the first inner line 2a and a distance M between the signal line 1 and the second inner line 2b are set to the manufacturing limit or to be close to the manufacturing limit. For this reason, it is possible to implement miniaturization of the digital phase shifter A3 and to reduce the loss of a signal (a high-frequency signal).
Next, a fourth embodiment of the present invention will be described with reference to
The ground layer 16 is a conductor having a rectangular shape when viewed in the upward/downward direction. The ground layer 16 extends from a side edge on a front side of a third ground conductor 15a to a side edge on a rear side of a fifth individual ground line 11f in a direction in which a signal line 1 extends and extends from a left end part of the third ground conductor 15a to a right edge of the fifth individual ground line 11f in a left/right direction. That is, the ground layer 16 is a conductive layer for covering an upper part of the third ground conductor 15a and partially covering upper parts of a modified short stub 10A, the fifth individual ground line 11f, and a sixth individual ground line 11g. The ground layer 16 has a function of shielding electromagnetic waves radiated upward from the modified short stub 10A. Also, the ground layer 16 is connected to the third ground conductor 15a, a first outer line 3a, and the fifth individual ground line 11f through vias 17.
The digital phase shifter A4 according to the present embodiment has only a configuration in which the ground layer 16 is added to the digital phase shifter A3 according to the third embodiment and the ground layer 16 is connected to the third ground conductor 15a, the first outer line 3a, and the fifth individual ground line 11f through the vias 17. Thus, as in the third embodiment, it is possible to limit fluctuations in the phase shift amount. Also, it is possible to implement miniaturization and reduce the loss of a signal (a high-frequency signal).
Finally, modifications of the above-described first to fourth embodiments will be described.
Although eight digital phase shift circuits Y1 to Y8 (or YA8), an output circuit Z, and the like are linearly connected in cascade in the first to fourth embodiments, a digital phase shifter A5 in which n digital phase shift circuits Y1 to Yn and an output circuit Z are connected in cascade in two rows (a multirow state) using two connection circuits E1 and E2 may be adopted as shown in
In
In the digital phase shifter A5 having a multirow configuration, because a space is provided between the rows as shown in the drawing, a short stub 10 can be arranged in this space. That is, according to the digital phase shifter A5 according to the modification, because it is not necessary to separately secure an arrangement space for the short stub 10, the arrangement space can be made small.
Also, a modification as shown in
On the other hand, the ground line for the stub according to the modification includes an additional ground line 11i connected to the tip portion of the signal line of the short stub 10 as shown in
Here, the short stub 10 in the first embodiment has been described as an example. The same can be similarly applied to the modified short stub 10A in the second to fourth embodiments. That is, in the second to fourth embodiments, an additional ground line 11i connected to the tip portion of the modified short stub 10A can also be provided.
Also, a modification as shown in
On the other hand, in the modification, the conductive layer Q of the first ground conductor 4a is cut off below the signal line 1 as shown in part (b) of
Here, the output circuit Z and the digital phase shift circuit Y8 of the first embodiment have been described as an example. The same can be similarly applied to the modified output circuit ZA and the digital phase shift circuit Y8 of the second embodiment and the modified output circuit ZB and the modified digital phase shift circuit YAs of the third and fourth embodiments. That is, in the second to fourth embodiments, the conductive layer Q of the first ground conductor 4a can also be cut off below the signal line 1 and the first individual ground line 11a can also be cut off below the modified output signal line 9A.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-024214 | Feb 2022 | JP | national |
| 2022-147145 | Sep 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/042237 | 11/14/2022 | WO |
