Patent Application
20240396530
The present invention relates to a digital phase shifter.
Priority is claimed on Japanese Patent Application No. 2022-136616, filed Aug. 30, 2022, the content of which is incorporated herein by reference.
In the following Non-Patent Document 1, a digitally controlled phase shift circuit (a digital phase shift circuit) targeting microwaves, quasi-millimeter waves, or millimeter waves is disclosed. As shown in
This digital phase shift circuit switches the operation mode between a low-delay mode and a high-delay mode by switching a return current flowing through the two inner lines or the two outer lines due to the transmission of signal waves in the signal line in accordance with the opening/closing of the two NMOS switches. That is, in the digital phase shift circuit, the operation mode becomes the low-delay mode when the return current flows through the two inner lines and the operation mode becomes the high-delay mode when the return current flows through the two outer lines.
Meanwhile, the above-described digital phase shift circuit is applied to a base station of a 5th generation (5G) communication network using, for example, a phased array antenna or the like, and a large number of digital phase shift circuits are actually mounted on a semiconductor substrate in a state in which the digital phase shift circuits are connected in cascade. That is, the above-described digital phase shift circuit is a unitary unit in the configuration of the actual phase shifter and constitutes a digital phase shifter that exhibits a desired function by connecting several tens of digital phase shift circuits in cascade.
However, it is desirable to make a value of inductance (an inductance value), which is one of the circuit constants, during the high-delay mode be sufficiently larger than an inductance value during the low-delay mode in this digital phase shifter, but there is a problem that a size thereof may increase when the inductance value is increased. As a result, it is difficult for a conventional digital phase shifter to sufficiently secure a difference (a phase shift amount) between the phase during the low-delay mode and the phase during the high-delay mode particularly at a low frequency.
The present invention has been made in view of the above-described circumstances and an objective of the present invention is to provide a digital phase shifter capable of increasing an inductance value during a high-delay mode as compared with conventional technologies.
A digital phase shifter of a first aspect of the present invention includes, for achieving the above-described objective, a first row; a second row arranged to extend in parallel to the first row and to overlap the first row viewed in an orthogonal direction to a direction in which the first row extends; and a connection unit electrically connecting one end of the first row and one end of the second row, wherein each of the first row and the second row is configured by connecting a plurality of digital phase shift circuits in cascade, each of the digital phase shift circuits including at least a signal line, two inner lines provided on both sides of the signal line, an outer line provided outside of one of the two inner lines or provided outside of the other of the two inner lines, a first ground conductor connected to one end of each of the inner lines and the outer line, a second ground conductor connected to the other end of the outer line, and two electronic switches, each of the electronic switches being provided between the other end of each of the inner lines and the second ground conductor, wherein the first ground conductor and the second ground conductor adjacent to each other are separated for the digital phase shift circuits adjacent to each other in the first row, wherein positional relationships of the outer line to the signal line are reversed for the digital phase shift circuits adjacent to each other in the first row, wherein the first ground conductor and the second ground conductor adjacent to each other are separated for the digital phase shift circuits adjacent to each other in the second row, wherein positional relationships of the outer line to the signal line are reversed for the digital phase shift circuits adjacent to each other in the second row, and wherein a plurality of the outer lines included in the first row are not adjacent to a plurality of the outer lines included in the second row in the orthogonal direction.
A second aspect of the present invention is that in the above-described first aspect, the inner lines and the outer line are formed in the same conductive layer.
A digital phase shifter of a third aspect of the present invention includes, for achieving the above-described objective, a plurality of digital phase shift circuits and a plurality of modified digital phase shift circuits, the plurality of digital phase shift circuits and the plurality of modified digital phase shift circuits being alternately connected in cascade, wherein each of the digital phase shift circuits includes at least a signal line, two inner lines provided on both sides of the signal line, two outer lines provided outside of the two inner lines, a first ground conductor connected to one end of each of the inner lines and the outer lines, a second ground conductor connected to the other end of each of the outer lines, and two electronic switches, each of the electronic switches being provided between the other end of each of the inner lines and the second ground conductor, and wherein each of the modified digital phase shift circuits includes at least a signal line, two inner lines provided on both sides of the signal line, two loop ground conductors having one ends connected to one ends of the inner lines and having U-shapes protruding toward outsides of the inner lines, and two electronic switches, one of the electronic switches being provided between the other end of one of the inner lines and the other end of one of the loop ground conductors, the other of the electronic switches being provided between the other end of the other of the inner lines and the other end of the other of the loop ground conductors.
A fourth aspect of the present invention is that in the above-described third aspect, one of the two outer lines is deleted in each of the plurality of digital phase shift circuits, and one of the two loop ground conductors is deleted in each of the plurality of modified digital phase shift circuits.
According to the present invention, it is possible to provide a digital phase shifter capable of increasing an inductance value during a high-delay mode as compared with conventional technologies.
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described. A digital phase shifter A1 according to the first embodiment is a high-frequency circuit that inputs high-frequency signals such as microwaves, quasi-millimeter waves, millimeter waves or the like and externally outputs a plurality of high-frequency signals that are phase-shifted by a predetermined phase shift amount.
As shown in
Here, the first to nth digital phase shift circuits B1 to Bn are unitary units constituting the digital phase shifter A1 and are linearly connected in cascade to have a relationship in which ones thereof are adjacent to each other. The first to nth digital phase shift circuits B1 to Bn have substantially similar functions to the digitally controlled phase shift circuit disclosed in Non-Patent Document 1.
That is, as denoted by representative reference sign B in
A side where the signal line 1 is provided in an opposite direction between the signal line 1 and the two ground conductors 4a and 4b may be referred to as an upper side of the basic digital phase shift circuit B and a side where the two ground conductors 4a and 4b are provided in the opposite direction may be referred to as a lower side of the basic digital phase shift circuit B.
The signal line 1 is a linear strip-shaped conductor extending in a predetermined direction as shown in
This signal line 1 electrically has inductance L1 as a distributed circuit constant. The inductance L1 is parasitic inductance having a magnitude corresponding to the shape of the signal line 1, such as the length or the like of the signal line 1. Also, the signal line 1 electrically has capacitance C1 as a distributed circuit constant. The capacitance C1 is parasitic capacitance between the signal line and the inner line, between the signal line and the outer line, or between silicon substrates.
The two inner lines 2a and 2b are linear strip-shaped conductors provided on both sides of the signal line 1. Between the two inner lines 2a and 2b, the first inner line 2a is spaced apart on one side (the right side in
The second inner line 2b is spaced apart on the other side (the left side in
The first outer line 3a is a linear strip-shaped conductor provided outside of the first inner line 2a on the one side of the signal line 1. That is, the first outer line 3a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is provided at a position farther from the signal line 1 than the first inner line 2a on the one side of the signal line 1.
Also, the first outer line 3a is provided parallel to the signal line 1 at an interval of a predetermined distance from the signal line 1 in a state in which the first inner line 2a is interposed therebetween as shown in the drawing. That is, the first outer line 3a extends in a direction that is the same as the extension direction of the signal line 1 similarly to the first inner line 2a and the second inner line 2b.
The second outer line 3b is a linear strip-shaped conductor provided outside of the second inner line 2b on the other side of the signal line 1, i.e., a side different from a side on which the first outer line 3a is. That is, the second outer line 3b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is provided at a position farther from the signal line 1 than the second inner line 2b on the other side of the signal line 1.
Also, the second outer line 3b is provided parallel to the signal line 1 at an interval of a predetermined distance from the signal line 1 in a state in which the second inner line 2b is interposed therebetween as shown in the drawing. That is, the second outer line 3b extends in a direction that is the same as the extension direction of the signal line 1 similarly to the first inner line 2a, the second inner line 2b, and the first outer line 3a described above.
The first ground conductor 4a is a linear strip-shaped conductor provided on one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the first ground conductor 4a is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is electrically grounded.
Also, the first ground conductor 4a is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b extending in the same direction. That is, the first ground conductor 4a is provided to extend in the left and right directions on the one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Furthermore, the first ground conductor 4a is provided below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at an interval of a predetermined distance therefrom. That is, a certain distance is provided in the upward/downward direction between the first ground conductor 4a and an end portion of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the length of the first ground conductor 4a is set such that one end thereof (the right end in
The second ground conductor 4b is a linear strip-shaped conductor provided on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the second ground conductor 4b is a long plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and is electrically grounded.
Also, the second ground conductor 4b is provided orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b extending in the same direction. That is, the second ground conductor 4b is provided to extend in the left and right directions on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Further, the second ground conductor 4b is provided below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b at an interval of a predetermined distance therefrom. That is, a certain distance is provided in the upward/downward direction between the second ground conductor 4b and an end portion of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the length of the second ground conductor 4b is set such that one end thereof (the right end in
The capacitor 5 has parallel flat plates having an upper electrode connected to the signal line 1 via the seventh connection conductor 6g and a lower electrode connected to the second ground conductor 4b via the fourth electronic switch 7d. The capacitor 5 has capacitance Ca corresponding to a facing area of the parallel flat plates. That is, the capacitance Ca is a circuit constant provided between the signal line 1 and the second ground conductor 4b.
The first connection conductor 6a is a conductor that electrically and mechanically connects one end of the first inner line 2a and the first ground conductor 4a. That is, the first connection conductor 6a is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the first inner line 2a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.
The second connection conductor 6b is a conductor that electrically and mechanically connects one end of the second inner line 2b and the first ground conductor 4a. That is, the second connection conductor 6b is a conductor extending in the upward/downward direction similarly to the first connection conductor 6a and has one end (an upper end) connected to the lower surface of the second inner line 2b and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.
The third connection conductor 6c is a conductor that electrically and mechanically connects one end of the first outer line 3a and the first ground conductor 4a. That is, the third connection conductor 6c is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of one end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.
The fourth connection conductor 6d is a conductor that electrically and mechanically connects the other end of the first outer line 3a and the second ground conductor 4b. That is, the fourth connection conductor 6d is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the other end of the first outer line 3a and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.
The fifth connection conductor 6e is a conductor that electrically and mechanically connects one end of the second outer line 3b and the first ground conductor 4a. That is, the fifth connection conductor 6e is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of one end of the second outer line 3b and the other end (a lower end) connected to the upper surface of the first ground conductor 4a.
The sixth connection conductor 6f is a conductor that electrically and mechanically connects the other end of the second outer line 3b and the second ground conductor 4b. That is, the sixth connection conductor 6f is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the other end of the second outer line 3b and the other end (a lower end) connected to the upper surface of the second ground conductor 4b.
The seventh connection conductor 6g is a conductor that electrically and mechanically connects the signal line 1 and one end of the capacitor 5. That is, the seventh connection conductor 6g is a conductor extending in the upward/downward direction and has one end (an upper end) connected to the lower surface of the signal line 1 and the other end (a lower end) connected to the one end (the upper surface) of the capacitor 5.
The first electronic switch 7a is a transistor that connects the other end of the first inner line 2a to the second ground conductor 4b so as to be able to open and close therebetween. The first electronic switch 7a is, for example, a MOS-type FET as shown in the drawing and has a drain terminal connected to the other end of the first inner line 2a, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
The first electronic switch 7a switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the first electronic switch 7a turns ON/OFF a connection between the other end of the first inner line 2a and the second ground conductor 4b through the switch controller 8.
The second electronic switch 7b is a transistor that connects the other end of the second inner line 2b and the second ground conductor 4b so as to be able to open and close therebetween. The second electronic switch 7b is a MOS-type FET similar to the first electronic switch 7a and has a drain terminal connected to the other end of the second inner line 2b, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
The second electronic switch 7b switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the second electronic switch 7b turns ON/OFF a connection between the other end of the second inner line 2b and the second ground conductor 4b through the switch controller 8.
The third electronic switch 7c is a transistor that connects one end of the signal line 1 and the first ground conductor 4a so as to be able to open and close therebetween. The third electronic switch 7c is a MOS-type FET similar to the first electronic switch 7a and the second electronic switch 7b described above and has a drain terminal connected to the signal line 1, a source terminal connected to the first ground conductor 4a, and a gate terminal connected to the switch controller 8. Also, the third electronic switch 7c may be provided between the other end of the signal line 1 and the second ground conductor 4b (see
This third electronic switch 7c switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the third electronic switch 7c turns ON/OFF a connection between one end of the signal line 1 and the first ground conductor 4a through the switch controller 8.
The fourth electronic switch 7d is a transistor that connects the other end of the capacitor 5 and the second ground conductor 4b so as to be able to open and close therebetween. The fourth electronic switch 7d is a MOS-type FET similar to the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c described above and has a drain terminal connected to the other end of the capacitor 5, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch controller 8.
This fourth electronic switch 7d switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the fourth electronic switch 7d turns ON/OFF a connection between the other end of the capacitor 5 and the second ground conductor 4b through the switch controller 8. Also, the fourth electronic switch 7d corresponds to the electronic switch for the capacitor in the present invention.
The switch controller 8 is a control circuit that controls the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d described above. The switch controller 8 includes four output ports and individually outputs gate signals from the output ports to the gate terminals of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d. That is, the switch controller 8 controls the ON/OFF operations of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d through the above-described gate signals.
Here, a schematic diagram in which the basic digital phase shift circuit B (i.e., the first to nth digital phase shift circuits B1 to Bn) is obliquely viewed such that the mechanical structure of the basic digital phase shift circuit B is easily understood is shown in
For example, in the basic digital phase shift circuit B, the signal line 1, the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b are formed in a first conductive layer, and the first ground conductor 4a and the second ground conductor 4b are formed in a second conductive layer facing the first conductive layer in a state in which the insulating layer is sandwiched between the first conductive layer and the second conductive layer.
The component of the first conductive layer, the component of the second conductive layer, the capacitor 5, and the first to fourth electronic switches 7a to 7d are connected through vias (through holes). That is, these vias are buried inside of the insulating layer and function as the first connection conductor 6a, the second connection conductor 6b, the third connection conductor 6c, the fourth connection conductor 6d, the fifth connection conductor 6e, the sixth connection conductor 6f, and the seventh connection conductor 6g described above.
As shown in
Next, the operation of the digital phase shifter A1 according to the first embodiment will be described in detail.
In the basic digital phase shift circuit B, the operation mode is switched in accordance with the conductive states of the first, second, and fourth electronic switches 7a, 7b, and 7d. That is, the operation modes of the basic digital phase shift circuit B include a low-delay mode in which only the first electronic switch 7a and the second electronic switch 7b are set in the ON state by the switch controller 8 and a high-delay mode in which only the fourth electronic switch 7d is set in the ON state by the switch controller 8.
In the low-delay mode, the switch controller 8 sets the first electronic switch 7a and the second electronic switch 7b in the ON state and sets the fourth electronic switch 7d in the OFF state. That is, in the low-delay mode, a first phase difference θL less than a second phase difference θ11 in the high-delay mode is caused by a first propagation delay time TL until the high-frequency signal propagates from the input end (the other end) of the signal line 1 to the output end (the one end) thereof.
This low-delay mode will be described in more detail. The first inner line 2a is in a state in which the other end thereof is connected to the second ground conductor 4b by setting the first electronic switch 7a in the ON state. That is, the first inner line 2a forms a first current-carrying path along which an electric current can flow between the one end and the other end of the first inner line 2a by connecting the one end of the first inner line 2a to the first ground conductor 4a via the first connection conductor 6a all the time and connecting the other end of the first inner line 2a to the second ground conductor 4b via the first electronic switch 7a.
On the other hand, the second inner line 2b is in a state in which the other end thereof is connected to the second ground conductor 4b by setting the second electronic switch 7b in the ON state. That is, the second inner line 2b forms a second current-carrying path along which an electric current can flow between the one end and the other end of the second inner line 2b by connecting one end of the second inner line 2b to the first ground conductor 4a via the second connection conductor 6b all the time and connecting the other end of the second inner line 2b to the second ground conductor 4b via the second electronic switch 7b.
Also, when a signal current flows from the input end to the output end of the signal line 1 in a state in which both ends of the first inner line 2a and the second inner line 2b are connected, a return current of the signal current flows from one end to the other end through the first inner line 2a and the second inner line 2b due to the propagation.
That is, a first return current flows through the first inner line 2a forming the first current-carrying path in a direction opposite to the current-carrying direction of the signal current by current-carrying of the signal current in the signal line 1. Also, a second return current flows through the second inner line 2b forming the second current-carrying path in a direction opposite to the current-carrying direction of the signal current, i.e., the direction that is the same as the direction of the first return current by current-carrying of the signal current in the signal line 1.
Here, both of the first return current flowing through the first inner line 2a and the second return current flowing through the second inner line 2b are in a direction opposite to the current-carrying direction of the signal current. Therefore, the first return current and the second return current act to reduce the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first inner line 2a and between the signal line 1 and the second inner line 2b. When a reduced amount of the inductance L1 is ΔLs, the effective inductance Lm of the signal line 1 is (L1-ΔLs).
Also, the signal line 1 has capacitance C1 as parasitic capacitance as described above. In the low-delay mode, since the fourth electronic switch 7d is set in the OFF state, a state is obtained in which the capacitor 5 is not connected between the signal line 1 and the second ground conductor 4b. That is, the capacitance Ca of the capacitor 5 does not affect the high-frequency signal propagating through the signal line 1. Therefore, the first propagation delay time TL proportional to (LmxCl)1/2 acts on the high-frequency signal propagating through the signal line 1.
Also, the high-frequency signal at the output end (one end) of the signal line 1 is a signal in which the phase of a high-frequency signal at the input end (the other end) of the signal line 1 is delayed by the first phase difference θL due to the first propagation delay time TL. That is, in the low-delay mode, the inductance L1 of the signal line 1 is reduced to the inductance Lm by the first return current and the second return current and therefore the original propagation delay time of the signal line 1 is reduced. As a result, the first phase difference θL smaller than the original phase difference that the signal line 1 has is implemented.
Here, in the low-delay mode, the loss of the signal line 1 is intentionally increased by setting the third electronic switch 7c in the ON state. The purpose of the loss imposition is to bring the output amplitude of the high-frequency signal in the low-delay mode close to the output amplitude in the high-delay mode
That is, the loss of the high-frequency signal in the low-delay mode is clearly less than the loss of the high-frequency signal in the high-delay mode. This loss difference causes an amplitude difference of the high-frequency signal output from the basic digital phase shift circuit B when the operation mode is switched between the low-delay mode and the high-delay mode. In this situation, in the basic digital phase shift circuit B, the above-described amplitude difference is eliminated by setting the third electronic switch 7c in the ON state in the low-delay mode.
On the other hand, in the high-delay mode, the switch controller 8 sets the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c in the OFF state and sets the fourth electronic switch 7d in the ON state. That is, in the high-delay mode, a second phase difference OH larger than the first phase difference θL in the low-delay mode is caused by a second propagation delay time TH until the high-frequency signal propagates from the input end (the other end) of the signal line 1 to the output end (the one end) thereof.
In this high-delay mode, since the first electronic switch 7a and the second electronic switch 7b are set in the OFF state, the first current-carrying path is not formed on the first inner line 2a and the second current-carrying path is not formed on the second inner line 2b. Therefore, the first return current flowing through the first inner line 2a becomes significantly small and the second return current flowing through the second inner line 2b becomes significantly small.
On the other hand, the first outer line 3a has one end connected to the first ground conductor 4a via the third connection conductor 6c and the other end connected to the second ground conductor 4b via the fourth connection conductor 6d. That is, a third current-carrying path along which an electric current can flow between the one end and the other end of the first outer line 3a is formed in advance on the first outer line 3a. Therefore, in the high-delay mode, a third return current flows from one end of the first outer line 3a to the other end thereof due to the signal current in the signal line 1. This third return current is in a direction opposite to the current-carrying direction of the signal current in the signal line 1. Therefore, the third return current can reduce the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first outer line 3a.
Also, the second outer line 3b has one end connected to the first ground conductor 4a via the fifth connection conductor 6e and the other end connected to the second ground conductor 4b via the sixth connection conductor 6f. That is, a fourth current-carrying path along which an electric current can flow between the one end and the other end of the second outer line 3b is formed in advance on the second outer line 3b. Therefore, in the high-delay mode, a fourth return current flows from the one end of the second outer line 3b to the other end thereof due to the signal current in the signal line 1. This fourth return current is in a direction opposite to the current-carrying direction of the signal current in the signal line 1. Therefore, the fourth return current can reduce the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the second outer line 3b.
Here, distances between the signal line 1 and the first outer line 3a and between the signal line 1 and the second outer line 3b are greater than distances between the signal line 1 and the first inner line 2a and between the signal line 1 and the second inner line 2b. Therefore, the third return current and the fourth return current have a smaller effect of reducing the inductance L1 than the first return current and the second return current. When the reduced amount of the inductance L1 due to the third return current and the fourth return current is ΔLh, the effective inductance Lp of the signal line 1 is (L1-ΔLh).
On the other hand, the signal line 1 has capacitance C1 as parasitic capacitance. Also, in the high-delay mode, since the fourth electronic switch 7d is set in the ON state, the capacitor 5 is connected between the signal line 1 and the second ground conductor 4b. That is, the signal line 1 has capacitance Cb obtained by summing the capacitance Ca of the capacitor 5 and the capacitance C1 (parasitic capacitance). Therefore, the second propagation delay time TH proportional to (LpxCb)1/2 acts on the high-frequency signal propagating through the signal line 1.
Also, the high-frequency signal at the output end of the signal line 1 is a signal in which the phase of the high-frequency signal at the input end of the signal line 1 is delayed by the second phase difference OH due to this second propagation delay time TH. That is, in the high-delay mode, the second phase difference θH greater than the first phase difference θL of the low-delay mode is implemented by weakly reducing the inductance L1 of the signal line 1 to the inductance Ln due to the third and fourth return currents and setting the fourth electronic switch 7d in the ON state.
Also, in the high-delay mode, the third electronic switch 7c is set in the OFF state. That is, in the high-delay mode, no action is taken to intentionally increase the loss of the signal line 1. As a result, the output amplitude of the high-frequency signal in the high-delay mode approaches the output amplitude in the low-delay mode.
In this digital phase shifter A1 according to the first embodiment, in ones adjacent to each other of the digital phase shift circuits B1 to Bn linearly connected in cascade, the outer line 3a and the outer line 3a adjacent to each other face each other with a gap P therebetween and the second outer line 3b and the second outer line 3b adjacent to each other face each other with a gap P therebetween. Also, in ones adjacent to each other of the digital phase shift circuits B1 to Bn, the first ground conductor 4a and the second ground conductor 4b adjacent to each other are arranged with a gap P therebetween.
That is, in ones adjacent to each other of the digital phase shift circuits B1 to Bn, each pair of the two first outer lines 3a and 3a adjacent to each other and the two second outer lines 3b and 3b adjacent to each other are arranged with a gap P without direct contact. Also, in ones adjacent to each other of the digital phase shift circuits B1 to Bn, the first ground conductor 4a and the second ground conductor 4b adjacent to each other are arranged with a gap P without direct contact.
For example, focusing on the first digital phase shift circuit B1, the second digital phase shift circuit B2, and the third digital phase shift circuit B3 shown in
Furthermore, the first ground conductor 4a of the first digital phase shift circuit B1 and the second ground conductor 4b of the second digital phase shift circuit B2 have a relationship of being adjacent to each other. For the first digital phase shift circuit B1 and the second digital phase shift circuit B2, each pair of the two first outer lines 3a and 3a, the two second outer lines 3b and 3b, and the first ground conductor 4a and the second ground conductor 4b are arranged with a gap P without contact.
Also, the first outer line 3a in the second digital phase shift circuit B2 and the first outer line 3a in the third digital phase shift circuit B3 have a relationship of being adjacent to each other. Also, the second outer line 3b in the second digital phase shift circuit B2 and the second outer line 3b in the third digital phase shift circuit B3 have a relationship of being adjacent to each other.
Furthermore, the first ground conductor 4a of the second digital phase shift circuit B2 and the second ground conductor 4b of the third digital phase shift circuit B3 have a relationship of being adjacent to each other. For the second digital phase shift circuit B2 and the third digital phase shift circuit B3, each pair of the two first outer lines 3a and 3a, the two second outer lines 3b and 3b, and the first ground conductor 4a and the second ground conductor 4b are arranged with a gap P without contact.
In this digital phase shifter A1, since each pair of the two first outer lines 3a and 3a adjacent to each other, the two second outer lines 3b and 3b adjacent to each other, and the first ground conductor 4a and the second ground conductor 4b adjacent to each other are not in direct contact with each other, a total net return path (a sum of 4b, 3b, and 4b) per unit during high delay can be lengthened and the inductance value can be increased. In the case of direct contact, return currents in opposite directions flowing through the adjacent second ground conductors 4b during high delay cancel each other out and the net return path length of the second ground conductors 4b becomes 0 (zero).
Therefore, according to the first embodiment, it is possible to provide the digital phase shifter A1 capable of increasing the inductance value during the high-delay mode as compared with conventional technologies. Therefore, according to the first embodiment, it is possible to increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode as compared with conventional technologies.
Here, the solid lines in
Also, the dotted lines in
Next, a second embodiment of the present invention will be described with reference to
In the digital phase shifter A1 according to the first embodiment, as shown in
That is, in the digital phase shifter A2 according to the second embodiment, as shown in
More specifically, as shown in
The distance between the first outer line 3a and the first outer line 3a adjacent to each other and the distance between the second outer line 3b and the second outer line 3b adjacent to each other in the digital phase shifter A2 are longer than those in the digital phase shifter A1 according to the first embodiment.
Since each pair of the two first outer lines 3a and 3a adjacent to each other, the two second outer lines 3b and 3b adjacent to each other, and the first ground conductor 4a and the second ground conductor 4b adjacent to each other in the digital phase shifter A2 are not in direct contact with each other and are spaced farther apart from each other than those in the digital phase shifter A1 according to the first embodiment, the inductance value during the high-delay mode in the digital phase shifter A2 can be further increased.
Therefore, according to the second embodiment, it is possible to provide the digital phase shifter A2 capable of further increasing the inductance value during the high-delay mode. Therefore, according to the second embodiment, it is possible to further increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode.
Next, a third embodiment of the present invention will be described with reference to
As described in the first embodiment, the basic digital phase shift circuit B is actually formed as a laminated structure in which a plurality of conductive layers are laminated with an insulating layer sandwiched therebetween. For example, in the basic digital phase shift circuit B, a signal line 1, a first inner line 2a, a second inner line 2b, a first outer line 3a, and a second outer line 3b are formed in a first conductive layer, and a first ground conductor 4a and a second ground conductor 4b are formed in a second conductive layer facing the first conductive layer in a state in which an insulating layer is sandwiched between the first conductive layer and the second conductive layer.
On the other hand, in the digital phase shifter A3 according to the third embodiment, in addition to the basic digital phase shift circuit B, a second modified digital phase shift circuit bB in which a conductive layer thereof is different from that of the basic digital phase shift circuit B is adopted, and the digital phase shifter A3 has a configuration in which the basic digital phase shift circuit B and the second modified digital phase shift circuit bB are alternately arranged.
That is, as shown in
More specifically, in the second modified digital phase shift circuit bB, the first outer line 3a and the second outer line 3b are formed in a conductive layer different from a conductive layer in which the first outer line 3a and the second outer line 3b of the basic digital phase shift circuit B are formed. Also, in the second modified digital phase shift circuit bB, the first ground conductor 4a and the second ground conductor 4b are formed in a conductive layer different from a conductive layer in which the first ground conductor 4a and the second ground conductor 4b of the basic digital phase shift circuit B are formed.
In the digital phase shifter A3, since each pair of the two first outer lines 3a and 3a adjacent to each other, the two second outer lines 3b and 3b adjacent to each other, and the first ground conductor 4a and the second ground conductor 4b adjacent to each other are not in direct contact with each other and are spaced farther apart from each other than those in the digital phase shifter A1 according to the first embodiment, the inductance value during the high-delay mode can be further increased.
Therefore, according to the third embodiment, it is possible to increase the inductance value during the high-delay mode as compared with that of the digital phase shifter A1 according to the first embodiment. Also, as a result, it is possible to increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode as compared with that of the digital phase shifter A1.
Next, a fourth embodiment of the present invention will be described with reference to
In addition to a basic digital phase shift circuit B, the digital phase shifter A4 adopts a third modified digital phase shift circuit cB in which the distances from a signal line 1 to a first outer line 3a and a second outer line 3b are different from those of the basic digital phase shift circuit B and the first outer line 3a, the second outer line 3b, a first ground conductor 4a, and a second ground conductor 4b are formed in a different conductive layer from that of the basic digital phase shift circuit B. Also, the digital phase shifter A4 has a configuration in which the basic digital phase shift circuit B and the third modified digital phase shift circuit cB are alternately arranged.
That is, as shown in
In the digital phase shifter A4, since each pair of the two first outer lines 3a and 3a adjacent to each other, the two second outer lines 3b and 3b adjacent to each other, and the first ground conductor 4a and the second ground conductor 4b adjacent to each other are not in direct contact with each other and are spaced farther apart from each other than those in the digital phase shifter A2 according to the second embodiment and the digital phase shifter A3 according to the third embodiment, the inductance value during the high-delay mode can be further increased.
Therefore, according to the fourth embodiment, it is possible to provide the digital phase shifter A4 capable of further increasing the inductance value during the high-delay mode. Thus, according to the fourth embodiment, it is possible to further increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode.
Next, a fifth embodiment of the present invention will be described with reference to
As shown in
The fourth modified digital phase shift circuit dB has a configuration in which, between a first outer line 3a and a second outer line 3b in a basic digital phase shift circuit B, the first outer line 3a is deleted. Also, the fourth modified digital phase shift circuit dB includes a first ground conductor 4a′ and a second ground conductor 4b′ shorter than a first ground conductor 4a and a second ground conductor 4b in the basic digital phase shift circuit B in accordance with the deletion of the first outer line 3a. The first ground conductor 4a′ and the second ground conductor 4b′ extend from the outer edge portion of the second outer line 3b to the outer edge portion of the first inner line 2a as shown in the drawing.
The fifth modified digital phase shift circuit eB has a configuration in which, between the first outer line 3a and the second outer line 3b in the basic digital phase shift circuit B, the second outer line 3b is deleted. Also, the fifth modified digital phase shift circuit eB includes a first ground conductor 4a″ and a second ground conductor 4b″ shorter than the first ground conductor 4a and the second ground conductor 4b in the basic digital phase shift circuit B in accordance with the deletion of the second outer line 3b. These first ground conductors 4a″ and the second ground conductors 4b″ extend from the outer edge portion of the first outer line 3a and the outer edge portion of the second inner line 2b as shown in the drawing.
In this digital phase shifter A5, there are no two first outer lines 3a and 3a adjacent to each other and there are no two second outer lines 3b and 3b adjacent to each other between ones adjacent to each other of the digital phase shift circuits B1 to Bn. Also, parts adjacent to each other of the first ground conductor 4a and the second ground conductor 4b are located only between the first inner line 2a and the second inner line 2b. Therefore, the inductance value during the high-delay mode can be increased.
Therefore, according to the fifth embodiment, the inductance value during the high-delay mode can be increased as compared with that of the digital phase shifter A2 according to the second embodiment. As a result, according to the fifth embodiment, a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode can be increased as compared with that of the digital phase shifter A1.
Next, a sixth embodiment of the present invention will be described with reference to
That is, the digital phase shifter A6 adopts, in addition to a basic digital phase shift circuit A, a sixth modified digital phase shift circuit fB including the first outer line 3a′ and the second outer line 3b′ in which the plurality of individual lines 3c to 3h having different distances from the signal line 1 are connected. Also, the digital phase shifter A6 has a configuration in which the basic digital phase shift circuit B and the third modified digital phase shift circuit cB are alternately arranged.
As shown in
In the sixth modified digital phase shift circuit fB, the first outer line 3a′ is configured by connecting three individual lines 3c to 3e using two connection lines 9a and 9b. The three individual lines 3c to 3e are linear strip-shaped conductors extending in the same direction as the signal line 1.
Among the three individual lines 3c to 3e, two individual lines 3c and 3e are arranged at the same distance from the signal line 1 as shown in the drawing. Between the two individual lines 3c and 3e, one individual line 3c has one end connected to a first ground conductor 4a and the other end connected to one end of one connection line 9a. Also, the other individual line 3e has one end connected to a second ground conductor 4b and the other end connected to one end of the other connection line 9b.
The remaining individual line 3d is arranged in a position farther from the signal line 1 than the two individual lines 3c and 3e and has one end connected to the other end of the one connection line 9a and the other end connected to one end of the other connection line 9b. The two connection lines 9a and 9b are linear strip-shaped conductors extending in the same direction as the first ground conductor 4a and the second ground conductor 4b.
That is, in the first outer line 3a′, the three individual lines 3c to 3e and the two connection lines 9a and 9b are connected in the order of individual line 3c→connection line 9a→individual line 3d→connection line 9b→individual line 3e.
On the other hand, the second outer line 3b′ is configured by connecting three individual lines 3f to 3h using two connection lines 9c and 9d. The three individual lines 3f to 3h are linear strip-shaped conductors extending in the same direction as the signal line 1.
Among the three individual lines 3f to 3h, two individual lines 3f and 3h are arranged at the same distance from the signal line 1 as shown in the drawing. Between the two individual lines 3f and 3h, one individual line 3f has one end connected to the first ground conductor 4a and the other end connected to one end of one connection line 9c. Also, the other individual line 3h has one end connected to the second ground conductor 4b and the other end connected to one end of the other connection line 9d.
The remaining individual line 3g is arranged in a position farther from the signal line 1 than the two individual lines 3f and 3h and has one end connected to the other end of the one connection line 9c and the other end connected to the other end of the other connection line 9d. The two connection lines 9c and 9d are linear strip-shaped conductors extending in the same direction as the first ground conductor 4a and the second ground conductor 4b.
That is, in the second outer line 3b′, the three individual lines 3f to 3h and the two connection lines 9c and 9d are connected in the order of individual line 3f→connection line 9c→individual line 3g→connection line 9d→individual line 3h.
In the digital phase shifter A6, the distances between the two first outer lines 3a and 3a adjacent to each other and between the two second outer lines 3b and 3b adjacent to each other are longer than those in the digital phase shifter A1 of the first embodiment. Also, in the first ground conductor 4a and the second ground conductor 4b adjacent to each other, since the first ground conductor and the second ground conductor of the sixth modified digital phase shift circuit fB are shorter than the first ground conductor and the second ground conductor of the basic digital phase shift circuit B, adjacent parts therebetween are small as compared with those of the digital phase shifter A1 of the first embodiment. Therefore, it is possible to increase the inductance value during the high-delay mode.
Therefore, according to the sixth embodiment, it is possible to provide the digital phase shifter A6 capable of increasing the inductance value during the high-delay mode. Thus, according to the sixth embodiment, it is possible to further increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode.
Next, a seventh embodiment of the present invention will be described with reference to
As described above, in the digital phase shifter A3 according to the third embodiment, between ones adjacent to each other of the digital phase shift circuits B1 to Bn, each pair of the first outer lines 3a, and the second outer lines 3b, in addition to the first ground conductor 4a and the second ground conductor 4b, are formed in different conductive layers. On the other hand, the digital phase shifter A7 according to the seventh embodiment has a configuration in which only a first ground conductor 4a and a second ground conductor 4b are formed in different conductive layers between ones adjacent to each other of digital phase shift circuits B to Bn.
As shown in
In the seventh modified digital phase shift circuit gB, a signal line 1, a first inner line 2a, a second inner line 2b, a first outer line 3a, and a second outer line 3b are formed in a first conductive layer. Also, in the seventh modified digital phase shift circuit gB, the first ground conductor 4a and the second ground conductor 4b are formed in a second conductive layer facing the first conductive layer in a state in which an insulating layer is sandwiched therebetween.
According to the digital phase shifter A7 of the seventh embodiment, since the first ground conductor 4a and the second ground conductor 4b adjacent to each other are formed in different conductive layers, the inductance value during the high-delay mode can be further increased approximately similarly to the digital phase shifter A3 according to the third embodiment.
Therefore, according to the seventh embodiment, a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode can be increased as compared with the digital phase shifter A1 of the first embodiment.
Next, an eighth embodiment of the present invention will be described with reference to
The digital phase shifter A8 has a configuration in which two digital phase shifters A5 according to the fifth embodiment are arranged in parallel and one ends thereof are electrically connected by a connection unit 10. In the eighth embodiment, one of the two digital phase shifters A5 arranged in parallel is referred to as a first row R1 and the other thereof is referred to as a second row R2. The second row R2 is arranged to overlap the first row R1 viewed in a direction (an upward/downward direction of the drawing) orthogonal to a direction in which the first row R1 extends.
The connection unit 10 has a U-shape that is convex in a direction in which the first row R1 and the second row R2 extend and connects an n digital phase shift circuit dBn included in the first row R1 and an nth digital phase shift circuit dBn included in the second row R2. The U-shaped connection unit 10 is arranged to open toward the first row R1 and the second row R2. Specifically, the connection unit 10 constitutes a so-called coplanar line and includes a signal line connection path 10a and two ground line connection paths 10b1 and 10b2 arranged at intervals on both sides of the signal line connection path 10a.
The signal line connection path 10a connects a signal line 1 included in the first row R1 and a signal line 1 included in the second row R2. The first ground line connection path 10b1 connects a first inner line 2a included in the nth digital phase shift circuit dBn of the first row R1 and a second inner line 2b included in the nth digital phase shift circuit dBn of the second row R2. The second ground line connection path 10b2 connects a second inner line 2b included in the nth digital phase shift circuit dBn of the first row R1 and a first inner line 2a included in the nth digital phase shift circuit dBn of the second row R2. Also, the connection unit 10 may constitute a so-called grounded coplanar line or a microstrip line.
Also, in the digital phase shifter A8 according to the eighth embodiment, the first row R1 and the second row R2 are arranged such that a plurality of outer lines 3a and 3b included in the first row R1 are not adjacent to (do not face) a plurality of outer lines 3a and 3b included in the second row R2 in a direction (an upward/downward direction of the drawing) orthogonal to a direction in which the first row R1 and the second row R2 extend. For example, the second outer line 3b included in a first digital phase shift circuit dB1 of the second row R2 and the first outer line 3a included in a second digital phase shift circuit eB2 of the first row R1 are in different positions in a direction (a left/right direction of the drawing) in which the first row R1 and the second row R2 extend. Also, the first outer line 3a included in the second digital phase shift circuit eB2 of the first row R1 and the second outer line 3b included in a third digital phase shift circuit dB3 of the second row R2 are in different positions in a direction (a left/right direction of the drawing) in which the first row R1 and the second row R2 extend.
According to the digital phase shifter A8 according to the eighth embodiment, since the two digital phase shifters A5 according to the fifth embodiment are connected, the inductance value during the high-delay mode can be further increased. Also, since the outer lines 3a and 3b are not adjacent to each other and are separated from each other between the first row R1 and the second row R2, it is possible to mitigate electromagnetic interference between the outer lines and to mitigate an influence on the phase shift amount.
Therefore, according to the eighth embodiment, it is possible to further increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode as compared with the digital phase shifter A1 of the first embodiment.
Also, in the digital phase shifter A8 according to the eighth embodiment, the outer lines 3a and 3b may be formed in the same conductive layer as the inner lines 2a and 2b or may be formed in a conductive layer different from that of the inner lines 2a and 2b.
Next, a ninth embodiment of the present invention will be described with reference to
That is, as shown in
In the eighth modified digital phase shift circuit hB, the first loop ground conductor 11a is a strip-shaped conductor extending in a curvilinear shape. One end of the first loop ground conductor 11a is connected to one end of a first inner line 2a. That is, the first loop ground conductor 11a is a curvilinear plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and has a U-shape protruding toward the outside of the first inner line 2a (a lower side of the drawing). The U-shaped first loop ground conductor 11a is arranged to open toward the first inner line 2a. Also, the first loop ground conductor 11a is electrically grounded.
The second loop ground conductor 11b is a strip-shaped conductor extending in a curvilinear shape. One end of the second loop ground conductor 11b is connected to one end of a second inner line 2b. That is, the second loop ground conductor 11b is a curvilinear plate-shaped conductor having a certain width, a certain thickness, and a predetermined length and has a U-shape protruding toward the outside of the second inner line 2b (an upper side of the drawing). The U-shaped second loop ground conductor 11b is arranged to open toward the second inner line 2b. Also, the second loop ground conductor 11b is electrically grounded.
A fifth electronic switch 7e is provided between the other end of the first loop ground conductor 11a and the other end of the first inner line 2a. The fifth electronic switch 7e is a transistor that connects the other end of the first loop ground conductor 11a and the other end of the first inner line 2a so as to be able to open and close therebetween. This electronic switch is a MOS-type FET similar to the above-described first to fourth electronic switches 7a to 7d and has a drain terminal connected to the other end of the first inner line 2a, a source terminal connected to the other end of the first loop ground conductor 11a, and a gate terminal connected to a switch controller 8.
The fifth electronic switch 7e switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the fifth electronic switch 7e turns ON/OFF a connection between the other end of the first inner line 2a and the other end of the first loop ground conductor 11a through the switch controller 8.
A sixth electronic switch 7f is provided between the other end of the second loop ground conductor 11b and the other end of the second inner line 2b. The sixth electronic switch 7f is a transistor that connects the other end of the second loop ground conductor 11b and the other end of the second inner line 2b so as to be able to open and close therebetween. This electronic switch is a MOS type FET similar to the above-described first to fifth electronic switches 7a to 7e and has a drain terminal connected to the other end of the second inner line 2b, a source terminal connected to the other end of the second loop ground conductor 11b, and a gate terminal connected to the switch controller 8.
The sixth electronic switch 7f switches the conductive state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input from the switch controller 8 to the gate terminal. That is, the sixth electronic switch 7f turns ON/OFF a connection between the other end of the second inner line 2b and the other end of the second loop ground conductor 11b through the switch controller 8.
In the eighth modified digital phase shift circuit hB, similarly to the basic digital phase shift circuit B, the operation mode is switched in accordance with the conductive states of the fifth electronic switch 7e and the sixth electronic switch 7f. That is, the operation modes of the eighth modified digital phase shift circuit hB include a low-delay mode in which both of the fifth electronic switch 7e and the sixth electronic switch 7f are set in the ON state by the switch controller 8 and a high-delay mode in which both of the fifth electronic switch 7e and the sixth electronic switch 7f are set in the OFF state by the switch controller 8.
That is, during the low-delay mode, a first return current flows through the first inner line 2a and a second return current flows through the second inner line 2b similarly to the basic digital phase shift circuit B. On the other hand, during the high-delay mode, a third return current flows through the first loop ground conductor 11a and a fourth return current flows through the second loop ground conductor 11b. A difference (a phase shift amount) occurs between the phase during the high-delay mode and the phase during the low-delay mode due to a difference between a change in inductance L1 caused by the first return current and the second return current and a change in the inductance L1 caused by the third return current and the fourth return current, or the like.
Also, in the digital phase shifter A9 according to the ninth embodiment, in the basic digital phase shift circuit B and the eighth modified digital phase shift circuit hB that are linearly connected in cascade and are adjacent to each other, the first outer line 3a and the first loop ground conductor 11a adjacent to each other are separated and the second outer line 3b and the second loop ground conductor 11b are separated. Also, in the digital phase shifter A9, each pair of the first ground conductor 4a and the loop ground conductor 11a adjacent to each other and the first ground conductor 4a and the loop ground conductor 11b adjacent to each other are separated, and each pair of the second ground conductor 4b and the loop ground conductor 11a adjacent to each other and the second ground conductor 4b and the loop ground conductor 11b adjacent to each other are separated. This is because the loop ground conductor of the eighth modified digital phase shift circuit hB has a U-shape.
According to the digital phase shifter A9, a distance between the loop ground conductor 11a and the outer line 3a, a distance between the loop ground conductor 11b and the outer line 3b, a distance between the loop ground conductor 11a and the ground conductor 4a, a distance between the loop ground conductor 11a and the ground conductor 4b, a distance between the loop ground conductor 11b and the ground conductor 4a, and a distance between the loop ground conductor 11b and the ground conductor 4b can be secured, and the inductance value during the high-delay mode can be increased.
Also, in the digital phase shifter A9 according to the ninth embodiment, the loop ground conductors 11a and 11b may be formed in the same conductive layer as the inner lines 2a and 2b or may be formed in a conductive layer different from that of the inner lines 2a and 2b. When the loop ground conductors 11a and 11b are formed in a conductive layer different from that of the inner lines 2a and 2b, between one end of the inner line 2a and one end of the loop ground conductor 11a and between one end of the inner line 2b and one end of the loop ground conductor 11b, connection conductors extending in an upward/downward direction similarly to the first to seventh connection conductors 6a to 6g may connect.
Also, each of the loop ground conductors 11a and 11b may not extend in a curvilinear shape or may have a shape in which a plurality of linearly extending conductors are connected. Alternatively, each loop ground conductor may have a shape obtained by appropriately combining and connecting a curvilinearly extending conductor and a linearly extending conductor.
Next, a tenth embodiment of the present invention will be described with reference to
As shown in
The fourth modified digital phase shift circuit dB has the same configuration as the configuration adopted in the fifth embodiment. The ninth modified digital phase shift circuit iB has a configuration in which between the first loop ground conductor 11a and the second loop ground conductor 11b in the eighth modified digital phase shift circuit hB, the first loop ground conductor 11a is deleted.
According to the digital phase shifter A10, the inductance value during the high-delay mode can also be increased similarly to the digital phase shifter A9 according to the ninth embodiment. Also, since the first ground conductor 4a and the first loop ground conductor 11a are deleted, it is possible to achieve size reduction as compared with the digital phase shifter A9 and to increase a difference (a phase shift amount) between the phase during the low-delay mode and the phase during the high-delay mode.
Therefore, according to the tenth embodiment, it is possible to further increase a difference (a phase shift amount) between the phase during the high-delay mode and the phase during the low-delay mode as compared with the digital phase shifter A1 of the first embodiment. Also, according to the tenth embodiment, the size of the digital phase shifter A10 can be reduced.
Also, in the digital phase shifter A10 according to the tenth embodiment, the second outer line 3b may be deleted instead of the first outer line 3a between the two outer lines 3a and 3b included in each basic digital phase shift circuit B. In other words, in the digital phase shifter A10 according to the tenth embodiment, each fourth modified digital phase shift circuit dB may be replaced with the fifth modified digital phase shift circuit eB described in the fifth embodiment. Also, the second loop ground conductor 11b may be deleted instead of the first loop ground conductor 11a between the two loop ground conductors 11a and 11b included in each eighth modified digital phase shift circuit hB.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-136616 | Aug 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2023/003963 | 2/7/2023 | WO |
