Patent Grant
12040765
The present invention relates to a digital phase shifter.
Priority is claimed on Japanese Patent Application No. 2022-024000, filed Feb. 18, 2022, the content of which is incorporated herein by reference.
A digital-controlled phase shift circuit (a digital phase shift circuit) for microwaves, submillimeter waves, or millimeter waves is disclosed in Non-Patent Document 1. As shown in FIG. 2 of Non-Patent Document 1, the digital phase shift circuit includes a signal line, two inner lines that are provided on two sides of the signal line, two outer lines that are provided on outer sides of the two inner lines, a first grounding bar that is connected to one end of each of the two inner lines and the two outer lines, a second grounding bar that is connected to the other end of each of the two outer lines, and two NMOS switches that are provided between the other ends of the two inner lines and the second grounding bar.
The digital phase shift circuit switches an operation mode thereof between a low-delay mode and a high-delay mode by switching a return current flowing in the two inner lines or the two outer lines according to on/off states of the two NMOS switches due to transmission of signal waves in the signal line. That is, the operation mode of the digital phase shift circuit is changed to the low-delay mode when a return current flows in the two inner lines and the operation mode is changed to the high-delay mode when a return current flows in the two outer lines.
The digital phase shift circuit is applied to, for example, a base station using a phased array antenna or the like and is actually mounted on a semiconductor substrate in a state in which a plurality of digital phase shift circuits are connected in a cascade manner. That is, the digital phase shift circuit is a basic unit in an actual configuration of a phase shifter, and a digital phase shifter is constructed by connecting several tens of digital phase shift circuits constituting individual stages in a cascade manner. The digital phase shifter realizes a plurality of phase shift quantities as a whole by setting the basic unit of each stage to a low-delay mode or a high-delay mode.
In such a digital phase shifter, the phase shift quantities of the stages are required to be evenly changed when switching operation modes of the basic units of the stages, but the inventor of the present invention found that the phase shift quantities of the stages are not evenly changed in a state in which the operation modes are abnormally set. In the digital phase shifter, even change of the phase shift quantities is lost, for example, when a state in which one basic unit is set to the high-delay mode and the other basic units are set to the low-delay mode is changed to a state in which all the basic units are set to the low-delay mode.
The present invention was made in consideration of the aforementioned circumstances and an object thereof is to provide a digital phase shifter that can more evenly change phase shift quantities.
In order to achieve the aforementioned object, a first aspect of the present invention is a digital phase shifter including: a plurality of digital phase shift circuits connected in a cascade manner, wherein each of the plurality of digital phase shift circuits includes a signal line, two inner lines provided on two sides of the signal line, two outer lines provided on outer sides of the inner lines, a first grounding conductor connected to one end of each of the inner lines and the outer lines, a second grounding conductor connected to other ends of the outer lines, and two electronic switches provided between other ends of the inner lines and the second grounding conductor, and is set to a low-delay mode in which return currents flow in the inner lines or a high-delay mode in which return currents flow in the outer lines, and wherein the digital phase shifter includes: a phase shift quantity moderator that moderates unevenness of a phase shift quantity of an uneven digital phase shift circuit of the plurality of digital phase shift circuits, of which the phase shift quantity is uneven with respect to those of other digital phase shift circuits of the plurality of digital phase shift circuits.
A second aspect of the present invention is the digital phase shifter according to the first aspect, including an output circuit including a single output signal line connected to the signal line of the uneven digital phase shift circuit and two output-grounding lines connected to the two inner lines of the uneven digital phase shift circuit, wherein the phase shift quantity moderator is an extension-grounding line connected to the first grounding conductor of the uneven digital phase shift circuit and an output-grounding line of the output-grounding lines.
A third aspect of the present invention is that in the digital phase shifter according to the second aspect, a length from a center of the output signal line to an outer edge of the extension-grounding line is set to be greater than ¼ of each length of the first and second grounding conductors.
A fourth aspect of the present invention is that in the digital phase shifter according to the first aspect, the phase shift quantity moderator is the uneven digital phase shift circuit and satisfies at least one of a condition that a length of the uneven digital phase shift circuit is less than that of the other digital phase shift circuits, a condition that a distance between the signal line and each inner line of the uneven digital phase shift circuit is greater than that of the other digital phase shift circuits, and a condition that a distance between the signal line and each outer line of the uneven digital phase shift circuit is less than that of the other digital phase shift circuits.
A fifth aspect of the present invention is that in the digital phase shifter according to any one of the first to fourth aspects, each of the plurality of digital phase shift circuits includes a capacitor of which an upper electrode is connected to the signal line and a lower electrode is connected to at least one of the first grounding conductor and the second grounding conductor.
A sixth aspect of the present invention is that in the digital phase shifter according to the fifth aspect, the phase shift quantity moderator satisfies a condition that the capacitor of the uneven digital phase shift circuit is smaller than each capacitor of the other digital phase shift circuits.
A seventh aspect of the present invention is that in the digital phase shifter according to the fifth or sixth aspect, each of the plurality of digital phase shift circuits further includes an electronic switch for a capacitor provided between the lower electrode of the capacitor and at least one of the first grounding conductor and the second grounding conductor.
An eighth aspect of the present invention is that in the digital phase shifter according to any one of the first to seventh aspects, each of the plurality of digital phase shift circuits includes two electronic switches that are provided between the other ends of the inner lines and the second grounding conductor, wherein the phase shift quantity moderator satisfies a condition that the two electronic switches of the uneven digital phase shift circuit is smaller than the two electronic switches of the other digital phase shift circuits.
According to the present invention, it is possible to provide a digital phase shifter that can more evenly change phase shift quantities.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
A first embodiment of the present invention will be first described below. A digital phase shifter A1 according to the first embodiment is a high-frequency circuit that receives an input of a high-frequency signal of microwaves, submillimeter waves, millimeter waves, or the like and outputs a plurality of high-frequency signals shifted in phase by a predetermined phase shift quantity to the outside.
The digital phase shifter A1 has a configuration in which an input circuit X, eight (a plurality of) digital phase shift circuits Y1 to Y8, and an output circuit Z are connected in a cascade manner as shown in
In the digital phase shifter A1, the input circuit X, the eight-stage (a plurality of stages of) digital phase shift circuits Y1 to Y8, and the output circuit Z are linearly connected in a cascade manner as shown in the drawing. In the digital phase shifter A1, a high-frequency signal input from one end (the left end) of the input circuit X is sequentially shifted in phase by a predetermined phase shift quantity by passing through the digital phase shift circuits Y1 to Y8, and the phase-shifted signal is output from one end (the right end) of the output circuit Z to the outside.
The input circuit X is a high-frequency circuit that receives a high-frequency signal with a wavelength band such as microwaves, submillimeter waves, millimeter waves or the like from the outside and supplies the received high-frequency signal to the first digital phase shift circuit Y1 adjacent thereto on the right side thereof. The input circuit X includes an input signal line x1 and two input-grounding lines x2 and x3 as shown in
The input signal line x1 is a linear strip-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and extends in a predetermined direction. When a high-frequency signal with a wavelength band such as microwaves. submillimeter waves, millimeter waves or the like is applied to an input end (the left end) of the input signal line x1 from the outside, a signal current flows from the input end (the left end) to an output end (the right end) of the input signal line x1.
The output end (the right end) of the input signal line x1 is connected to one end of a signal line 1 of the first digital phase shift circuit Y1 which will be described later. That is, the input signal line x1 transmits the high-frequency signal input from the outside to the input end (the left end) thereof and supplies the high-frequency signal from the output end (the right end) thereof to the signal line 1 of the first digital phase shift circuit Y1.
The two input-grounding lines x2 and x3 are linear strip-shaped conductors that are provided on two sides of the input signal line x1. Among the two input-grounding lines x2 and x3, the first input-grounding line x2 is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is disposed to be separated from one side (the lower side in
The first input-grounding line x2 is electrically grounded, one end (the left end) thereof is connected to the outside, and the other end (the right end) thereof is connected to a second grounding conductor 4b in the first digital phase shift circuit Y1 which will be described later. In the first input-grounding line x2, a first return current which will be described later flows from the other end (the right end) to the one end (the left end).
Among the two input-grounding lines x2 and x3, the second input-grounding line x3 is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is disposed to be separated from the other side (the upper side in
The eight (a plurality of) digital phase shift circuits Y1 to Y8 are basic phase shift units constituting the digital phase shifter A1 and are linearly connected in a cascade manner in the order of the first digital phase shift circuit Y1→the second digital phase shift circuit Y2→(omission)→the eighth digital phase shift circuit Y8 as shown in the drawing. The digital phase shift circuits Y1 to Y8 have substantially the same function as the digital-controlled phase shift circuit disclosed in Non-Patent Document 1.
That is, each of the digital phase shift circuits Y1 to Y8 is a delay circuit that delays a high-frequency signal input from the input circuit X or the digital phase shift circuit adjacent thereto on the left side by a preset phase shift quantity and outputs the delayed high-frequency signal to the digital phase shift circuit adjacent thereto on the right side or the output circuit Z. Each of the digital phase shift circuits Y1 to Y8 includes a signal line 1, two inner lines 2a and 2b, two outer lines 3a and 3b, two grounding conductors 4a and 4b, a capacitor 5, seven connection conductors 6a to 6g, four electronic switches 7a to 7d, and a switch controller 8 as indicated by a representative sign Y in
The signal line 1 is a linear strip-shaped conductor that extends in a predetermined direction as shown in
In the configuration shown in
An actual installation attitude of the digital phase shift circuit Y is not limited to this attitude and may have any attitude.
The signal line 1 has an inductance L1 which is an electrical distributed circuit constant. The inductance L1 is a parasitic inductance with a size according to the shape of the signal line 1 such as a length of the signal line 1. The signal line 1 also has a capacitance C1 which is an electrical distributed circuit constant. The capacitance C1 is a parasitic capacitance between the signal line and the inner line, between the signal line and outer line, or between silicon substrates.
The two inner lines 2a and 2b are linear strip-shaped conductors that are provided on two sides of the signal line 1. Among the two inner lines 2a and 2b, the first inner line 2a is a long plate-shaped conductor that is disposed to be separated from one side (the right side in
The second inner line 2b is a long plate-shaped conductor that is disposed to be separated from the other side (the left side in
The first outer line 3a is a linear strip-shaped conductor that is provided on an outer side of the first inner line 2a on one side of the signal line 1. That is, the first outer line 3a is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is provided at a position which is farther from the signal line 1 than the first inner line 2a on the one side of the signal line 1.
The first outer line 3a is provided parallel to the signal line 1 with a predetermined distance therefrom in a state in which the first inner line 2a is interposed therebetween as shown in the drawing. That is, the first outer line 3a extends in the same direction as the extension direction of the signal line 1 similarly to the first inner line 2a and the second inner line 2b.
The second outer line 3b is a linear strip-shaped conductor that is provided on an outer side of the second inner line 2b on the other side of the signal line 1, that is, on the side other than the first outer line 3a. That is, the second outer line 3b is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is provided at a position which is farther from the signal line 1 than the second inner line 2b on the other side of the signal line 1.
The second outer line 3b is provided parallel to the signal line 1 with a predetermined distance therefrom in a state in which the second inner line 2b is interposed therebetween as shown in the drawing. That is, the second outer line 3b extends in the same direction as the extension direction of the signal line 1 similarly to the first inner line 2a, the second inner line 2b, and the first outer line 3a.
The first grounding conductor 4a is a linear strip-shaped conductor that is provided on one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the first grounding conductor 4a is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is electrically grounded.
The first grounding conductor 4a is provided to be orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b which extend in an equal direction. That is, the first grounding conductor 4a is provided to extend in the left-right direction on one end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
The first grounding conductor 4a is provided a predetermined distance below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, a fixed distance is provided in the up-down direction between the first grounding conductor 4a and the ends of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the first grounding conductor 4a is set in length such that one end in the left-right direction (the right end in
The second grounding conductor 4b is a linear strip-shaped conductor that is provided on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, the second grounding conductor 4b is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is electrically grounded.
The second grounding conductor 4b is provided to be orthogonal to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b which extend in an equal direction. That is, the second grounding conductor 4b is provided to extend in the left-right direction on the other end side of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
The second grounding conductor 4b is provided a predetermined distance below the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. That is, a fixed distance is provided in the up-down direction between the second grounding conductor 4b and the ends of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.
Here, the second grounding conductor 4b is set in length such that one end in the left-right direction (the right end in
The capacitor 5 is parallel plates of which an upper electrode is connected to the signal line 1 via the seventh connection conductor 6g and a lower electrode is connected to the second grounding conductor 4b via the fourth electronic switch 7d. The capacitor 5 has a capacitance Ca according to the opposite area of the parallel plates. That is, the capacitance Ca is a circuit constant that is provided between the signal line 1 and the second grounding conductor 4b. The lower electrode of the capacitor 5 may be connected to the first grounding conductor 4a via the fourth electronic switch 7d, or the lower electrode of the capacitor 5 may be connected to each of the first and second grounding conductors 4a and 4b via the fourth electronic switch 7d.
The first connection conductor 6a is a conductor that electrically and mechanically connects one end of the first inner line 2a and the first grounding conductor 4a. That is, the first connection conductor 6a is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the first inner line 2a, and the other end (the lower end) thereof is connected to the top of the first grounding conductor 4a.
The second connection conductor 6b is a conductor that electrically and mechanically connects one end of the second inner line 2b and the first grounding conductor 4a. That is, the second connection conductor 6b is a conductor extending in the up-down direction similarly to the first connection conductor 6a, one end (the upper end) thereof is connected to the bottom of the second inner line 2b, and the other end (the lower end) thereof is connected to the top of the first grounding conductor 4a.
The third connection conductor 6e is a conductor that electrically and mechanically connects one end of the first outer line 3a and the first grounding conductor 4a. That is, the third connection conductor 6e is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the first outer line 3a at the one end thereof, and the other end (the lower end) thereof is connected to the top of the first grounding conductor 4a.
The fourth connection conductor 6d is a conductor that electrically and mechanically connects the other end of the first outer line 3a and the second grounding conductor 4b. That is, the fourth connection conductor 6d is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the first outer line 3a at the other end thereof, and the other end (the lower end) thereof is connected to the top of the second grounding conductor 4b.
The fifth connection conductor 6e is a conductor that electrically and mechanically connects one end of the second outer line 3b and the first grounding conductor 4a. That is, the fifth connection conductor 6e is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the second outer line 3b at the one end thereof, and the other end (the lower end) thereof is connected to the top of the first grounding conductor 4a.
The sixth connection conductor 6f is a conductor that electrically and mechanically connects the other end of the second outer line 3b and the second grounding conductor 4b. That is, the sixth connection conductor 6f is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the second outer line 3b at the other end thereof, and the other end (the lower end) thereof is connected to the top of the second grounding conductor 4b.
The seventh connection conductor 6g is a conductor that electrically and mechanically connects the signal line 1 and the upper electrode of the capacitor 5. That is, the seventh connection conductor 6g is a conductor extending in the up-down direction, one end (the upper end) thereof is connected to the bottom of the signal line 1, and the other end (the lower end) thereof is connected to the upper electrode (the top) of the capacitor 5.
The first electronic switch 7a is a transistor that disconnectably connects the other end of the first inner line 2a and the second grounding conductor 4b. The first electronic switch 7a is, for example, an MOS FET as shown in the drawing, a drain terminal thereof is connected to the other end of the first inner line 2a, a source terminal thereof is connected to the second grounding conductor 4b, and a gate terminal thereof is connected to the switch controller 8.
The first electronic switch 7a switches a conduction state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input to the gate terminal thereof from the switch controller 8. That is, the first electronic switch 7a turns on/off connection between the other end of the first inner line 2a and the second grounding conductor 4b under the control of the switch controller 8.
The second electronic switch 7b is a transistor that disconnectably connects the other end of the second inner line 2b and the second grounding conductor 4b. The second electronic switch 7b is an MOS FET similarly to the first electronic switch 7a, a drain terminal thereof is connected to the other end of the second inner line 2b, a source terminal thereof is connected to the second grounding conductor 4b, and a gate terminal thereof is connected to the switch controller 8.
The second electronic switch 7b switches a conduction state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input to the gate terminal thereof from the switch controller 8. That is, the second electronic switch 7b turns on/off connection between the other end of the second inner line 2b and the second grounding conductor 4b under the control of the switch controller 8.
The third electronic switch 7e is a transistor that disconnectably connects one end of the signal line 1 and the second grounding conductor 4b. The third electronic switch 7c is an MOS FET similarly to the first electronic switch 7a and the second electronic switch 7b, a drain terminal thereof is connected to the one end of the signal line 1, a source terminal thereof is connected to the second grounding conductor 4b, and a gate terminal thereof is connected to the switch controller 8.
The third electronic switch 7c switches a conduction state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input to the gate terminal thereof from the switch controller 8. That is, the third electronic switch 7e turns on/off connection between the one end of the signal line 1 and the second grounding conductor 4b under the control of the switch controller 8.
The fourth electronic switch 7d is a transistor that disconnectably connects the lower electrode of the capacitor 5 and the second grounding conductor 4b. The fourth electronic switch 7d is an MOS FET similarly to the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c, a drain terminal thereof is connected to the lower electrode of the capacitor 5, a source terminal thereof is connected to the second grounding conductor 4b, and a gate terminal thereof is connected to the switch controller 8.
The fourth electronic switch 7d switches a conduction state between the drain terminal and the source terminal to an open state or a closed state on the basis of a gate signal input to the gate terminal thereof from the switch controller 8. That is, the fourth electronic switch 7d turns on/off connection between the lower electrode of the capacitor 5 and the second grounding conductor 4b under the control of the switch controller 8. The fourth electronic switch 7d corresponds to an electronic switch for a capacitor in the claims.
The switch controller 8 is a control circuit that controls the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d. The switch controller 8 includes four output ports and individually outputs the gate signals to the gate terminals of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d from the corresponding output ports. That is, the switch controller 8 controls ON/OFF operations of the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d in accordance with the gate signals.
Among the plurality of digital phase shift circuits Y1 to Y8 shown in
The eighth digital phase shift circuit Y8 is a most downstream digital phase shift circuit located most downstream in a transmission direction of the high-frequency signal. Although details will be described later, the eighth digital phase shift circuit Y8 is an uneven digital phase shift circuit of which a phase shift quantity when it is switched from the high-delay mode to the low-delay mode is uneven with respect to the phase shift quantities of the other digital phase shift circuits Y1 to Y7.
The output circuit Z is a high-frequency circuit adjacent to the right side (the right side in
The output signal line z1 is a linear strip-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and extends in a predetermined direction. An input end (the left end) of the output signal line z1 is connected to the output end (the right end) of the signal line 1 in the eighth digital phase shift circuit Y8. The output signal line z1 transmits a high-frequency signal input to the input end (the left end) thereof from the eighth digital phase shift circuit Y's and outputs the high-frequency signal from an output end (the right end) thereof to the outside. That is, in the output signal line z1, a signal current of the high-frequency signal flows from the input end (the left end) to the output end (the right end).
The two output-grounding lines z2 and z3 are linear strip-shaped conductors that are provided on two sides of the output signal line z1. Among the two output-grounding lines z2 and z3, the first output-grounding line z2 is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length and is disposed to be separated from one side (the lower side in
The first output-grounding line z2 is electrically grounded, one end (the left end) thereof is connected to the first grounding conductor 4a in the eighth digital phase shift circuit Y8, and the other end (the right end) thereof is connected to the outside. In the first output-grounding line z2, a first return current which will be described later flows from the other end (the right end) to the one end (the left end).
Among the two output-grounding lines z2 and z3, the second output-grounding line z3 is a long plate-shaped conductor that has a fixed width, a fixed thickness, and a predetermined length similarly to the first output-grounding line z2 and is disposed to be separated from the other side (the upper side in
The two extension-grounding lines z4 and z5 are phase shift quantity moderators that are connected to the first grounding conductor 4a and respectively to the two output-grounding lines z2 and z3 in the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit). That is, among the two extension-grounding lines z4 and z5, the first extension-grounding line z4 is connected to the first grounding conductor 4a and the first output-grounding line z2 in the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit). The first extension-grounding line z4 is a first phase shift quantity moderator that moderates unevenness of the phase shift quantity of the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit) with respect to those of the other digital phase shift circuits Y1 to Y7.
The first extension-grounding line z4 is provided with a width W from the outer edge of the first output-grounding line z2 to one end (an end portion) of the first grounding conductor 4a in the eighth digital phase shift circuit Y8 as shown in the drawing. The width W is a width in a direction (hereinafter also referred to as a width direction) orthogonal to a cascade connection direction of the plurality of digital phase shift circuits Y, that is, a width in the extension direction of the first and second grounding conductors 4a and 4b. That is, the first extension-grounding line z4 is a rectangular grounding line with one end of the first grounding conductor 4a, one end (the left end) of the first output-grounding line z2, and the other end (the right end) of the first output-grounding line z2 as apices. The first extension-grounding line z4 is not limited to a configuration having the width W, and the width thereof has only to be set such that the length from the center of the output signal line z1 (the center in the width direction of the output signal line z1) to the outer edge (the outer end in the width direction, that is, the lower edge in
The second extension-grounding line z5 is connected to the first grounding conductor 4a and the second output-grounding line z3 in the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit). The second extension-grounding line z5 is a second phase shift quantity moderator that moderates unevenness of the phase shift quantity of the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit) with respect to those of the other digital phase shift circuits Y1 to Y7.
The second extension-grounding line z5 is provided with a width W from the outer edge of the second output-grounding line z3 to the other end (an end portion) of the first grounding conductor 4a in the eighth digital phase shift circuit Y8 as shown in the drawing. That is, the second extension-grounding line z5 is a rectangular grounding line with the other end of the first grounding conductor 4a, one end (the left end) of the second output-grounding line z3, and the other end (the right end) of the second output-grounding line z3 as apices. The second extension-grounding line z5 is not limited to a configuration having the width W, and the width thereof has only to be set such that the length from the center of the output signal line z1 (the center in the width direction of the output signal line z1) to the outer edge (the outer end in the width direction, that is, the upper edge in
For example, in the digital phase shift circuit Y, the signal line 1, the first inner line za, the second inner line zb, the first outer line 3a, and the second outer line 3b are formed in a first conductive layer, and the first grounding conductor 4a and the second grounding conductor 4b are formed in a second conductive layer facing the first conductive layer with an insulating layer interposed therebetween.
The components of the first conductive layer, the components of the second conductive layer, the capacitor 5, and the first to fourth electronic switches 7a to 7d are connected using vias (through-holes). That is, the vias are buried in an insulating layer and serve as the first connection conductor 6a, the second connection conductor 6b, the third connection conductor 6c, the fourth connection conductor 6d, the fifth connection conductor 6e, the sixth connection conductor 6f, and the seventh connection conductor 6g.
In the digital phase shifter A1 including the digital phase shift circuits Y (the digital phase shift circuits Y1 to Y8) as components, the eight digital phase shift circuits Y1 to Y8 are disposed to be in contact with each other as shown in
Operations of the digital phase shifter A1 according to the first embodiment will be described below in detail with additional reference to
The operation mode of the digital phase shift circuit Y (each of the digital phase shift circuits Y1 to Y8) in the digital phase shifter A1 is switched according to conduction states of the first, second, and fourth electronic switches 7a, 7b, and 7d. That is, the operation mode of the digital phase shift circuit Y includes a low-delay mode in which only the first electronic switch 7a and the second electronic switch 7b are set to the on state by the switch controller 8 and a high-delay mode in which only the fourth electronic switch 7d is set to the on state by the switch controller 8.
In the low-delay mode, the switch controller 8 sets the first electronic switch 7a and the second electronic switch 7b to the on state and sets the fourth electronic switch 7d to the off state. That is, in the low-delay mode, a first phase difference θL which is less than a second phase difference θH in the high-delay mode is caused due to a first transmission delay time TL, in a period until a high-frequency signal is transmitted from the input end (the other end) of the signal line 1 to the output end (the one end) thereof.
Specifically, in the low-delay mode, when the first electronic switch 7a is set to the on state, the other end of the first inner line za is connected to the second grounding conductor 4b. That is, since one end of the first inner line za is normally connected to the first grounding conductor 4a via the first connection conductor 6a, when the other end of the first inner line za is connected to the second grounding conductor 4b via the first electronic switch 7a, a first current path in which a current can flow between the one end and the other end of the first inner line za is formed.
On the other hand, when the second electronic switch 7b is set to the on state, the other end of the second inner line zb is connected to the second grounding conductor 4b. That is, since one end of the second inner line zb is normally connected to the first grounding conductor 4a via the second connection conductor 6b, when the other end of the second inner line zb is connected to the second grounding conductor 4b via the second electronic switch 7b, a second current path in which a current can flow between the one end and the other end of the second inner line zb is formed.
When a signal current flows from the input end to the output end of the signal line 1 in a state in which the one end of a first inner line za and the other end of another first inner line za are connected and the one end of a second inner line zb and the other end of another second inner line zb are connected, return currents of the signal current flow from the one ends to the other ends of the first inner line za and the second inner line zb due to transmission of the signal current.
That is, in the first inner line za constituting the first current path, a first return current in a direction opposite to the flowing direction of the signal current flows due to flowing of the signal current in the signal line 1. In the second inner line zb constituting the second current path, a second return current in a direction opposite to the flowing direction of the signal current, that is, in the same direction as the first return current, flows due to flowing of the signal current in the signal line 1.
Here, the first return current flowing in the first inner line za and the second return current flowing in the second inner line zb are both opposite to the flowing direction of the signal current. Accordingly, the first return current and the second return current operate to decrease the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first inner line za and the second inner line zb. When a decrease of the inductance L1 is defined as ΔLs, an effective inductance Lm of the signal line 1 is (L1−ΔLs).
The signal line 1 has the capacitance C1 which is a parasitic capacitance as described above. In the low-delay mode, since the fourth electronic switch 7d is set to the off state, the capacitor 5 is not connected between the signal line 1 and the second grounding conductor 4b. That is, the capacitance Ca of the capacitor 5 does not affect the high-frequency signal being transmitted in the signal line 1. Accordingly, the first transmission delay time TL which is proportional to (Lm×C1)1/2 acts on the high-frequency signal being transmitted in the signal line 1.
The high-frequency signal at the output end (the one end) of the signal line 1 is delayed in phase by the first phase difference θL from the high-frequency signal at the input end (the other end) of the signal line 1 due to the first transmission delay time TL. That is, in the low-delay mode, since the inductance L1 of the signal line 1 is decreased to the inductance Lm due to the first return current and the second return current, the original transmission delay time of the signal line 1 is decreased and as a result, the first phase difference θL which is less than the original phase difference of the signal line 1 is realized.
In the low-delay mode, a loss in the signal line 1 is intentionally increased by setting the third electronic switch 7c to the on state. This setting of a loss is used for the output amplitude of a high-frequency signal in the low-delay mode to approach the output amplitude in the high-delay mode. The third electronic switch 7e is not an essential component and may be omitted.
That is, the loss of a high-frequency signal in the low-delay mode is apparently less than the loss of a high-frequency signal in the high-delay mode. This loss difference causes an amplitude difference between high-frequency signals output from the digital phase shift circuits Y when the operation mode is switched between the low-delay mode and the high-delay mode. With these circumstances, the amplitude difference is resolved by setting the third electronic switch 7e to the on state during the low-delay mode in the digital phase shift circuits Y.
On the other hand, in the high-delay mode, the switch controller 8 sets the first electronic switch 7a, the second electronic switch 7b, and the third electronic switch 7c to the off state and sets the fourth electronic switch 7d to the on state. That is, in the high-delay mode, a second phase difference θH which is greater than the first phase difference θL in the low-delay mode is caused due to a second transmission delay time TH in a period until a high-frequency signal is transmitted from the input end (the other end) of the signal line 1 to the output end (the one end).
In the high-delay mode, since the first electronic switch 7a and the second electronic switch 7b are set to the off state, a first current path is not formed in the first inner line za, and a second current path is not formed in the second inner line zb. Accordingly, the first return current in the first inner line za becomes much smaller and the second return current in the second inner line zb becomes much smaller.
On the other hand, one end of the first output line 3a is connected to the first grounding conductor da via the third connection conductor 6c and the other end thereof is connected to the second grounding conductor 4b via the fourth connection conductor 6d. That is, a third current path in which a current can flow between the one end and the other end of the first output line 3a is formed in advance in the first outer line 3a.
Accordingly, in the high-delay mode, a third return current flows from the one end of the first outer line 3a to the other end thereof due to a signal current in the signal line 1. The third return current flows in a direction opposite to the flowing direction of the signal current in the signal line 1. Accordingly, the third return current can decrease the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the first outer line 3a.
One end of the second outer line 3b is connected to the first grounding conductor 4a via the fifth connection conductor 6e and the other end thereof is connected to the second grounding conductor 4b via the sixth connection conductor 6f. That is, a fourth current path in which a current can flow between the one end and the other end of the first output line 3a is formed in advance in the second outer line 3b.
Accordingly, in the high-delay mode, a fourth return current flows from the one end of the second outer line 3b to the other end thereof due to the signal current in the signal line 1. The fourth return current flows in a direction opposite to the flowing direction of the signal current in the signal line 1. Accordingly, the fourth return current can decrease the inductance L1 of the signal line 1 due to electromagnetic coupling between the signal line 1 and the second outer line 3b.
Here, the distance between the signal line 1 and the first outer line 3a and the second outer line 3b is larger than the distance between the signal line 1 and the first inner line za and the second inner line zb. Accordingly, the third return current and the fourth return current have a weaker effect of decreasing the inductance L1 than the first return current and the second return current. When a decrease in the inductance L1 due to the third return current and the fourth return current is defined as ΔLh, an effective inductance Lp of the signal line 1 is (L1−ΔLh).
On the other hand, the signal line 1 has the capacitance C1 which is a parasitic capacitance. In the high-delay mode, since the fourth electronic switch 7d is set to the on state, the capacitor 5 is connected between the signal line 1 and the second grounding conductor 4b. That is, the signal line 1 has a capacitance Cb which is a sum of the capacitance Ca and the capacitance C1 (the parasitic capacitance) of the capacitor 5. Accordingly, the second transmission delay time TH which is proportional to (Lp×Cb)1/2 acts on the high-frequency signal being transmitted in the signal line 1.
The high-frequency signal at the output end of the signal line 1 is delayed in phase by the second phase difference θH from the high-frequency signal at the input end of the signal line 1 due to the second transmission delay time TH. That is, in the high-delay mode, since the inductance L1 of the signal line 1 is more weakly decreased to an inductance Ln due to the third return current and the fourth return current and the fourth electronic switch 7d is set to the on state, the second phase difference θH which is greater than the first phase difference θL in the low-delay mode is realized.
In the high-delay mode, the third electronic switch 7e may be set to the off state. That is, in the high-delay mode, a process of intentionally increasing the loss in the signal line 1 is not performed. As a result, the loss applied to the high-frequency signal in the high-delay mode is substantially the same as the loss applied to the high-frequency signal in the low-delay mode.
In the digital phase shifter A1 in which the eight digital phase shift circuits Y1 to Y8 are linearly arranged, the flowing path of the return current changes variously according to the set state of the operation mode in the digital phase shift circuits Y1 to Y8. For example,
That is, in this case, the first return current R1 flows in the order of the first output-grounding line z2 and the first extension-grounding line z4→the first grounding conductor 4a in the eighth digital phase shift circuit Y8→the first outer line 3a in the eighth digital phase shift circuit Y8→the second grounding conductor 4b in the eighth digital phase shift circuit Y8→the first inner line za in the seventh digital phase shift circuit Y7→(omission)→the first inner line za in the first digital phase shift circuit Y1→the first input-grounding line x2 in the input circuit X.
The second return current R2 flows in the order of the second output-grounding line z3 and the second extension-grounding line z5→the first grounding conductor 4a in the eighth digital phase shift circuit Y8→the second outer line 3b in the eighth digital phase shift circuit Y8→the second grounding conductor 4b in the eighth digital phase shift circuit Y8→the second inner line zb in the seventh digital phase shift circuit Y7→(omission)→the second inner line zb in the first digital phase shift circuit Y1→the second input-grounding line x3 in the input circuit X.
Here, since the first extension-grounding line z4 and the second extension-grounding line z5 are provided in the output circuit 7, the current path for the first return current R1 and the second return current R2 flowing in the output circuit Z is broader by the width W of the first extension-grounding line z4 and the second extension-grounding line z5 than that when only the first output-grounding line z2 and the second output-grounding line z3 are provided therein.
On the other hand.
In this case, the second return current R2′ flows in the order of the second output-grounding line z3→the second inner line zb in the eighth digital phase shift circuit Y8→the second inner line zb in the seventh digital phase shift circuit Y7→(omission)→the second inner line zb in the first digital phase shift circuit Y1→the second input-grounding line x3 in the input circuit X.
In the digital phase shifter A1 according to the first embodiment, since the first extension-grounding line z4 and the second extension-grounding line z5 are provided in the output circuit Z, change of the path of the return current in the eighth digital phase shift circuit Y8 is moderated. That is, since the first extension-grounding line z4 is a grounding line connecting the first grounding conductor 4a and the first output-grounding line z2 in the eighth digital phase shift circuit Ys, it operates to shorten the path of the first return current R1 in an area surrounded by a two-dot chain line in
Since the second extension-grounding line z5 is a grounding line connecting the first grounding conductor 4a and the second output-grounding line z3 in the eighth digital phase shift circuit Ys, it operates to shorten the path of the second return current R2 in an area surrounded by a two-dot chain line in
With the digital phase shifter A1 according to the first embodiment, it is possible to improve evenness in the phase shift quantity of the eighth digital phase shift circuit Y8 (the uneven digital phase shift circuit) with respect to the other digital phase shift circuits Y1 to Y7. That is, according to the first embodiment, it is possible to provide the digital phase shifter A1 that can more evenly change the phase shift quantities of the eight digital phase shift circuits Y1 to Y8.
A second embodiment of the present invention will be described below with reference to
That is, the first modified digital phase shift circuit aY8 satisfies a condition that a length (the length of two outer lines 3a and 3b and the like, that is, the length in the cascade connection direction) Pa thereof is less than a length P of the other digital phase shift circuits Y1 to Y7. The first modified digital phase shift circuit aY8 serves as a phase shift quantity moderator that moderates unevenness in phase shift quantity of the eighth digital phase shift circuit Y8 in the first embodiment with respect to the other digital phase shift circuits Y1 to Y7.
The modified output circuit 7′ has a configuration in which two extension-grounding lines z4 and z5 are removed from the output circuit Z according to the first embodiment. That is, the digital phase shifter A2 according to the second embodiment employs the first modified digital phase shift circuit aY8 instead of the two extension-grounding lines z4 and z5 in the first embodiment as the phase shift quantity moderator.
As described above in the first embodiment, the change in path of the return current in the eighth digital phase shift circuit Y8 causes the phase shift quantity when the high-delay mode in the eighth digital phase shift circuit Y8 is switched to the low-delay mode to become greater than the phase shift quantity when the high-delay mode in the other digital phase shift circuits Y1 to Y7 is switched to the low-delay mode. The length Pa of the first modified digital phase shift circuit aY8 (the uneven digital phase shift circuit) with respect to the length P of the other digital phase shift circuits Y1 to Y7 is set such that the phase shift quantity when the high-delay mode in the first modified digital phase shift circuit aY8 is switched to the low-delay mode becomes equal to the phase shift quantity when the high-delay mode in the other digital phase shift circuits Y1 to Y7 is switched to the low-delay mode.
Here, when the length Pa of the two outer lines 3a and 3b is set to be less than the length P of the two outer lines 3a and 3b in the other digital phase shift circuits Y1 to Y7, the length of the two inner lines 2a and 2b is shortened similarly to the length Pa of the two outer lines 3a and 3b. By shortening the length of the two inner lines 2a and 2b, the length of the eighth digital phase shift circuit Y8 is decreased and a phase difference between the low-delay mode and the high-delay mode in a unit cell is decreased.
The most important performance of a digital phase shifter is a difference (phase) between the phase shift quantity in the low-delay mode and the phase shift quantity in the high-delay mode. The first modified digital phase shift circuit aY8 (the uneven digital phase shift circuit) in the second embodiment has a function of reducing both the phase shift quantity in the low-delay mode and the phase shift quantity in the high-delay mode and thus the phase difference thereof is the same as in the other digital phase shift circuits Y1 to Y7.
With the digital phase shifter A2 according to the second embodiment, it is possible to further improve evenness in the phase shift quantity of the first modified digital phase shift circuit a Y8 (the uneven digital phase shift circuit) with respect to the other digital phase shift circuits Y1 to Y7 than in the digital phase shifter A1 according to the first embodiment. That is, according to the second embodiment, it is possible to provide the digital phase shifter A2 that can further improve evenness in the phase shift quantity of the eight digital phase shift circuits Y1 to Y8 than in the digital phase shifter A1.
A third embodiment of the present invention will be described below with reference to
The second modified digital phase shift circuit bY8 satisfies a condition that a distance Qa of the two inner lines 2a and 2b from the signal line 1 (a distance Qa in the width direction) is greater than a distance Q of the two inner lines 2a and 2b from the signal line 1 in the other digital phase shift circuits Y1 to Y7 as shown in the drawing. In the second modified digital phase shift circuit bY8, the phase shift quantity in the low-delay mode is increased such that a difference (a phase difference) between the phase in the high-delay mode and the phase in the low-delay mode is equal to the phase shift quantity in the other digital phase shift circuits Y1 to Y7.
The second modified digital phase shift circuit bY8 (the uneven digital phase shift circuit) serves as a phase shift quantity moderator that moderates unevenness in phase shift quantity of the eighth digital phase shift circuit Y8 in the first embodiment with respect to the other digital phase shift circuits Y1 to Y7. That is, the digital phase shifter A4 according to the fourth embodiment employs the third modified digital phase shift circuit cY8 as the phase shift quantity moderator.
The modified output circuit Z′ has a configuration in which two extension-grounding lines z4 and z5 are removed from the output circuit Z according to the first embodiment. That is, the digital phase shifter A3 according to the third embodiment employs the second modified digital phase shift circuit bY8 instead of the two extension-grounding lines 24 and 25 in the first embodiment. The modified output circuit Z′ may include an extension-grounding line corresponding to the two extension-grounding lines 24 and z5 in the output circuit Z.
With the digital phase shifter A3 according to the third embodiment, it is possible to further improve evenness in the phase shift quantity of the second modified digital phase shift circuit bY8 (the uneven digital phase shift circuit) with respect to the other digital phase shift circuits Y1 to Y7 than in the digital phase shifter A1 according to the first embodiment. That is, according to the third embodiment, it is possible to provide the digital phase shifter A3 that can further improve evenness in the phase shift quantity of the eight digital phase shift circuits Y1 to Y8 than in the digital phase shifter A1.
A fourth embodiment of the present invention will be described below with reference to
The third modified digital phase shift circuit cY8 satisfies a condition that a distance Sa of the two outer lines 3a and 3b from the signal line 1 (a distance Sa in the width direction) is less than a distance S of the two outer lines 3a and 3b from the signal line 1 in the other digital phase shift circuits Y1 to Y7 as shown in the drawing. In the third modified digital phase shift circuit cY8, the phase shift quantity in the high-delay mode is decreased such that a difference (a phase difference) between the phase in the high-delay mode and the phase in the low-delay mode is equal to the phase shift quantity in the other digital phase shift circuits Y1 to Y7.
The third modified digital phase shift circuit cY8 (the uneven digital phase shift circuit) serves as a phase shift quantity moderator that moderates unevenness in phase shift quantity of the eighth digital phase shift circuit Y8 in the first embodiment with respect to the other digital phase shift circuits Y1 to Y7. That is, the digital phase shifter A4 according to the fourth embodiment employs the third modified digital phase shift circuit cY8 as the phase shift quantity moderator.
The modified output circuit Z′ has a configuration in which two extension-grounding lines z4 and z5 are removed from the output circuit Z according to the first embodiment. That is, the digital phase shifter A4 according to the fourth embodiment employs the third modified digital phase shift circuit cY8 instead of the two extension-grounding lines z4 and z5 in the first embodiment. The modified output circuit Z′ may include an extension-grounding line corresponding to the two extension-grounding lines z4 and z5 in the output circuit Z.
With the digital phase shifter A4 according to the fourth embodiment, it is possible to further improve evenness in the phase shift quantity of the third modified digital phase shift circuit cY8 (the uneven digital phase shift circuit) with respect to the other digital phase shift circuits Y1 to Y7 than in the digital phase shifter A1 according to the first embodiment. That is, according to the fourth embodiment, it is possible to provide the digital phase shifter A4 that can further improve evenness in the phase shift quantity of the eight digital phase shift circuits Y1 to Y8 than in the digital phase shifter A1.
Here, the second to fourth embodiments respectively employ the first modified digital phase shift circuit aY8, the second modified digital phase shift circuit bY8, and the third modified digital phase shift circuit cY8 instead of the two extension-grounding lines z4 and z5 in the first embodiment. That is, in the second to fourth embodiments, the phase shift quantity moderator satisfies one of a condition that the length (the length of the outer lines 3a and 3b or the like) Pa of the uneven digital phase shift circuit is less than the length P in the other digital phase shift circuits Y1 to Y7, a condition that the distance Qa between the signal line 1 and each of the inner lines 2a and 2b of the uneven digital phase shift circuit is greater than the distance Q in the other digital phase shift circuits Y1 to Y7, and a condition that the distance Sa between the signal line 1 and each of the outer lines 3a and 3b of the uneven digital phase shift circuit is less than the distance S in the other digital phase shift circuits Y1 to Y7.
As conditions associated with an uneven digital phase shift circuit for causing the phase of the uneven digital phase shift circuit to approach the phases of the other digital phase shift circuits Y1 to Y7, a condition that a capacitance of the capacitor 5 in the most downstream digital phase shift circuit is less than the capacitance of the capacitor 5 in the other digital phase shift circuits Y1 to Y7 and a condition that the first electronic switch 7a and the second electronic switch 7b in the uneven digital phase shift circuit are smaller than the first electronic switch 7a and the second electronic switch 7b in the other digital phase shift circuits Y1 to Y7 are conceivable in addition to the aforementioned three conditions.
That is, it is possible to reduce the phase shift quantity in the high-delay mode by employing the condition that the capacitance of the capacitor 5 in the uneven digital phase shift circuit is less than the capacitance of the capacitor 5 in the other digital phase shift circuits Y1 to Y7. It is possible to increase the phase shift quantity in the low-delay mode by employing the condition that the first electronic switch 7a and the second electronic switch 7b in the uneven digital phase shift circuit are smaller than the first electronic switch 7a and the second electronic switch 7b in the other digital phase shift circuits Y1 to Y7.
Accordingly, it is possible to improve evenness in phase shift quantity of the uneven digital phase shift circuit with respect to that in the other digital phase shift circuits Y1 to Y7 using the condition associated with the capacitor 5 in the uneven digital phase shift circuit or the condition associated with the first electronic switch 7a and the second electronic switch 7b in the uneven digital phase shift circuit.
By combining the aforementioned three conditions, a change in phase difference due to a change of the path of the return current in the uneven digital phase shift circuit may be cancelled. That is, the phase shift quantity moderator in the present invention may satisfy at least one of the condition that the length (the length of the outer lines 3a and 3b or the like) Pa of the uneven digital phase shift circuit is less than the length P in the other digital phase shift circuits Y1 to Y7, the condition that the distance Qa between the signal line 1 and each of the inner lines 2a and 2b in the uneven digital phase shift circuit is greater than the distance Q in the other digital phase shift circuits Y1 to Y7, and the condition that the distance Sa between the signal line 1 and each of the outer lines 3a and 3b in the uneven digital phase shift circuit is less than the distance S in the other digital phase shift circuits Y1 to Y7.
By combining the aforementioned five conditions, a change in phase difference due to a change of the path of the return current in the uneven digital phase shift circuit may be cancelled. That is, an uneven digital phase shift circuit satisfying at least one of the condition that the length (the length of the outer lines 3a and 3b or the like) Pa of the most downstream digital phase shift circuit is less than the length P in the other digital phase shift circuits Y1 to Y7, the condition that the distance Qa between the signal line 1 and each of the inner lines 2a and 2b in the uneven digital phase shift circuit is greater than the distance Q in the other digital phase shift circuits Y1 to Y7, the condition that the distance Sa between the signal line 1 and each of the outer lines 3a and 3b in the uneven digital phase shift circuit is less than the distance S in the other digital phase shift circuits Y1 to Y7, the condition associated with the capacitor 5 in the uneven digital phase shift circuit, and the condition associated with the first electronic switch 7a and the second electronic switch 7b in the uneven digital phase shift circuit may be employed as the phase shift quantity moderator.
In the aforementioned embodiments, an example in which the most downstream digital phase shift circuit (the eighth digital phase shift circuit Y8) which is located most downstream in the transmission direction of a high-frequency signal serves as an uneven digital phase shift circuit has been described. However, the uneven digital phase shift circuit in the present invention is not limited to the most downstream digital phase shift circuit.
One of the other digital phase shift circuits Y1 to Y7 may serve as an uneven digital phase shift circuit depending on the method of setting the high-delay mode and the low-delay mode in the eight-stage digital phase shift circuits Y1 to Y8. For example, when the first digital phase shift circuit Y; is an uneven digital phase shift circuit, a phase shift quantity moderator corresponding to the first extension-grounding line z4 and the second extension-grounding line z5 in the first embodiment may be provided in the input circuit X or the shape of the first digital phase shift circuit Y1 is modified as described above in the second to fourth embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-024000 | Feb 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/030132 | 8/5/2022 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2023/157339 | 8/24/2023 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6816031 | Miller | Nov 2004 | B1 |
| 11979129 | Lardizabal | May 2024 | B2 |
| 20140312986 | Edelstein et al. | Oct 2014 | A1 |
| 20190158068 | Valdes Garcia et al. | May 2019 | A1 |
| 20230420815 | Uemichi | Dec 2023 | A1 |
| Number | Date | Country |
|---|---|---|
| 106785250 | May 2017 | CN |
| 109616723 | Apr 2019 | CN |
| 111326839 | Jun 2020 | CN |
| 2011-259215 | Dec 2011 | JP |
| 2013-98744 | May 2013 | JP |
| 2016-158035 | Sep 2016 | JP |
| Entry |
|---|
| W/Japanese International Search Report dated Oct. 4, 2022, issued in counterpart International Application No. PCT/JP2022/030132. (3 pages). |
| Tousi et al., “A Ka-band Digitally-Controlled Phase Shifter with sub-degree Phase Precision”, 2016 IEEE Radio Frequency Integrated Circuits Symposium, pp. 356-359. Cited in Specification. (4 pages). |
