BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power converter, and particularly relates to a digital control circuit with embedded microcontroller for a power converter.
2. Background of the Invention
A power converter is an electrical or electro-mechanical device for converting electrical energy from one form to another, i.e., converting between AC and DC, or just changing the voltage or frequency, or some combination of these. The power converter could be as simple as a transformer to change the voltage of AC power, but also includes far more complex systems. Nowadays, the power converter are required for microcontrollers to achieve less energy losses, a better performance and complete protections.
SUMMARY OF THE INVENTION
The present invention provides a control circuit for a power converter. The control circuit comprises a microcontroller, an oscillation circuit, an analog-to-digital converter and a signal generator. The microcontroller comprises a flash memory. The oscillation circuit comprises a phase lock loop for generating a clock signal. The analog-to-digital converter is coupled to an output of the power converter and generates a digital feedback signal for the microcontroller. The signal generator is configured to receive the clock signal and a data of the microcontroller for generating a switching signal. The microcontroller controls the switching signal, and the switching signal is configured to switch a transformer for regulating the output of the power converter.
From another point of view, the present invention further provides a digital power control circuit for a power converter. The digital power control circuit comprises a microcontroller, an oscillation circuit, a signal detection circuit and a signal generator. The microcontroller includes a flash memory. The oscillation circuit includes a phase lock loop for generating a clock signal. The signal detection circuit is coupled to an output of the power converter, and is configured to generate a feedback signal. The signal generator is configured to receive the clock signal and the feedback signal for generating a switching signal. The microcontroller controls the switching signal, and the switching signal is configured to switch a transformer for regulating the output of the power converter.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 shows a schematic view illustrating one embodiment of a power converter according to the present invention.
FIG. 2A shows waveforms of the switching signals OA and OB according to the present invention.
FIG. 2B shows waveforms of the switching signals OA, OB and signals DET1, PWM1 according to the present invention.
FIG. 3 shows a block diagram illustrating one embodiment of a controller according to the present invention.
FIG. 4 shows a block diagram illustrating one embodiment of a signal generator according to the present invention.
FIG. 5 shows a circuit diagram illustrating one embodiment of a PWM circuit according to the present invention.
FIG. 6 shows a circuit diagram illustrating one embodiment of a PWM signal generator according to the present invention.
FIG. 7 shows a circuit diagram illustrating one embodiment of a protection circuit according to the present invention.
FIG. 8 shows a circuit diagram illustrating one embodiment of a signal detection circuit according to the present invention.
FIG. 9 shows waveforms of the switching signals OA, OB and switching current IP according to the present invention.
FIG. 10 shows a block diagram illustrating one embodiment of an oscillation circuit according to the present invention.
FIG. 11 shows a circuit diagram illustrating one embodiment of a reference signal generator according to the present invention.
DETAILED DESCRIPTION OF EMBODIMENTS
The present invention of described embodiments below provides a digital control circuit with embedded microcontroller for a power converter. The digital control circuit reduces the loading of a microcontroller and provides a real time operation to achieve a better performance and complete protections.
FIG. 1 shows a schematic view illustrating one embodiment of a power converter according to the present invention. Transistors 20 and 25 switch a transformer 10 through a capacitor 30 and an inductor 35. In FIG. 1, the drain of the transistor 20 receives an input voltage VIN. The capacitor 30 and the inductor 35 develop a resonant tank. The inductor 35 may represent as a part of the transformer 10, such as leakage inductance of the transformer 10. The secondary windings of the transformer 10 generate the output voltage VO at a capacitor 40 via rectifiers 55 and 65. Transistors 50 and 60 are connected to the rectifier 55 and 65 respectively for the synchronous rectifying. The rectifiers 55 and 65 may be the body diode of the transistors 50 and 60 respectively. According to the output voltage VO, resistors 71 and 72 form a voltage divider for generating a feedback signal VFB coupled to a controller 100. In accordance with the feedback signal VFB, the controller 100 generated switching signals OA, OB coupled to control the transistors 20, 25 through a driver transformer 15. The frequency of the switching signals OA, OB will determine an output power of the resonant power converter.
A diode 45 is connected to the rectifier 55 for generating a signal DET1 coupled the controller 100. A diode 46 is connected to the rectifier 65 for generating a signal DET2 coupled the controller 100. When the transistor 50 is off, a pulled-low state of the signal DET1 indicates that the rectifier 55 is still turned on. According to the state of the switching signals OA, OB and/or the signals DET1, DET2, the controller 100 generates signals PWM1 and PWM2 to control the synchronous rectifying transistors 50 and 60 respectively.
A current transformer 19 coupled to the transformer 10 detects a switching current Ip of the transformer 10 and generates a current signal VCS via a high speed bridge-rectifier 80 and a resistor 81 through signals X and Y. Through a resistor 85 and a capacitor 86, a current signal VOI is further generated in accordance with the current signal VCS for the over-current protection. The current signals VCS and VOI are coupled to the controller 100. A signal VOV is further coupled to the controller 100 for the over-voltage protection. The level of the signal VOV is correlated to the level of the output voltage VO.
FIG. 2A shows waveforms of the switching signals OA and OB according to the present invention. The on-time period of the switching signal OA is represented as TA. The on-time period of the switching signal OB is represented as TB. TD is the dead-time period in between the switching signals OA and OB. The frequency, the duty-cycle and the pulse width of the switching signals OA and OB may be programmable through timers.
FIG. 2B shows waveforms of the switching signals OA, OB and signals DET1, PWM1 according to the present invention. When the switching signal OA is “pulled-high and/or the signal DET1 is “pulled-low”, then the signal PWM1 will be generated to turn on the transistor 50 for the synchronous rectifying. The TDB is a de-bounce time period provided to assure that the signal DET has been pulled low. The pulse width TPWM of the signal PWM1 is programmable by a timer. Another timer will record the timing TR that starts from “the turn-off of the signal PWM1” to “the pulled-high of the signal DET1”. It means the timing TR records the period from “the turn-off of the transistor 50” to “the turn-off of the rectifier 55”. The timing TR is utilized to program the pulse width TPWM for optimizing the synchronous rectifying.
FIG. 3 shows a block diagram illustrating one embodiment of the controller 100 according to the present invention. The controller 100 includes a microcontroller (MCU) 110 having a flash memory 112. The flash memory 112 includes a program memory, a data memory and a calibration memory. An oscillation circuit (OSC) 500 generates a clock signal CK. A reference signal generator (REF) 600 generates reference signals such as VREF, VTN, etc. The calibration memory of the flash memory 112 is configured to calibrate the outputs of the oscillation circuit 500 and the reference signal generator 600. After the power on, the data SFLH of calibration memory of the flash memory 112 will be stored into the oscillation circuit 500 and the reference signal generator 600. For instance, the controller 100 is an IC (integration circuit). The calibration memory is programmed into the flash memory 112 during the mass production of the controller 100.
Through the data bus DB, the microcontroller 110 controls a signal generator 150 to generate the switching signals OA, OB and an interrupt signal INT. The interrupt signal INT is configured to interrupt the microcontroller 110 in response to the falling edge of the switching signals OA, OB. A PWM circuit 200 is coupled to generate the signals PWM1, PWM2 in response to the switching signals OA, OB and/or the signals DET1, DET2. The pulse width of the signals PWM1, PWM2 is programmable by the microcontroller 110. A protection circuit (PROTECTION) 300 generates a reset signal RST configured to turn-off the switching signals OA, OB and signals PWM1, PWM2 when the signal VOV is over a threshold, the signal VOI is over another threshold or a watchdog timer is overflow. A signal detection circuit (SIGNAL DETECTION) 350 is configured to convert the feedback signal VFB, the current signals VCS and VOI to the digital data for the microcontroller 110.
FIG. 4 shows a block diagram illustrating one embodiment of a signal generator 150 according to the present invention. The signal generator 150 includes a timer-A 160 for determining the period of on-time TA of the switching signal OA (shown in FIG. 2A), a timer-B 170 for determining the period of on-time TB of the switching signal OB, and a timer-D 180 for determining the period of dead-time TD. For instance, the timer-A 160 and the timer-B 170 are 16-bit length, and the timer-A 160 and timer-B 170 can be programmed through the data bus DB. The timer-D 180 is 8-bit length, and the timer-D 180 also can be programmed through the data bus DB. The outputs of the timer-A 160, the timer-B 170 and the timer-D 180 are coupled to a logic circuit 190 to generate the switching signals OA, OB via AND gates 191 and 192 by signals SA, SB, SD, EN—a, EN—b and EN—d. The reset signal RST is also connected to the AND gates 191 and 192. The interrupt signal INT can be generated through a pulse generation circuit 195 corresponding to falling edges of the switching signal OA and OB.
FIG. 5 shows a circuit diagram illustrating one embodiment of a PWM circuit 200 according to the present invention. The PWM circuit 200 includes a PWM signal generator 230 for generating the signals PWM1 and PWM2 in response to the switching signals OA, OB and/or signals DET1, DET2. The PWM signal generator 230 also generates trigger signals SD1, SD2. The trigger signals SD1, SD2 are correlated to the signals DET1, DET2. The timer (TR1) 210 receives the signals PWM1 through inverter 211, and the timer (TR2) 220 receives the signals PWM2 through inverter 221. The timer 210 is configured to record the time period TR (shown in FIG. 2B) that begins from turning off of the signal PWM1 to the logic-low state of the trigger signal SD1 corresponding to the rising edge of the signal DET1. A timer 220 is configured to record the period (timing) TR (shown in FIG. 2B) that begins from turning off of the signal PWM2 to the logic-low state of the trigger signal SD2 corresponding to the rising edge of the signal DET2. The data of the timers 210 and 220 are stored in registers (REG) 215, 225 respectively. The microcontroller 110 may read the data of timers 210 and 220 (registers 215, 225) from the data bus DB.
FIG. 6 shows a circuit diagram illustrating one embodiment of a PWM signal generator 230 according to the present invention. The PWM signal generator 230 includes a comparator 231 coupled to receive the signal DET1. The comparator 231 will generate an output signal coupled to a de-bounce circuit 235 according to the comparison result of when the signal DET1 is higher or lower than a threshold VT1. The de-bounce circuit 235 will output a trigger signal SD1. The trigger signal SD1 and the switching signal OA are coupled to a flip-flop 237 via an AND gate 232. Through an AND gate 239, the output of the flip-flop 237 is applied to control an input signal for a PWM1 timer 250. The value of the PWM1 timer 250 is programmable by the microcontroller 110 through the data bus DB.
A comparator 241 is coupled to receive the signal DET2. The comparator 241 will generate an output signal coupled to a de-bounce circuit 245 according to the comparison result of when the signal DET2 is higher or lower than the threshold VT1. The de-bounce circuit 245 will output a trigger signal SD2. The trigger signal SD2 and the switching signal OB are coupled to a flip-flop 247 via an AND gate 222. Through an AND gate 249, the output of the flip-flop 247 is applied to control an input signal for a PWM2 timer 260. The value of the PWM2 timer 260 is programmable by the microcontroller 110 through the data bus DB.
The data of a register (PWM_REG) 270 is programmable by the microcontroller 110 via the data bus DB. When the clock signal CK is enabled for clocking the PWM1 timer 250, a start signal ST1 will be generated. A digital comparator 255 will be configured to compare the value of the PWM1 timer 250 and the value of register 270. When the value of the timer 250 and the value of register 270 are equal, the digital comparator 255 will generate a stop signal SO1. The stop signal SO1 is configured to reset the flip-flop 237 and stops the clock signal CK sent into the PWM1 timer 250. Both the start signal ST1 and the stop signal SO1 are configured to generate the signal PWM1 through a signal S2, a logic circuit 280 and an AND gate 281.
When the clock signal CK is enabled for clocking the PWM2 timer 260, a start signal ST2 will be generated. A digital comparator 265 will be configured to compare the value of the PWM2 timer 260 and the value of register 270. When the value of the PWM2 timer 260 and the value of register 270 are equal, the digital comparator 265 will generate a stop signal SO2. The stop signal SO2 is configured to reset the flip-flop 247 and stop the clock signal CK coupled to the PWM2 timer 260. Both the start signal ST2 and the stop signal SO2 are configured to generate the signal PWM2 through signal S1, the logic circuit 280 and an AND gate 282. The reset signal RST is coupled to AND gates 281 and 282 to turn off the signals PWM1 and PWM2 when the reset signal RST is enabled for the protection.
FIG. 7 shows a circuit diagram illustrating one embodiment of a protection circuit 300 according to the present invention. A comparator 310 is configured to receive the signal VOV, and the comparator 310 generates an output signal to a de-bounce circuit 315 when the signal VOV is over a threshold VT2. A comparator 311 is configured to receive the signal VOI, and generate an output signal to a de-bounce circuit 316 when the signal VOI is over a threshold VT4. The output of the de-bounce circuits 315, 316 are coupled to a flip-flop 325 via an OR gate 335 for generating the reset signal RST. Another input of the OR gate 335 is an overflow signal OVF. A watchdog timer (WDT) 330 generates the overflow signal OVF. The watchdog timer 330 is controlled by the microcontroller 110 though the data bus DB. When the protection is happened by the signal VOV, VOI or the watchdog timer 330, the protection state and the reset signal RST will be latched by the flip-flop 325. Only the microcontroller 110 can clear the flip-flop 325 via the data bus DB, a decoder 340 and an inverter 345.
FIG. 8 shows a circuit diagram illustrating one embodiment of a signal detection circuit 350 according to the present invention. A decoder 370 coupled to the data bus DB generates the signals to control a multiplexer (MUX) 360, a sample-and-hold circuit (S/H) 362 and an analog-to-digital converter (A/D) 365. The maximum value of the analog-to-digital converter 365 is scaled by the reference signal VREF. The microcontroller 110 of FIG. 3 can read the output of the analog-to-digital converter 365 through the data bus DB. The multiplexer 360 is configured to receive the feedback signal VFB, the current signals VOI and VCS. Therefore, the microcontroller 110 can read the information of the feedback signal VFB (the feedback data), the current signals VOI and VCS.
FIG. 9 shows waveforms of the switching signals OA, OB and switching current IP according to the present invention. Refer to FIG. 1 and FIG. 9, the switching current IP is the current flows through the transformer 10 and the current transformer 19 of FIG. 1. The switching current IP can be converted to the signal VCS. By measuring the current signal VCS (through the signal detection circuit 350) in response to the interrupt signal INT (the falling edge of the switching signals OA, OB), the microcontroller 110 can detect the signal level of ΔI. The signal level of ΔI indicates the margin of the switching current IP before it falls to zero current. The level of ΔI is utilized to ensure the switching of the transistors 20 and 30 achieving ZVS (zero voltage switching). It also can make sure the resonant switching can be operated in inductive-mode. The level of ΔI also indicates the lowest switching frequency that is allowed for controlling the resonant power converter.
FIG. 10 shows a block diagram illustrating one embodiment of an oscillation circuit 500 according to the present invention. The oscillation circuit 500 includes an oscillator (OSC) 510 generating an oscillation signal F0. The frequency of the oscillation signal F0 is determined by the reference signal VREF, a trim-data signal W1 and a frequency selection signal WA. A register (REG) 511 is utilized to store the trim-data signal W1 by signal STORE. The trim-data signal W1 is loaded from the data SFLH of calibration memory when the power is turned on. A register 512 is utilized to store the frequency selection signals WA and WB. The frequency selection signals WA and WB are loaded from the data bus DB of microcontroller 110. The oscillation signal F0 is further connected to a phase comparator 530 to compare with a divided-clock signal FN. An error signal SPX generated by the phase comparator 530 is coupled to a voltage-control-oscillator (VCO) 520 through a low-pass filter (LPF) 535. The voltage-control-oscillator (VCO) 520 generates the clock signal CK. The clock signal CK is further coupled to a counter 525 for generating the divided-clock signal FN. The voltage-control-oscillator 520, the counter 525, the phase comparator 530 and the low-pass filter 535 develop a phase lock loop (PLL) for generating the clock signal CK in accordance with the oscillation signal F0. The frequency of the clock signal is programmable by the trim-data signal W1 and the frequency selection signals WA, WB.
FIG. 11 shows a circuit diagram illustrating one embodiment of a reference signal generator 600 according to the present invention. The reference signal generator 600 includes a bandgap 610 generating a bandgap voltage VBG. The bandgap voltage VBG is operated as a full scale voltage of a digital-to-analog converter (DAC) 620. The digital-to-analog converter 620 generates the reference signal VREF and the threshold signals VTN. VT0 in accordance with the bandgap voltage VBG and the data of a register (REG) 630. The data of the register 630 is loaded from the data SFLH of calibration memory when the power is turned on. Therefore, the reference signal VREF and the threshold signals VTN . . . VT0 can be precisely produced.
Although the present invention and the advantages thereof have been described in detail, it should be understood that various changes, substitutions, and alternations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. That is, the discussion included in this invention is intended to serve as a basic description. It should be understood that the specific discussion may not explicitly describe all embodiments possible; many alternatives are implicit. The generic nature of the invention may not fully explained and may not explicitly show that how each feature or element can actually be representative of a broader function or of a great variety of alternative or equivalent elements. Again, these are implicitly included in this disclosure. Neither the description nor the terminology is intended to limit the scope of the claims.
Patent Application
20130329464
