Claims
- 1. A method of operating a processor, the processor including a CPU having an ALU and a register set, the register set being accessed by said ALU by first and second internal buses, and said processor including a memory, said CPU having repetitive machine cycles and being operated by microinstructions, comprising the steps of:
- a) executing a first series of instructions in said CPU using a number of temporary registers in said register set of the CPU;
- b) upon occurrence of certain events requiring execution of a second series of instructions different from said first series, followed by execution of a return to said first series, determining the magnitude of said number of temporary registers, by operation of a single one of said microinstructions, by
- in every one of said machine cycles when said CPU is not stalled;
- loading onto said first internal bus of said CPU a binary bit mask defining said temporary registers to be saved, and
- converting said binary bit mask of the temporary registers to be saved by a counter logic circuit in said CPU to a value, said value being a multiple of the number of bits in said binary bit mask; then
- in response to a selected single one of said microinstructions, loading said value from said counter onto said second internal bus of said CPU in the same machine cycle as said steps of loading a bit mask and converting said bit mask;
- c) and subsequently storing the contents of said number of temporary registers in memory in a number of locations determined by said value using an address generated in said ALU.
- 2. A method according to claim 1 wherein said certain events include execution of an instruction in the CPU which requires saving said number of temporary registers to a stack in said memory.
- 3. A method according to claim 3 wherein said certain event include CALL or RETURN instructions.
- 4. A method according to claim 1 including the step of testing said memory by said CPU to see if said number of locations is available and storing said contents only if said number of locations is available.
- 5. A method according to claim 4 wherein said memory used for said step of storing is a stack.
- 6. A digital processor comprising:
- a) a CPU with execution means for executing a first series of instructions in the CPU using a number of temporary registers of the CPU; wherein said CPU has repetitive machine cycles and is operated by microinstructions stored within said CPU; said execution means including an ALU and first and second internal buses providing inputs of said ALU; and means in said execution means for applying to said first internal bus a binary bit-mask representation indicating said number of temporary registers to be saved;
- b) a counter logic circuit in said CPU coupled to said first and second internal buses in said execution means for determining the magnitude of said
- b) upon occurrence of certain events requiring execution of a second series of instructions different from said first series, followed by execution of a return to said first series, determining the magnitude of said number of temporary registers, by operation of a single one of said microinstructions, by
- in every one of said machine cycles when said CPU is not stalled;
- loading onto said first internal bus of said CPU a binary bit mask defining said temporary registers to be saved, and
- converting said binary bit mask of the temporary registers to be saved by a counter logic circuit in said CPU to a value, said value being a multiple of the number of bits in said binary bit mask; then
- in response to a selected single one of said microinstructions, loading said value from said counter onto said second internal bus of said CPU in the same machine cycle as said steps of loading a bit mask and converting said bit mask;
- c) and subsequently storing the contents of said number of temporary registers in memory in a number of locations determined by said value using an address generated in said ALU.
- 7. A processor according to claim 6 wherein said means for storing activated upon occurance of an event
- 8. A processor according to claim 7 wherein said event is execution of an instruction in the CPU which requires saving said number of temporary registers to a stack in said memory.
- 9. A processor according to claim 8 wherein said instruction is a CALL instruction.
- 10. A processor according to claim 6 including means for testing said memory to see if said number of locations is available and wherein the memory access means stores said contents in said memory only if said number of locations is available.
- 11. A processor according to claim 10 wherein said memory used for said storing is a stack.
- 12. A processor according to claim 6 including means for probing said memory at locations determined by said value to find out if said locations are within prescribed bounds for said storing.
Parent Case Info
This is a continuation of Ser. No. 221925, filed Jul. 20, 1988, now abandoned.
US Referenced Citations (20)
Non-Patent Literature Citations (2)
Entry |
Mishra, "The VAX Microarchitecture", Digital Technical Journal, Feb. 1987, pp. 20-33. |
Troiani et al, "The VAX 8600 I Box, A Pipelined Implementation of the VAX Architecture", Digital Technical Journal, Aug. 1985, pp. 24-42. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
221925 |
Jul 1988 |
|