DIGITAL PROPORTIONAL INTEGRAL LOOP FILTER

Abstract

A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priorities of Korean Patent Application Nos. 10-2008-0124303 filed on Dec. 8, 2008, and 10-2009-0060619 filed on Jul. 3, 2009, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital proportional integral loop filter for fast settling time, and more particularly, to a digital proportional integral loop filter capable of changing a loop filter gain through one-time switching to thereby change a loop filter coefficient even with a great change in loop filter gain by generating offsets using a phase error average value and a phase error accumulation average value, and capable of locking to a single desired frequency at a time to thereby reduce settling time.

2. Description of the Related Art

A conventional analog phase locked loop (PLL) including a phase/frequency detector, a charge pump, and an RC loop filter has been replaced with an all-digital PLL (ADPLL) including a time-to-digital converter and a simple digital loop filter. This is because signal processing can be performed with a digital circuit capable of avoiding dependency on a fine voltage resolution of an analog circuit. A new technology for an ADPLL digital loop filter has been proposed which has rapid frequency acquisition time while maintaining superior phase noise characteristics and spurious performance by applying a digital signal processing scheme to a loop filter.

FIG. 1 illustrates a related art proportional loop filter 100 using a gear-shift scheme. The proportional loop filter 100 using the gear-shift scheme includes bit shifters 120 and 121, adders 140 and 143, and a multiplexer 150. The bit shifters 120 and 121 acts as a multiplier and a divider. The multiplexer 150 outputs a value 130 of α₁·φ_E[k] when a tracking mode control signal is 0, and outputs the sum of a value 131 of α₂·φ_E[k] and a value 142 of ΔNTW when the tracking mode control signal is 1.

An output of a phase detector 101 is inputted to the proportional loop filter 100. A PLL loop gain value must be large in order to quickly reduce a settling time of an ADPLL, and must be small in order to obtain superior phase noise characteristics. To meet both of the opposite characteristics, a gear-shift scheme is used.

The case wherein the tracking mode control signal is 0 means that the acquisition of a fast settling time is desirable. In this case, the value α₁ is selected so that a bandwidth of the ADPLL is widened, and the value 130 of α₁·φ_E[k] is outputted as the output of the loop filter. The case wherein the tracking mode control signal is 1 means that superior phase noise characteristic is desirable. In this case, the value α₂ (<α₁) is selected so that the loop bandwidth is narrowed to reduce noise, and the value 131 of α₂·φ_E[k] is outputted.

However, if the output of the loop filter abruptly changes from α₁ φ_E[k] as the value 130 to α₂·φ_E[k] as the value 131, the frequency locking of the ADPLL may be unlocked.

α₁·φ_E[k](130)=α₂·φ_E[k](131)+ΔNTW   (1)

If the offset value 142 of ΔNTW is added as expressed in Equation (1), the phase error value is maintained at the same value as before the change, even though the loop filter gain is changed. Thus, the frequency locking of the ADPLL is not unlocked, and noise is reduced because the loop bandwidth is narrowed.

ΔNTW(142)=(α₁−α₂)·φ_E[k]  (2)

The offset value may be calculated from Equation (2) under the conditions of Equation (1).

Since the hardware sizes of the multiplier and the divider are large, the bit shifters 120 and 121 may be used if a corresponding to the square of 2 is used. Thus, the size and complexity of the required hardware are reduced.

The output of the multiplexer 150 is the output 151 of the loop filter 100, and is inputted to a digitally controlled oscillator (DCO) 160. In the loop filter using the gear-shift scheme, noise may be further added at the moment when the gear shift is switched. When the difference between α₁ and α₂ is great, the gear shift may not find the frequency corresponding to α₂ at a time, and a settling time for a desired frequency value is required. Therefore, in order to reduce the settling time and improve the phase noise characteristic, the amount of shift switching must be increased by changing the loop filter gain value in sequence, for example, 2⁻²→2⁻⁴→2⁻⁶. Furthermore, there may be a problem in the stability of the ADPLL because the gear shift of the loop filter gain is applied only to the proportional loop filter structure.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a digital proportional integral loop filter capable of outputting a single desired frequency through one-time gain change by generating offset values using a phase error average value and a phase error accumulation average value even with a great change in loop filter gain, and capable of locking to the single desired frequency at a time to thereby reduce settling time.

According to an aspect of the present invention, there is provided a digital proportional integral loop filter including: a first proportional amplification unit multiplying a phase error value by a first proportional loop gain; a first integral amplification unit multiplying a phase error accumulation value by a first integral loop gain; a second proportional amplification unit multiplying the phase error value by a second proportional loop gain; a second integral amplification unit multiplying the phase error accumulation value by a second integral loop gain; a first offset value generation unit generating a first offset value which is calculated by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value; and a second offset value generation unit generating a second offset value which is calculated by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a structure of a type-I loop filter using a related art gear-shift scheme;

FIG. 2 illustrates a structure of a digital proportional integral loop filter according to an embodiment of the present invention;

FIG. 3 illustrates a detailed structure of the digital proportional integral loop filter of FIG. 2; and

FIG. 4 is a graph of simulation results showing an output frequency change of an ADPLL to which the digital proportional integral loop filter is added.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.

In addition, in a whole disclosure, when one element is referred to as being “connected” to another element, it should be understood that the former can be “directly connected” to the latter, or “electrically connected” to the latter via an intervening element. Furthermore, “including” an element signifies further including, not excluding, another element if there is no specific reference to the contrary.

FIG. 2 illustrates a structure of a digital proportional integral loop filter according to an embodiment of the present invention.

Referring to FIG. 2, the digital proportional integral loop filter according to the embodiment of the present invention includes a first proportional amplification unit 210, a first integral amplification unit 220, a first adder 230, a second proportional amplification unit 240, a second integral amplification unit 250, a first offset value generation unit 260, a second offset value generation unit 270, a second adder 280, and a multiplexer 290.

The first proportional amplification unit 210 and the second proportional amplification unit 240 multiply phase errors by proportional loop gains.

The first integral amplification unit 220 and the second integral amplification unit 250 accumulate phase errors to generate a phase error accumulation value, and multiply the phase error accumulation value by integral loop gains.

The first offset value generation unit 260 generates a phase error average value by averaging the phase errors during a certain period where an average enable signal is activated, subtracts a second proportional loop gain from a first proportional loop gain, and multiplies the subtraction result value by the phase error average value. The multiplication result value is outputted as a first offset value.

The second offset value generation unit 270 generates a phase error accumulation average value by averaging the phase error accumulation values during a certain period where the average enable signal is activated, subtracts a second integral loop gain from a first integral loop gain, and multiplies the subtraction result value by the phase error accumulation average value. The multiplication result value is outputted as a second offset value.

The first adder 230 adds the output of the first proportional amplification unit 210 and the output of the first integral amplification unit 220, and outputs the addition result value to the multiplexer 290.

The second adder 280 adds the output of the second proportional amplification unit 240, the output of the second integral amplification unit 250, the output of the first offset value generation unit 260, and the output of the second offset value generation unit 270, and outputs the addition result value to the multiplexer 290.

The multiplexer 290 outputs the output of the first adder 230 when a gain change enable control signal is 0, and outputs the output of the second adder 280 when the gain change enable control signal is 1.

FIG. 3 illustrates a detailed structure of the digital proportional integral loop filter of FIG. 2.

In FIG. 3, α₁, α₂, β₁, β₂, ΔNTW1, and ΔNTW2 represent the first proportional loop gain, the second proportional loop gain, the first integral loop gain, the second integral loop gain, the first offset value, and the second offset value, respectively.

Referring to FIGS. 2 and 3, the digital proportional integral loop filter according to the embodiment of the present invention receives a phase error 301 of φ_E[k] and includes a phase error accumulation generator 432 with an adder 340 and a feedback loop 341. Here, the phase error accumulation generator 432 maybe shared by the second integral amplification unit 250, the first offset value generation unit 260, and the second offset value generation unit 270.

The first proportional amplification unit 210 may include an amplifier 310. Since the phase error 301 of φ_E[k] is multiplied by the first proportional loop gain α₁, α₁·φ_E[k] may be the output of the first proportional amplification unit 210.

The first integral amplification unit 220 may include the phase error accumulation generator 342 and an amplifier 312. The phase error accumulation generator 342 receives the phase error value φ_E[k] to generate the phase error accumulation value LF_temp[k] . Since the phase error accumulation value LF_temp[k] is multiplied by the first integral loop gain β₁, β₁·LF_temp[k] may be the output of the first integral amplification unit 220.

An adder 314 adds the output of the first proportional amplification unit 210 and the output of the first integral amplification unit 220 and outputs the addition result value to the multiplexer 315. When the gain change enable signal is 0 (signal state before gain change), the output of the loop filter may be given as follows:

LF_output[k]=α₁·φ_E[k]+β₁·LF_temp[k]

The second proportional amplification unit 240 may include two amplifiers 310 and 334. Since α₁ and α₂/α₁ are sequentially multiplied by the phase error φ_E[k], α₂·φ_E[k] may be the output of the second proportional amplification unit 240.

The second integral amplification unit 250 may include the phase error accumulation generator 342 and two amplifiers 312 and 364. The phase error accumulation generator 342 receives the phase error value φ_E[k] to generate the phase error accumulation value LF_temp[k]. Since β₁ and β₂/β₁ are sequentially multiplied by the phase error accumulation value LF_temp[k], β₂·LF_temp[k] may be the output of the second integral amplification unit 250.

The first offset value generation unit 260 may include a phase error average calculator 320, two amplifiers 330 and 332, and an adder 331. The first offset values ΔNTW1, when the phase error average calculator 320 is disabled and enabled, are as follows:

ΔNTW1=(α₁−α₂)φ_E[k]

ΔNTW1_ave=(α₁−α₂)φ_E—ave[k]

The second offset value generation unit 270 may include a phase error accumulation average calculator 350, two amplifiers 360 and 362, and an adder 361. The second offset values ΔNTW2, when the phase error accumulation average calculator 350 is disabled and enabled, are as follows:

ΔNTW2=(β₁−β₂)LF_temp[k]

ΔNTW2_ave=(β₁−β₂)LF_temp[k]

At this point, the phase error average value φ_E—ave[k] is a value obtained by accumulating the phase error value φ_E[k] during a period where the average enable signal is 1, and dividing the resulting value by the number of accumulation. The phase error accumulation average value LF_temp_ave[k] is a value obtained by accumulating the phase error accumulation value LF_temp[k] during a period where the average enable signal is 1, and dividing the resulting value by the number of accumulation.

An adder 365 adds the output of the second proportional amplification unit 240, the output of the second integral amplification unit 250, the output of the first offset value generation unit 260, and the output of the second offset value generation unit 270, and outputs the addition result value to the multiplexer 315. In a case where the gain change enable signal is 1 (state after the gain change), the output of the loop filter, when the phase error average calculator 320 and the phase error accumulation average calculator 350 are disabled, is as follows:

LF_output[k]=α₂·φ_E[k]+ΔNTW1+β₂·LF_temp[k]+ΔNTW2_ave

Also, in a case where the gain change enable signal is 1 (state after the gain change), the output of the loop filter, when the phase error average calculator 320 and the phase error accumulation average calculator 350 are enabled, is as follows:

LF_output[k]=α₂·φ_E[k]+ΔNTW1_ave+β₂·LF_temp[k]+ΔNTW2_ave

The operation of the digital proportional integral loop filter in accordance with the embodiment of the present invention will be described below, while comparing the outputs of the loop filter before and after the gain change.

When the gain change enable signal is 0 (signal state before loop filter gain change), the output of the loop filter is as follows:

LF_output[k]=α₁·φ_E[k]+β₁·LF_temp[k]

When the phase error average calculator 320 and the phase error accumulation average calculator 350 are disabled and the gain change enable signal is 1 (after loop filter gain change), the output of the loop filter is as follows:

LF_output[k]=α₂·φ_E[k]+ΔNTW1+β₂·LF_temp[k]+ΔNTW2

Also, two offset values are as follows:

ΔNTW1=(α₁−α₂)φ_E[k]

ΔNTW2=(β₁−β₂)LF_temp[k]

Therefore, since the outputs of the loop filter before and after the gain change are identical to each other, the frequency locking is not unlocked during the gain change. Furthermore, the use of the proportional integral loop filter may increase the stability of ADPLL, compared with the use of the proportional loop filter.

Another feature of the digital proportional integral loop filter according to the embodiment of the present invention is that, unlike the existing gear shift method, the phase error average value φ_E—ave[k] instead of the phase error φ_E(k) is used as the input of the gear shift in the proportional amplification unit. Moreover, the phase error accumulation average value LF_temp_ave[k] instead of the phase error accumulation value LF_temp[k] is used as the input of the gear shift in the integral amplification unit.

Therefore, two offset values using such average values are as follows:

ΔNTW1_ave=(α₁−α₂)φ_E—ave[k]

ΔNTW2_ave=(β₁−β₂)LF_temp_ave[k]

In this case, the output of the loop filter after the gain change is as follows:

LF_output[k]=α₂·φ_E[k]+ΔNTW1_ave+β₂·LF_temp[k]+ΔNTW2_ave

Since the offset values are generated using the average values, the desired frequency may be outputted through one-time gain change, even though the loop filter gain value is greatly changed.

FIG. 4 is a graph of simulation results showing the output frequency change of the ADPLL with the digital proportional integral loop filter according to the embodiment of the present invention.

During a phase error average period 420 before the gain change of the loop filter, the phase error average calculator and the phase error accumulation average calculator within the first and second offset value generation units calculate the phase error average value φ_E—ave[k] and the phase error accumulation average value LF_temp_ave[k], respectively.

At the moment the gain change enable control signal becomes 1, the loop filter gain values change from α₁=2⁻³ and β₁=2⁻⁷ to α₂=2⁻⁸ and β₂=2⁻¹⁵.

From graph A of FIG. 4 showing a DCO input signal, it can be seen that a DCO input close to a desired frequency is generated at a time after the gain change of the loop filter.

Furthermore, from graph B of FIG. 4 showing a DCO output signal, it can be seen that a frequency corresponding to a desired frequency range is generated at a time after the gain change of the loop filter.

As set forth above, the gear shift method according to the related art has a problem in that the number of the gear shift switching may increase when the loop filter gain value is greatly changed. However, the digital proportional integral loop filter in accordance with the embodiment of the present invention may solve the problem of the related art by containing the phase error average value and the phase error accumulation average value during the offset value generation. Furthermore, the settling time may be reduced because the locking to a desired frequency is achieved at a time, even though the loop filter gain value is greatly changed. Moreover, since the proportional integral loop filter is used, the stability of the ADPLL may increase.

While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A digital proportional integral loop filter comprising: a first proportional amplification unit multiplying a phase error value by a first proportional loop gain;a first integral amplification unit multiplying a phase error accumulation value by a first integral loop gain;a second proportional amplification unit multiplying the phase error value by a second proportional loop gain;a second integral amplification unit multiplying the phase error accumulation value by a second integral loop gain;a first offset value generation unit generating a first offset value which is calculated by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value; anda second offset value generation unit generating a second offset value which is calculated by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

2. The digital proportional integral loop filter of claim 1, wherein the digital proportional integral loop filter further comprises: a first adder adding an output of the first proportional amplification unit and an output of the first integral amplification unit;a second adder adding an output of the second proportional amplification unit, an output of the second integral amplification unit, an output of the first offset value generation unit, and an output of the second offset value generation unit; anda multiplexer outputting an output of the first adder or an output of the second adder.

3. The digital proportional integral loop filter of claim 2, wherein the first offset value generation unit comprises: a phase error average calculator calculating the phase error average value within a period where an average enable control signal is activated;a first amplifier multiplying an output of the phase error average calculator by (the first proportional loop gain/the second proportional loop gain);a third adder outputting a value which is calculated by subtracting the output of the phase error average calculator from an output of the first amplifier; anda second amplifier multiplying an output of the third adder by the second proportional loop gain.

4. The digital proportional integral loop filter of claim 2, wherein the second offset value generation unit comprises: a phase error accumulation average calculator calculating the phase error accumulation average value within a period where an average enable control signal is activated;a third amplifier multiplying an output of the phase error accumulation average calculator by (the first integral loop gain/the second integral loop gain);a fourth adder outputting a value which is calculated by subtracting the output of the phase error accumulation average calculator from an output of the third amplifier; anda fourth amplifier multiplying an output of the fourth adder by the second integral loop gain.

5. The digital proportional integral loop filter of claim 2, wherein the multiplexer outputs the output of the first adder when a gain change enable control signal is a state before a gain change, and outputs the output of the second adder when the gain change enable control signal is a state after the gain change.

6. The digital proportional integral loop filter of claim 1, wherein the digital proportional integral loop filter comprises a phase error accumulation generator receiving the phase error value to generate a phase error accumulation value, wherein the phase error accumulation generator is shared by the first integral amplification unit, the second integral amplification unit, and the second offset value generation unit.

7. The digital proportional integral loop filter of claim 6, wherein the phase error accumulation generator comprises: a fifth adder adding the phase error value and an output of a feedback loop; andthe feedback loop providing an output of the fifth adder to an input of the fifth adder.

8. The digital proportional integral loop filter of claim 1, further comprising first to third phase error accumulation generators provided in the first integral amplification unit, the second integral amplification unit, and the second offset value generation unit, respectively, to receive the phase error value to generate phase error accumulation values.