BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an exemplary configuration of a digital signal processing apparatus according to an embodiment of the present invention;
FIG. 2 is a block diagram showing a sigma-delta modulator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a data configuration of a memory according to an embodiment of the present invention;
FIG. 4 is a flowchart showing a process executed by a CPU according to an embodiment of the present invention;
FIG. 5 is a block diagram showing an exemplary hardware configuration of a decimation filter according to an embodiment of the present invention;
FIG. 6 is a detail flowchart showing a digital filtering process of Step S1-2 of FIG. 4 according to an embodiment of the present invention; and
FIG. 7 is a schematic diagram for describing an operation of a digital signal processing apparatus according to an embodiment of the present invention.