The invention relates to integrated circuit devices (“ICs”). More particularly, the invention relates to a digital signal processing block with a preadder stage for an IC.
Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Performance of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) is limited by the speed of the FPGA fabric. However, dedicated circuit resources, such as DSPs in an FPGA, are capable of performing operations faster than equivalent circuits implemented in FPGA fabric. Accordingly, it would be desirable and useful to provide means for expanding the usefulness of DSPs.
One or more embodiments generally relate to integrated circuit devices (“ICs”) and, more particularly, to a digital signal processing block with a preadder stage for an IC.
One embodiment of the present invention relates generally to an integrated circuit with a digital signal processing block. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus.
Another embodiment of the present invention relates generally to a systolic finite impulse response filter including a shift register coupled to a chain of digital signal processing blocks. The shift register is configured to broadcast a broadcast input to each first register of all but an ending one of the digital signal processing blocks of the chain. Each of the digital signal processing blocks has a second register. Each of the digital signal processing blocks has a third register. Output of the second register is coupled to input of the third register for each of the digital signal processing blocks to provide dual registers thereof. The dual registers is coupled in series for propagating a filter input series from a starting one of the digital signal processing blocks to the ending one of the digital signal processing blocks of the chain. Each of the digital signal processing blocks has a first adder coupled for receiving output from each of the first register and the third register for providing a first sum thereof. Each of the digital signal processing blocks has a fourth register coupled for receiving a respective filter coefficient. Each of the digital signal processing blocks has a multiplier coupled for receiving the first sum and the filter coefficient respectively thereof and configured for providing a partial result thereof. Each of the digital signal processing blocks has a second adder coupled for receiving the partial result thereof. Second adders of the digital signal processing blocks are coupled for accumulating the partial result of each of the digital signal processing blocks to provide a filter output series from the ending one of the digital signal processing blocks of the chain.
Yet another embodiment of the present invention relates generally to a method for filtering. A filter input series is obtained and provided to a chain of digital signal processing blocks as a first input thereto. Effective length of the digital signal processing blocks is dynamically changed to effectively adjust number of filter taps.
Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of the invention; however, the accompanying drawing(s) should not be taken to limit the invention to the embodiment(s) shown, but are for explanation and understanding only.
In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.
As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,
In some FPGAs, each programmable tile includes a programmable interconnect element (“INT”) 111 having standardized connections to and from a corresponding interconnect element in each adjacent tile. Therefore, the programmable interconnect elements taken together implement the programmable interconnect structure for the illustrated FPGA. The programmable interconnect element 111 also includes the connections to and from the programmable logic element within the same tile, as shown by the examples included at the top of
For example, a CLB 102 can include a configurable logic element (“CLE”) 112 that can be programmed to implement user logic plus a single programmable interconnect element (“INT”) 111. A BRAM 103 can include a BRAM logic element (“BRL”) 113 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured embodiment, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile 106 can include a DSP logic element (“DSPL”) 114 in addition to an appropriate number of programmable interconnect elements. An IOB 104 can include, for example, two instances of an input/output logic element (“IOL”) 115 in addition to one instance of the programmable interconnect element 111. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element 115 typically are not confined to the area of the input/output logic element 115.
In the pictured embodiment, a columnar area near the center of the die (shown in
Some FPGAs utilizing the architecture illustrated in
Note that
DSPs 106 are described in additional detail in a co-pending patent application entitled “Integrated Circuit with Cascading DSP Slices” by James M. Simkins, et al., assigned application Ser. No. 11/019,783, filed Dec. 21, 2004, which is incorporated by reference herein in its entirety. Example implementations of DSPs 106 may be found in Virtex™ and Spartan™ FPGAs available from Xilinx, Inc., of San Jose, Calif.
Preadder 204 includes multiplexers 301 through 306, registers 311 through 314, logic gates 321 and 322, and adder/subtractor 331. It should be appreciated that even though bit widths are illustratively shown in
While not shown for purposes of clarity and not limitation, in this embodiment, control select inputs to multiplexers 301 through 305 are provided from configuration memory cells of FPGA fabric. Such configuration memory cells are configured from a configuration bitstream. Thus, in the context of an FPGA, when such FPGA is obtaining state information as part of a power up cycle, the program states of those memory cells determine selected outputs for multiplexers 301 through 305, and such memory cells are not capable of having their state changed without resetting the FPGA. In other words, the status of multiplexers 301 through 305 during operation is static. In contrast to the static status of multiplexers 301 through 305 during FPGA operation, multiplexer 306 is dynamically operable; in other words, multiplexer 306 may have its control select changed during operation of an FPGA without having to reset such FPGA. Such control select, in this exemplary embodiment, is provided by a portion of inmode 202, namely inmode 202-0, where the “-0” is used to indicate bit position zero of an inmode bus.
Moreover, in addition to dynamic operation of multiplexer 306, logic gates 321 and 322, as well as subtractor 331, may be dynamically operated. Thus, such dynamically operable components may be changed during operation of user design. In this embodiment, inmodes 202-0 through 202-3 of
Inmode 202-0 is provided as a dynamic control select signal to multiplexer 306 for gating to provide either A input 211 or AC input 341 as delayed by either of A1 register 311 or A2 register 312, by both A1 register 311 and A2 register 312, or by neither A1 register 311 nor A2 register 312. Again, once selected by memory cell state, a selected output from multiplexers 301 through 305 is static during operation without resetting an FPGA.
Either A input 211 or AC input 341 may be output from multiplexer 301. Output from multiplexer 301 is provided as data input to A1 register 311 and as data input to multiplexer 302. Output of A1 register 311 is provided as data input to multiplexers 302, 304, and 306. Output of multiplexer 302 is provided as data input to A2 register 312 and as data input to multiplexer 303. Output of multiplexer 303 is provided as data input to multiplexers 304 and 306, as well as being provided as an X MUX output 342. Referring to
Returning to
As previously mentioned, preadder 204 includes a dual A register and a dual D register. This means, e.g., that A1 register 311 and A2 register 312 are dual-register configurable, even though both A1 and A2 registers, only one of A1 and A2 registers, or neither of A1 and A2 registers may be used in providing input to logic gate 322 via output of multiplexer 306. Furthermore, the dual D register is in reference to D register 313 and AD register 314.
Again, it should be appreciated that the upper input to multiplexer 306, as well as the lower input to multiplexer 304, sourced from the output of multiplexer 301 may be no registers deep, either A1 or A2 deep, or A1 and A2 deep. Furthermore, again, the lower input of multiplexer 306, as well as the upper input of multiplexer 304, is always A1 deep. Output of multiplexer 304 is AC output (“ACOUT”) signal (“AC output”) 343 of
Whether an upper input or a lower input of multiplexer 306 is selected for output is controlled by state of inmode 202-0, and output from multiplexer 306 is provided as data input to logic gate 322. Even though AND gates are illustratively depicted for logic gates 321 and 322, it should be appreciated that other logic gates may be used in accordance with the description herein. The other input of AND gate 322, which is an inverted input, is coupled to receive inmode 202-1. For this embodiment, inmode 202-1 represents bit position one of a bus of inmode 202. Output of AND gate 322 is provided as an input to adder/subtractor 331, namely A path input 261 as described below in additional detail, and to an upper input of multiplexer 305.
D input 201 is provided as data input to D register 313. Data output of D register 313 is provided to an upper input of AND gate 321. A lower input of AND gate 321 is coupled to receive inmode 202-2, which for this embodiment is bit position two of a bus of inmode 202. Output of AND gate 321 is provided as another input to adder/subtractor 331, namely D path input 262 as described below in additional detail. Whether adder/subtractor 331 is configured for adding or subtracting is controlled by inmode 202-3, which for this embodiment is bit position three of a bus of inmode 202. Output of adder/subtractor 331 is provided to a data input port of AD register 314. Output of AD register 314 is provided as another input to multiplexer 305. Output of multiplexer 305 is a multiplier operand signal, namely A multiplier (“A MULT”) signal 344 (illustratively shown in
Again, it should be appreciated that multiplexer 306, AND gate 322, AND gate 321, adder/subtractor 331 are respectively controlled for purposes of dynamic operation by inmodes 202-0 through 202-3, respectively representing bit positions zero through three of a bus of inmode 202. While inmodes 202-0 and 202-3 are used as control select signals for either selecting an output or a function, inmodes 202-1 and 202-2 are operative by their state for affecting or not affecting the output of AND gates 322 and 321, respectively.
In addition to being able to dynamically control AND gates 321 and 322, output of either of AND gates 321 and 322 may be used to source a zero input to adder/subtractor 331. Accordingly, it should be appreciated that if AND gate 322 provides a zero operand input to adder/subtractor 331, then the input of D input 201 which may be provided as an output of multiplexer 305, may pass through registers 313 and 314, namely a two deep register path. Alternatively, if a zero is sourced from the output of AND gate 321, and adder/subtractor 331 is used, then it is possible to have a three deep register path for either of A input 211 or AC input 341, namely through A1 register 311, A2 register 312, and AD register 314.
Likewise, X multiplexer (“X MUX”) signal 442 corresponds to X multiplexer signal 342, though again with a smaller bit width for this embodiment. It should be appreciated that X multiplexer signals 342 and 442 are AB concatenated as generally indicated as AB signal 250 of
Output of multiplexer 405 is another multiplier operand signal, namely B multiplier (“B MULT”) signal 444 (illustratively shown in
With simultaneous reference to
AB concatenated signal 250 does not have M register 253 in its path. Thus, a multiply operation between A and B has three pipeline register stages, and an add operation, such as an addition of AB concatenated (“A:B”) and C has two register stages. However, by the use of A2 register 312 and B2 register 412, registers A2312 and B2412 may be used to provide a register pipeline stage which would otherwise be associated with M register 253. In other words, the number of pipeline stages for inputs to X multiplexer 252 may be configured to be the same within DSP slice 200, which can be used to avoid register misses, namely “bubbles.” Accordingly, by setting an operational mode, as described below in additional detail, an A:B+C operation for example and an A*B+C operation for example may both be performed in three clock cycles, e.g., A1 register 311 to A2 register 312 to a P register of
A1 register 311, and A2 register 312, as well as B1 register 411 and B2 register 412, may be used to provide a register file function. Because of the dynamic control bus function of inmode 202, such register file may operate as a random access register file. Alternatively, A1 register 311, and A2 register 312, as well as B1 register 411 and B2 register 412, may be configured to provide shift register logic (“SRL”). Thus dual functionality of both a random access register file and an SRL is provided within DSP slice 200 using dynamic control via an inmode bus 202. Bus, e.g., can mean either a group of signals or a group of signal traces, or both.
Other functionality includes having preadder 204 used as a two-to-one multiplexer, namely by having adder/subtractor 331 select between inputs thereto for output to AD register 314 by having one of the operands be zero. In other words, one of outputs of AND gates 322 and 321 may be respectively forced to zero respectively, responsive to inmode 202-1 and 202-2. Additionally, if output of the A input path is a negative, then a zero may be sourced from the operand input along the D path to adder/subtractor 331 such that adder/subtractor 331 may be used to produce an absolute value of an A or AC operand provided to adder/subtractor 331. Furthermore, by shifting bits using A1 and A2 registers, a twos complement inversion may be performed.
Thus, to recapitulate, inmode 202-0 is used as a none/A1/A2 select signal. Inmode 202-1 may be used to zero output along an A register path, namely registers A1 and A2 (“A registers”). In other words, the ability to zero output facilitates multiplexing between A registers and a D register without using resets and without destroying register contents. When inmode 202-1 is equal to a logic 1, A path input 261 to adder/subtractor 331 is forced to zero, and thus D path input 262 to preadder 331 may be effectively selected for output. Additionally, when inmode 202-1 is equal to logic 1, A path input 261 to multiplexer 305 may be used to force A multiplier signal 344 to zero. However, in order to force A multiplier signal 344 to zero, the D port setting, namely the configuration memory cell setting for providing a control select signal to multiplexer 305 is set for disabling the D port, namely “if use_D port=false.”
Inmode 202-2 may be used to zero output of D register 313 along the lines previously described with respect to inmode 202-1 and output of an A register selected path. Thus, D path input 262 to adder/subtractor 331 would be a logic 0, which may be used for facilitating multiplexing between A path input 261 and D path input 262. Furthermore, inmode 202-1 and inmode 202-2 may be used for dynamic power gating for power conservation. If inmode 202-1 is at a logic 1 state, the A path input 261 to adder/subtractor 331 is forced to 0, and if inmode 202-2 is at a logic 0 state, the D path input 262 to adder/subtractor 331 is forced to 0. If both inputs to adder/subtractor 331 are logic 0, operation of adder/subtractor 331 consumes less power as there is no transistor switching within adder/subtractor 331 under such condition. Thus, by “dynamic power gating,” it is meant that both inputs to adder/subtractor 331 may be set to logic zero when adder/subtractor 331 functionality is not selected. By having fixed logic values provided as operand inputs to adder/subtractor 331, adder/subtractor 331 does not switch, and this may be used for dynamic conservation of power. In other words, because inmodes may be dynamically set for dynamically fixing operand inputs to adder/subtractor 331, adder/subtractor functionality may be dynamically selected or deselected, and with respect to the later, dynamic power conservation may be implemented.
Inmode 202-3 may be used to have the A operand of A input path 261 either added to or subtracted from the D operand of D input path 262 by adder/subtractor 331. Again, dynamic inversion of an A operand on A input path 261 may be used as an absolute value function. In other words, a register value held in A1 or A2 for example may be dynamically inverted by having the D operand input 262 forced to zero as previously described.
Inmode 202-4 may be used as a B1/B2 register select signal in the same way that inmode 202-0 may be used as an A1/A2 register select signal. Accordingly, it should be appreciated that functionality of DSP slice 200 extends well beyond simply adding a preadder to a DSP as was done in the Spartan™ FPGA DSP 48A available from Xilinx, Inc., of San Jose, Calif.
Furthermore, it should be appreciated that complex multiplication operations may be performed, such as (A+ai)*(B+bi)=(AB−ab)+(Ab+aB)i. A and a may be separate operands respectively input to A2 register 312 and A1 register 311 by using separate clock enable signals provided to those registers, and selectively outputting one of such two operands from multiplexer 306 responsive to inmode 202-0. Likewise, B and b may be separate operands respectively input to B2 register 412 and B1 register 411 by using separate clock enable signals provided to those registers, and selectively outputting one of such two operands from multiplexer 405 responsive to inmode 202-4. Operands A, B, a, and b may be stored locally in BRAM. Because of operand reuse, BRAM is only accessed in bursts of every other two clock cycles by DSP slice 200, may be read only once for the example complex multiplication operation, as A1, A2, B1 and B2 registers may be used to locally store the real and imaginary parts of such operands. Even though the example of a complex multiplication was used, it should be understood that the same may be said for performing a sequential multiplication, such as (A:a)*(B:b) for example. For purposes of clarity by way of example and not limitation, suppose 42 bits*34 bits is for (A:a)*(B:b), then the result may be obtained by A*B+sh17(A*0b+B*000000000a+sh17(0b*00000000a), where “sh17” indicates a 17 bit shift.
The sixth column of table 500 indicates programming state of a memory cell used to provide control select control of multiplexer 305 of
The seventh column of table 500 indicates the operand input on multiplier A port 344. The possible operand inputs illustratively shown are the values held in A1 or A2 for D registers. Additionally, as previously described, a logic 0 may be provided as A multiplier output 344. Furthermore, the value obtained by adding the operand values of D+A2, D+A1, D−A2, or D−A1, as stored in AD register 314 may be provided as A multiplier output 344. The notation A1/A2 and B1/B2 is used to describe one- and two-deep registers, respectively. If A input operands to adder/subtractor 331 are gated off, then registers D 313 and AD 314 in combination appear like a two-deep registration for D port 201. Thus, the notation D1/D2 respectively refers to D/AD registers for one- and two-deep registration, respectively.
In the Spartan™ FPGA the preadder is positioned between an input register and an output register, where the output register feeds the multiplier. However, this configuration cannot be used for implementing a systolic filter. In the following description, DSP slices 200 are described for implementing a systolic filter.
It should be understood that DSP slice 200 with the addition of preadder 204 and dual B register 242 is capable of supporting sequential complex multiplications, sequential multiplications, and sequential complex conjugate operations. Additionally, the ability to balance the AB concatenation path with the AB multiply path by having A2 and B2 registers essentially be virtual registers with respect to M register 253 allows dynamic switching between multiply and add operations with a three stage pipeline. Furthermore, the ability to dynamically access A1, A2, B1, B2, registers for writing to either of two deep input registers or reading from either of two deep input registers is facilitated by inmode 202, as previously described. Moreover, the flexibility to have zero input to either preadder input port facilitates a multichannel filters.
Three sets of filter coefficients may be locally stored, such as using A1 register 311, A2 register 312, and D register 313 and being able to switch from symmetric to non-symmetric operations dynamically, namely on each clock cycle. Additionally, it should be appreciated that the AD multiplexing capability of using adder/subtractor 331, when add and subtraction functionality is not needed, is supported for dynamic operations. When three sets of filter coefficient are stored locally, then preadder symmetry is not being used. Raw data is being applied via B input port 212 and/or B cascade input port 441 instead of A input port 211 and/or A cascade input port 341, and filter coefficients may be selected by using adder/subtractor 331 to provide a multiplexing function. Thus non-symmetric filters are possible with three sets of filter coefficients.
Even though FIR filter 700 is of a different design than FIR filter 600 of
However, in contrast to FIR filter 600, for FIR filter 700, an input register stage 606 is moved to the inputs of the preadder stage 605, a preadder stage 605 along with input registers 606 may be implemented in DSPs, and only SRL 604 is implemented in FPGA fabric 602. SRL 604 is, e.g., a SRL 16, with eight register stages. Input to SRL 604 is filter input x(n) 701, and output from SRL 604 is provided to each D register 313 of DSP slices 200-1 through 200-4 in parallel, namely broadcast.
Filter input x(n) 701 is also provided to an initial register of a chain of DSP slices 200-1 through 200-4. Inputs to FIR filter 700 may be obtained on or off chip with respect to an FPGA in which such FIR filter 700 is implemented. Filter input 701 is provided to A1 and A2 registers 311 and 312 of DSP slice 200-1 and then to A1 and A2 registers of each of the other DSP slices as in the form of a shift register, namely for sequential input. In this embodiment, A1 register 311 and A2 register 312 of DSP slices 200-1 through 200-4 in combination have the same delay or number of register stages as SRL 604.
Filter input 701 to SRL 604 is D input 201 prior to being broadcast to DSP slices 200-1 through 200-4. In this embodiment, because D input 201 is broadcast to each of DSP slices 200-1 through 200-4, it is implemented in FPGA fabric. Filter input 701 is also provided as input A 211 to DSP slice 200-1, namely a first stage DSP slice. However, for input to DSP slices 200-2 through 200-4 such input is AC output 343 provided as AC input 341 to the next stage in the cascade.
Four coefficients h0 through h3 are respectively provided to B input ports, namely B inputs 212 of DSP slices 200-1 through 200-4. In this embodiment, coefficients h0 through h3, namely coefficients 703, are provided to respective B input ports 212 of each of DSP slices 200-1 through 200-4, as such coefficients are not cascaded. In other words, BC input 441 and BC output 443 are not used in this embodiment. Coefficients 703 may be input to either B1 registers 411 or B2 registers 412. For purposes of clarity by way of example and not limitation, it shall be assumed that B1 registers 411 are used; however, it should be appreciated that B2 registers 412 may be used instead of B1 registers 411 or a combination of B1 and B2 registers may be used.
A PC output 802 is cascaded with a PC input 801 between each of the DSP slices. A PC output of DSP slice 200-4 provides the resultant filter output y(n−8) 710. Duplicate tap delay 711 is input to SRL 604 in order to provide for timing adjustments.
It should be appreciated that DSP slices 200 may be modeled using VHDL as modular components.
Again, AC input 341 is provided to A1 and A2 registers 311 and 312 sequentially. Each D input 201 is provided to D register 313 and outputs of those registers are provided to adder/subtractor 331 in an add mode.
Again, output of registers 312 is sequentially provided as AC output 343 to a downstream DSP slice 200-3, namely the AC input 341 of such downstream DSP slice 200-3. Likewise, AC input 341 is obtained from the AC output 343 of an upstream DSP slice 200-1.
Each B input 212 receives a coefficient to a B register such as B1 register 411. Output of adder/subtractor 331 is provided to AD register 314 and outputs of registers 411 and 314 are provided to multiplier 251.
Output of multiplier 251 is provided to M register 253 and output of M register 253, which is provided to an adder and then a subsequent output register stage, as was done in the prior art and thus not described in unnecessary detail for purposes of clarity. Moreover, as done in the prior art and thus not described in unnecessary detail for purposes of clarity, PC input 801, which may be obtained from a PC output 802 of an upstream DSP slice 200-1 is input to such adder for summing with the output of register 253, and the result of such add may be provided to an output register for providing PC output 802 to a downstream DSP slice 200-3.
Even though D input 201 may be shifted to register 313 of DSP slice 200-5, DSP slice 200-5 is configured to disable use of D port or a zero is input on D input path 262 to adder/subtractor 331 in an add mode of DSP slice 200-5. Accordingly, it should be appreciated that using dynamic configuration, an odd slice, such as DSP slice 200-5, at a final stage of an FIR filter, such as FIR filter 900, may be dynamically changed for purposes of operating as an odd number of tap filter. Likewise, an A input path 261 may be dynamically changed such that contents in registers 311 and 312 do not show up at adder/subtractor 331 of DSP slice 200-5, but rather a logic 0 is provided to both input ports of adder/subtractor 331.
In other words, by setting inmodes 202-1 and 202-2 appropriately, both inputs to adder/subtractor 331 may be zero. Additionally, for an even number of filter taps, there would not be an odd coefficient, such as h4 903, and hence coefficient input for any unused tap may be a logic 1 or a logic 0. Thus, output from register 253 may be a logic 0 provided to a final stage adder to provide an output which is in effect y(n−8) 710 of
Additionally, in this embodiment, there is a time lag in the operation or shifting of data into an FIR filter, and accordingly dynamic adjustment, as well as the data from one sequence of FIR operations to another sequence of FIR operations may be shadowed in. In other words, without waiting for completion of one FIR operation, such as an odd FIR operation, the data and parameters for a subsequent FIR operation may be shadowed into the FIR filter while still operating the FIR filter to complete the prior FIR operation sequence. The same is true for going from an odd FIR sequence of operations to an even FIR sequence of operations.
In either of the embodiments of
Accordingly, in this embodiment, a multiple stage FIR filter may be implemented. Such an FIR filter may be implemented for a longest possible FIR use depending on the application. Such an FIR filter may be used for example in time division multiplexing application, where FIR filters of different lengths are dynamically set without reconfiguration of programmable logic. In other words, a shift register for broadcasting a D input 201 may be set up for the longest FIR filter of a user application; but the SRL delay is dynamically modified to match the number of taps in the filter.
Even though only the last DSP slice of an odd FIR filter was described for dynamic setting using inmode, it should be appreciated that any number of DSP slices at the end an FIR may be dynamically set as such. Accordingly, in the above described 9-tap FIR filter, such FIR filter may be dynamically adjusted from nine taps down to one tap, or even effectively no taps in a bypass mode, without reconfiguration of programmable logic used to implement a shift register. More generally, a filter input series, x(n), may be coupled for input to a chain of DSPs forming an FIR filter for providing a filter output series, y(n−p), where p is an integer number of the effective number of taps and is dynamically adjustable.
It should be appreciated that even though generally fixed coefficients were described, such coefficients may change from application to application. Again, because two-deep register buffering is used, shadowing of information from one FIR depth to the next FIR depth may be used where the transfer is staggered for each of the stages.
Accordingly, it should be appreciated that such a filter may be gated by gating logic for dynamically zeroing out the ending one or more DSP blocks to operate such a filter as having an even number of taps even though there are an odd number of the DSP blocks in the chain. Moreover, such gating logic may be used for dynamically zeroing out the ending one or more DSP blocks to operate such filter as having an odd number of taps even though there are an even number of the DSP blocks in the chain.
While the foregoing describes exemplary embodiment(s) in accordance with one or more aspects of the invention, other and further embodiment(s) in accordance with the one or more aspects of the invention may be devised without departing from the scope thereof, which is determined by the claim(s) that follow and equivalents thereof. Claim(s) listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.
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