Claims
- 1. A digital signal processing circuit for processing data obtained from a playback channel, wherein a transmission rate of data from the playback channel is greater than a rate at which data can be processed comprising:a memory means for storing a digital signal obtained from the playback channel; a control means for writing the digital signal in said memory means at a first rate and reading out the digital signal from said memory means at a second rate lower than said first rate; a processing means for executing a desired process relative to the digital signal thus read out from said memory means; and said control means comprising a first counter for counting pulses of a first fixed-frequency clock signal to generate successive write addresses for writing said memory means until one sector of data is written therein, and a second counter for counting pulses of a second fixed-frequency clock signal to generate addresses for reading said memory means automatically on completion of writing said one sector.
- 2. The digital signal processing circuit according to claim 1, wherein said playback channel is associated with a disk.
- 3. The digital signal processing circuit according to claim 1, wherein said playback channel is a partial response channel.
- 4. The digital signal processing circuit according to claim 1, further comprising an A-D converter for converting the analog signal obtained from said playback channel into a digital signal, said A-D converter being disposed in a preceding stage of said memory means and driven in accordance with a first clock signal of a fixed frequency; and said processing means is driven in accordance with a second clock signal of another fixed frequency lower than that of the first clock signal.
- 5. The digital signal processing circuit according to claim 1, wherein said control means generates a read/write control signal and the read/write address signal in response to the first fixed-frequency clock signal, the second fixed-frequency clock signal, a sector index signal and a data read command signal.
- 6. The digital signal processing circuit according to claim 1, wherein said processing means includes an equalizer for equalizing the digital signal.
- 7. The digital signal processing circuit according to claim 1, wherein said processing means includes an interpolator for interpolating the 0° phase data on the basis of the digital signal.
- 8. The digital signal processing circuit according to claim 1, wherein said processing means includes a decoder for decoding the digital signal with the maximum likelihood.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-059711 |
Feb 1992 |
JP |
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Parent Case Info
This application is a continuation of Ser. No. 08/552,169 filed Nov. 2, 1995, now abandoned which is a continuation of Ser. No. 08/016,098 filed Feb. 10, 1993, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5146477 |
Cantoni et al. |
Sep 1992 |
|
5291468 |
Carmon et al. |
Mar 1994 |
|
Non-Patent Literature Citations (1)
Entry |
Cotton et al., “Dual-Ported Four-Sector File Buffer”, IBM Technical Disclosure Bulletin, vol. 19, No. 10, p. 3635-7, Mar. 1977. |
Continuations (2)
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Number |
Date |
Country |
Parent |
08/552169 |
Nov 1995 |
US |
Child |
08/963122 |
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US |
Parent |
08/016098 |
Feb 1993 |
US |
Child |
08/552169 |
|
US |