The invention relates generally to Inter-Integrated Circuit (I2C) systems and, more particularly, to deglitch filters for I2C systems.
Referring to
Turning to
Some other examples of prior art systems are European Patent No. 1109315 and U.S. Pat. Nos. 5,001,374; 5,418,486; 6,958,641; and 7,397,292.
A preferred embodiment of the present invention, accordingly, provides an apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus. The apparatus comprises a serial data (SDA) filter that is adapted to receive an SDA signal from the I2C bus, wherein the SDA filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected; a serial clock (SCL) filter that is adapted to receive an SCL signal from the I2C bus, wherein the SCL filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected, and wherein the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and wherein the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter; I2C interface logic that is coupled to the SDA filter and to the SCL filter; and operational circuitry that is coupled the I2C interface logic.
In accordance with a preferred embodiment of the present invention, the SDA filter further comprises a first flip-flop that is adapted to receive the SDA signal; a second flip-flop that is coupled to an output of the first flip-flop; a third flip-flop that is coupled to an output the second flip-flop; and an XOR gate that is coupled to the output of the second flip-flop and to an output of the third flip-flop, wherein the XOR gate issues the disable signal when the transient in the SDA signal is detected.
In accordance with a preferred embodiment of the present invention, the SDA filter further comprises a first multiplexer having a plurality of input terminals, a plurality of select terminals, and an output terminal, wherein at least one of the select terminals of the first multiplexer is coupled to the output of the second flip-flop, and wherein at least one of the select terminals of the first multiplexer is coupled to the output of the third flip-flop; a second multiplexer having a plurality of input terminals, a select terminal, and an output terminal, wherein at least one of the input terminals of the second multiplexer is coupled to the output terminal of the first multiplexer, and wherein the select terminal is coupled to the hold terminal of the SDA filter; and a fourth flip-flop that is adapted to receive a signal from output terminal of the third multiplexer.
In accordance with a preferred embodiment of the present invention, the SCL filter further comprises a first flip-flop that is adapted to receive the SCL signal; a second flip-flop that is coupled to an output of the first flip-flop; a third flip-flop that is coupled to an output the second flip-flop; and an XOR gate that is coupled to the output of the second flip-flop and to an output of the third flip-flop, wherein the XOR gate issues the disable signal when the transient in the SDA signal is detected.
In accordance with a preferred embodiment of the present invention, the SCL filter further comprises a first multiplexer having a plurality of input terminals, a plurality of select terminals, and an output terminal, wherein at least one of the select terminals of the first multiplexer is coupled to the output of the second flip-flop, and wherein at least one of the select terminals of the first multiplexer is coupled to the output of the third flip-flop; a second multiplexer having a plurality of input terminals, a select terminal, and an output terminal, wherein at least one of the input terminals of the second multiplexer is coupled to the output terminal of the first multiplexer, and wherein the select terminal is coupled to the hold terminal of the SDA filter; and a fourth flip-flop that is adapted to receive a signal from output terminal of the third multiplexer.
In accordance with a preferred embodiment of the present invention, a system is provided. The system comprises an I2C bus; an integrated circuit (IC) that is coupled to the I2C bus, wherein the IC includes: a serial data (SDA) filter that is adapted to receive an SDA signal from the I2C bus, wherein the SDA filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected; a serial clock (SCL) filter that is adapted to receive an SCL signal from the I2C bus, wherein the SCL filter includes a hold terminal and a disable terminal, and wherein the hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected, and wherein the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and wherein the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter; I2C interface logic that is coupled to the SDA filter and to the SCL filter; and operational circuitry that is coupled the I2C interface logic.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
Referring to
In operation, the I2C interface 306 employs SDA filter 310 and SCL filter 312 and I2C interface logic 314 to provide generally deglitched communications over the I2C bus 203. The SDA filter 310 and SCL filter 312 are each coupled between the I2C bus 302 and I2C interface logic 314, which, in turn, is coupled to operational circuitry 308. To perform the deglitching, though, each of filters 310 and 312 include cross-coupled disable and hold terminals. Thus, when a glitch is detected in either of filters 310 or 312, a disable signal
To accomplish this, filters 310 and 312 generally take the form of filter 400 as shown in
In operation, this filter 400 is able to generate a filter data output DOUT and a disable signal
Turning to
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
Number | Name | Date | Kind |
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5001374 | Chang | Mar 1991 | A |
5267172 | Vermesse | Nov 1993 | A |
5418486 | Callahan | May 1995 | A |
6414540 | Drexler | Jul 2002 | B2 |
6958641 | Lee | Oct 2005 | B2 |
7397292 | Potanin | Jul 2008 | B1 |
20070024607 | Chen | Feb 2007 | A1 |
Number | Date | Country |
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1109315 | Jun 2001 | EP |
Number | Date | Country | |
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20100244919 A1 | Sep 2010 | US |