Patent Application
20250111813
This application claims the priority benefits of Japanese application no. 2023-170545, filed on Sep. 29, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a digital-to-analog conversion device, a display driver for driving a display panel, and a display device.
A known liquid crystal display device includes a display panel in which a plurality of data lines and a plurality of scan lines are arranged to intersect each other and in which display cells serving as pixels are formed at the intersections, as well as a source driver and a gate driver that drive the display panel (see, for example, Japanese Patent Application Laid-Open No. 2009-145492).
The source driver includes a shift register, a level shifter, a data register latch, a DA (digital-to-analog) conversion part, and an output amplifier part.
The shift register generates a plurality of latch timing signals for selecting latches in synchronization with a clock signal, and supplies the same to the data register latch.
The data register latch takes in, for example, n 8-bit display data pieces corresponding to each display cell based on a video signal, on the basis of each of the latch timing signals supplied from the shift register. The level shifter performs a level shift process on each of the n display data pieces to increase the amplitude of the signal level corresponding to each bit, and supplies each of the resulting level-shifted n display data pieces to the DA conversion part.
The DA conversion part includes a gamma circuit and n selection circuits (decoders) provided corresponding to the n display data pieces, respectively. The gamma circuit generates, for example, 256 voltages having different voltage values as reference voltages, and supplies the same to each of the n selection circuits. Each of the selection circuits selects, from the 256 reference voltages, a reference voltage that corresponds to the value indicated by the 8-bit display data piece which the selection circuit receives. With this configuration, the DA conversion part supplies the n reference voltages selected by the n selection circuits described above as n gradation voltages to the output amplifier part. The output amplifier part amplifies each of the n gradation voltages individually, and supplies the amplified voltages as output voltages to the n data lines of the display panel.
With the trend toward larger screen size and higher resolution for display panels in recent years, the period (one data period) in which the output voltage (gradation voltage) corresponding to one display data piece is charged to the display cell of the display panel has become shorter, and the output voltage is required to have a high-quality waveform in order to obtain the desired display quality.
However, the display data piece uses binary code. Even if the amount of change in luminance level of the display data piece supplied to the DA conversion part per horizontal scan period is slight, the number of changes in the logic level of each bit of the display data piece may be large.
For example, in the case where a display data piece changes the state from representing a luminance level of “126” to “127”, the 8-bit binary code changes from [01111110] to [01111111]. In other words, for a change in luminance level of “1”, the number of bits changed in the binary code is “1”.
However, in the case where the display data piece changes the state from representing a luminance level of “127” to “128”, the 8-bit binary code changes from [01111111] to [10000000].
Thus, in binary code, the Hamming distance between adjacent codes changes between “1” and the total number of bits (for example, 8). Therefore, in this case, even though the amount of change in luminance level is “1”, the Hamming distance between the codes, that is, the total number of inversions of the logic level for each bit digit, is “8”.
As a result, a current corresponding to the number of inversions of the logic level flows suddenly in each of the data register latch and the DA conversion part, and this causes noise. Therefore, there is a risk that the noise may be superimposed on the output voltage and cause the image quality to deteriorate.
The disclosure provides a digital-to-analog conversion device capable of generating a high-quality output voltage with noise superimposition suppressed, and a display driver and a display device including the digital-to-analog conversion device.
A digital-to-analog conversion device according to the disclosure includes: a Gray code conversion circuit receiving a series of digital data pieces including binary codes, and generating Gray code data pieces obtained by respectively converting the digital data pieces into Gray codes; a decoder receiving the Gray code data pieces and a plurality of reference voltages having different voltage values, selecting two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputting the two reference voltages as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit including a first input terminal and a second input terminal that respectively receive the first selection voltage and the second selection voltage, and generating an output voltage by amplifying a voltage that is obtained by interpolating the first selection voltage and the second selection voltage by a weighting ratio assigned to the first input terminal and the second input terminal.
A display driver according to the disclosure includes first to nth digital-to-analog conversion circuits that receive a series of pixel data pieces, each of which represents a luminance level of each pixel based on a video signal in a binary code, convert the pixel data pieces into first to nth output voltages having voltage values corresponding to the luminance levels for each of n (n is an integer greater than or equal to 2) pixel data pieces included in the series of pixel data pieces, and supply the first to nth output voltages to first to nth data lines of a display panel. The display driver includes: a Gray code conversion circuit generating Gray code data pieces by respectively converting the pixel data pieces included in the series of pixel data pieces into Gray codes, in which each of the first to nth digital-to-analog conversion circuits includes: a decoder receiving the Gray code data pieces and a plurality of reference voltages having different voltage values, selecting two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputting the two reference voltages as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit including a first input terminal and a second input terminal that respectively receive the first selection voltage and the second selection voltage, and generating, as the output voltage, a voltage obtained by interpolating the first selection voltage and the second selection voltage by a weighting ratio assigned to the first input terminal and the second input terminal.
A display device according to the disclosure includes: a display panel on which first to nth (n is an integer greater than or equal to 2) data lines are arranged, each of which includes a plurality of display cells formed thereon; a display driver including first to nth digital-to-analog conversion circuits that receive a series of pixel data pieces, each of which represents a luminance level of each pixel based on a video signal in a binary code, convert the pixel data pieces into first to nth output voltages having voltage values corresponding to the luminance levels for each of n pixel data pieces included in the series of pixel data pieces, and supply the first to nth output voltages to the first to nth data lines of the display panel; and a Gray code conversion circuit generating Gray code data pieces by respectively converting the pixel data pieces included in the series of pixel data pieces into Gray codes, in which each of the first to nth digital-to-analog conversion circuits includes: a decoder receiving the Gray code data pieces and a plurality of reference voltages having different voltage values, selecting two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputting the two reference voltages as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit including a first input terminal and a second input terminal that respectively receive the first selection voltage and the second selection voltage, and generating, as the output voltage, a voltage obtained by interpolating the first selection voltage and the second selection voltage by a weighting ratio assigned to the first input terminal and the second input terminal.
In the disclosure, a series of digital data pieces represented by a binary code is received, each digital data piece is converted into a Gray code, and each of the Gray code data pieces converted into the Gray code is digital-to-analog converted to generate an output voltage having an analog voltage value.
Thus, it is possible to generate a high-quality output voltage with a reduced amount of noise generated during transition between adjacent gradations in the digital data piece.
As shown in
The display panel 20 is composed of, for example, a liquid crystal or organic EL (electroluminescence) panel, and includes horizontal scan lines S1 to Sm (m is an integer greater than or equal to 2) extending in the horizontal direction of a two-dimensional screen, and data lines D1 to Dn (n is an integer greater than or equal to 2) extending in the vertical direction of the two-dimensional screen. At each intersection of the horizontal scan lines and the data lines, a display cell PC serving as a pixel is formed.
The display controller 11 receives a video signal VS, and supplies to the scan driver 12 a scan timing signal indicating the timing for sequentially selecting the horizontal scan lines S1 to Sm according to the video signal VS.
Further, the display controller 11 generates various control signals including a start pulse signal STP and a clock signal CLK, and a video data signal VD, based on the video signal VS. The start pulse signal STP is a single pulse signal that is generated according to a horizontal scan synchronization signal included in the video signal VS. In addition, the video data signal VD is a signal including a series of pixel data pieces that represent, in binary code, the luminance level of each display cell PC serving as a pixel. The display controller 11 supplies these video data signal VD and control signals to the data driver 13.
The scan driver 12 sequentially applies horizontal scan pulses to the horizontal scan lines S1 to Sm of the display panel 20 according to the scan timing signal supplied from the display controller 11.
According to the various control signals (including STP and CLK) supplied from the display controller 11, the data driver 13 converts each of n pixel data pieces in the series of pixel data pieces included in the video data signal VD into an analog voltage having a magnitude corresponding to the luminance level indicated by that pixel data piece. Then, the data driver 13 supplies the n voltages, which are obtained by respectively converting the n pixel data pieces into analog voltages, to the data lines D1 to Dn of the display panel 20 as output voltages G1 to Gn.
As shown in
The Gray code conversion circuit 130 receives the video data signal VD, and converts each of the pixel data pieces included in the video data signal VD into a Gray code. For example, as shown in
When the shift register 131 receives the start pulse signal STP which is a single pulse signal, the shift register 131 shifts this sequentially at a timing synchronized with the clock signal CLK to generate n systems of latch timing signals SR1 to SRn, each of which produces a single pulse at a different timing. The shift register 131 supplies the latch timing signals SR1 to SRn to the data latch part 132.
The data latch part 132 includes data latches LC1 to LCn which receive the latch timing signals SR1 to SRn individually. The data latch LC1 latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SR1. The data latch LC2 latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SR2. Similarly, each of the data latches LC3 to LCn latches one Gray code data piece included in the series VDG of Gray code data pieces at the timing of a single pulse included in the latch timing signal SRj (j is an integer of 3 to n) that the data latch receives.
Then, the data latches LC1 to LCn simultaneously supply the n pieces of Gray code data (hereinafter also referred to as GR data) that the data latches LC1 to LCn have latched as described above to the DA conversion part 133 as GR data R1 to Rn.
The DA conversion part 133 includes a reference voltage generation circuit RFG that generates a plurality of reference voltages V0 to Vx (x is an integer greater than or equal to 1) having different voltage values, and DA conversion circuits DA1 to DAn provided corresponding to the GR data R1 to Rn, respectively.
The DA conversion circuits DA1 to DAn individually receive the corresponding GR data R1 to Rn, convert the GR data R1 to Rn into output voltages G1 to Gn having analog voltage values by using the above-mentioned reference voltages V0 to Vx, and output the output voltages G1 to Gn. The DA conversion circuits DA1 to DAn have the same internal configuration.
As shown in
The decoder DEC receives the reference voltages V0 to Vx supplied from the reference voltage generation circuit RFG, and the GR data R1 composed of a Gray code of a total of (k+1) bits, including the kth (k is an integer greater than or equal to 2) bit (most significant bit) to the 0th bit (least significant bit).
The decoder DEC includes a first decoder DE1 and a second decoder DE2.
The first decoder DE1 receives an upper bit group MB including the most significant bit in the GR data R1, and selects 2w (w is an integer greater than or equal to 1) reference voltages having adjacent values from the reference voltages V0 to Vx based on the upper bit group MB.
The total number of reference voltages V0 to Vx is 2(k−w+1), and the upper bit group MB is the kth bit (most significant bit) to the (2·w)th bit in the GR data R1. Here, “w” is a value that satisfies the relationship of k≥(2w−1)>0.
The first decoder DE1 supplies the selected 2w reference voltages to the second decoder DE2 as selection voltages L1 to L2w.
The second decoder DE2 receives a lower bit group LB including the least significant bit in the GR data R1, as well as the selection voltages L1 to L2w. The lower bit group LB is the (2·w−1)th bit to the 0th bit (least significant bit) in the GR data R1.
The second decoder DE2 selects two of the above-mentioned selection voltages L1 to L2w that include an overlap based on the lower bit group LB, and supplies the same to the amplifier circuit AP1 as a first selection voltage T1 and a second selection voltage T2. In the DA conversion circuit DA1 shown in
In other words, the GR data R1 is a 4-bit Gray code composed of the third bit d3 to the 0th bit d0 shown in
V7>V6>V5>V4>V3>V2>V1>V0
Furthermore, in
As shown in
The transistors Q1 and Q5 supply the reference voltage V0 to the transistor Q9 in the case where the third bit d3 is at logic level 1, and supply the reference voltage V7 to the transistor Q9 in the case where the third bit d3 is at logic level 0.
The transistors Q2 and Q6 supply the reference voltage V4 to the transistor Q11 in the case where the third bit d3 is at logic level 1, and supply the reference voltage V3 to the transistor Q11 in the case where the third bit d3 is at logic level 0.
The transistors Q3 and Q7 supply the reference voltage V6 to the transistor Q10 in the case where the third bit d3 is at logic level 1, and supply the reference voltage V1 to the transistor Q10 in the case where the third bit d3 is at logic level 0.
The transistors Q4 and Q8 supply the reference voltage V5 to the transistor Q12 in the case where the third bit d3 is at logic level 1, and supply the reference voltage V2 to the transistor Q12 in the case where the third bit d3 is at logic level 0.
In the case where the second bit d2 is at logic level 1, the transistors Q9 and Q11 supply the reference voltage V0 or V7 supplied via the transistor Q1 or Q5 to the second decoder DE2 as the selection voltage L1. On the other hand, in the case where the second bit d2 is at logic level 0, the transistors Q9 and Q11 supply the reference voltage V3 or V4 supplied via the transistor Q2 or Q6 to the second decoder DE2 as the selection voltage L1.
In the case where the second bit d2 is at logic level 1, the transistors Q10 and Q12 supply the reference voltage V2 or V5 supplied via the transistor Q4 or Q8 to the second decoder DE2 as the selection voltage L2. On the other hand, in the case where the second bit d2 is at logic level 0, the transistors Q10 and Q12 supply the reference voltage V2 or V5 supplied via the transistor Q4 or Q8 to the second decoder DE2 as the selection voltage L2.
As shown in
In the selection circuit EXSEL, in the case where the first bit d1 is at logic level 1, the transistors Q21 and Q24 supply the selection voltage L2 supplied from the first decoder DE1 to the transistor Q25. On the other hand, in the case where the first bit d1 is at logic level 0, the transistors Q21 and Q24 supply the selection voltage L1 supplied from the first decoder DE1 to the transistor Q25.
In the case where the first bit d1 is at logic level 1, the transistors Q22 and Q23 supply the selection voltage L1 supplied from the first decoder DE1 to the transistor Q26. On the other hand, in the case where the first bit d1 is at logic level 0, the transistors Q22 and Q23 supply the selection voltage L2 supplied from the first decoder DE1 to the transistor Q26.
In the case where the 0th bit d0 is at logic level 1, the transistors Q25 and Q26 output the selection voltage L1 or L2 supplied via the transistor Q22 or Q23 as the selection voltage T1. On the other hand, in the case where the 0th bit d0 is at logic level 0, the transistors Q25 and Q26 output the selection voltage L1 or L2 supplied via the transistor Q21 or Q24 as the selection voltage T1.
In the selection circuit SEL, in the case where the first bit d1 is at logic level 1, the transistors Q31 and Q32 output the selection voltage L2 supplied from the first decoder DE1 as the selection voltage T2. On the other hand, in the case where the first bit d1 is at logic level 0, the selection voltage L1 supplied from the first decoder DE1 is output as the selection voltage T2.
As a result, as shown in
The amplifier circuit AP1 is an operational amplifier having an interpolation function, the output terminal of which is connected to the inverting input terminal of which, and the operational amplifier includes two non-inverting input terminals +A1 and +A2 that receive the selection voltages T1 and T2, respectively.
The amplifier circuit AP1 performs interpolation between the selection voltage T1 received at the non-inverting input terminal +A1 and the selection voltage T2 received at the non-inverting input terminal +A2 by the weighting ratio that is preset for each of the non-inverting input terminals +A1 and +A2, and generates the amplified voltage obtained as the result as an output voltage Vout.
For example, in the case where the weighting ratio assigned to the non-inverting input terminal +A1 and the non-inverting input terminal +A2 is:
For example, the DA conversion circuit DA1 outputs the output voltage Vout output from its own amplifier circuit AP1 as an output voltage G1.
Therefore, according to the configuration of each of the DA conversion circuits DA1 to DAn shown in
Each of the DA conversion circuits DA1 to DAn outputs the output voltage Vout output from its own amplifier circuit AP1 as the output voltages G1 to Gn.
Furthermore, in the data driver 13, each of the GR data pieces, which is obtained by converting each pixel data piece representing the luminance level of each pixel based on the video signal VS in, for example, 4 bits from binary code into Gray code, is taken in by the data latch part 132. At this time, the data latch part 132 supplies the n GR data pieces taken therein to the DA conversion part 133 as GR data R1 to Rn. The DA conversion part 133 converts each piece of the GR data R1 to Rn into an analog voltage value corresponding to the luminance level represented by the original binary code.
In this case, in Gray code, the Hamming distance between adjacent codes is always “1”. For example, as shown in
Therefore, in the data latch part 132 and the decoder DEC of the DA conversion part 133, the frequency of logic level inversion occurring at each bit is significantly reduced compared to the case where the n pixel data pieces are received directly in the form of binary code, and accordingly, the current flows within the data latch part 132 and the DA conversion part 133 decreases. This suppresses noise caused by a sudden increase in the current flowing within the data latch part 132 and the DA conversion part 133 due to transition of the pixel data pieces. Thus, the data driver 13 is capable of outputting high-quality output voltages G1 to Gn without noise being superimposed thereon.
The second decoder DE2 shown in
In
The selection circuit EXS3 outputs, as the selection voltage T1, the selection voltage L1 or L4 supplied from the selection circuit EXS1, or the selection voltage L2 or L3 supplied from the selection circuit EXS2, according to the first bit d1 and the 0th bit d0.
The selection circuit SE1 supplies the selection voltage L1 or L4 to the selection circuit EXS4 according to the third bit d3. The selection circuit SE2 supplies the selection voltage L2 or L3 to the selection circuit EXS4 according to the third bit d3.
The selection circuit EXS4 outputs, as the selection voltage T2, the selection voltage L1 or L4 supplied from the selection circuit SE1, or the selection voltage L2 or L3 supplied from the selection circuit SE2, according to the second bit d2 and the first bit d1.
According to the configuration shown in
Therefore, according to the second decoder DE2 shown in
The second decoder DE2 shown in
In
The selection circuit EXS5 supplies the selection voltage L1 or L8 supplied from the selection circuit EXS1, or the selection voltage L4 or L5 supplied from the selection circuit EXS2, to the selection circuit EXS7 according to the third bit d3 and the second bit d2.
The selection circuit EXS6 supplies the selection voltage L2 or L7 supplied from the selection circuit EXS3, or the selection voltage L3 or L6 supplied from the selection circuit EXS4, to the selection circuit EXS7 according to the third bit d3 and the second bit d2.
The selection circuit EXS7 outputs, as the selection voltage T1, the selection voltage L1, L8, L4, or L5 supplied from the selection circuit EXS5, or the selection voltage L2, L7, L3, or L6 supplied from the selection circuit EXS6, according to the first bit d1 and the 0th bit d0.
In
The selection circuit EXS8 supplies the selection voltage L1 or L8 supplied from the selection circuit SE1, or the selection voltage L4 or L5 supplied from the selection circuit SE2, to the selection circuit EXS10 according to the fourth bit d4 and the third bit d3.
The selection circuit EXS9 supplies the selection voltage L2 or L7 supplied from the selection circuit SE3, or the selection voltage L3 or L6 supplied from the selection circuit SE4, to the selection circuit EXS10 according to the fourth bit d4 and the third bit d3.
The selection circuit EXS10 outputs, as the selection voltage T2, the selection voltage L1, L8, L4, or L5 supplied from the selection circuit EXS8, or the selection voltage L2, L7, L3, or L6 supplied from the selection circuit EXS9, according to the second bit d2 and the first bit d1.
According to the configuration shown in
Therefore, according to the second decoder DE2 shown in
The decoder DEC shown in
In Examples 1 to 4 described above, in order to convert each of the n pixel data pieces into an analog voltage value, n DA conversion circuits (DA1 to DAn) each having the configuration shown in
However, the use thereof is not limited to DA conversion for pixel data pieces, and a configuration including a DA conversion circuit and a Gray code conversion circuit as shown in
As shown in
The Gray code conversion circuit 130a receives a series DIN of digital data pieces composed of binary codes, and supplies a series IDG of Gray code data pieces obtained by converting each of the digital data pieces into a Gray code to the decoder DECa. The decoder DECa includes the first decoder DE1 and the second decoder DE2 shown in
The decoder DECa selects two reference voltages including an overlap from the reference voltages V0 to Vx based on each Gray code data piece in the series IDG of Gray code data pieces by the operations of the first decoder DE1 and the second decoder DE2 described above. Then, the decoder DECa supplies the two selected reference voltages as selection voltages T1 and T2 to the non-inverting input terminals +A1 and +A2 of the amplifier circuit APa. The amplifier circuit APa generates an output voltage Vout by amplifying a voltage obtained by interpolating the selection voltage T1 and the selection voltage T2, by a weighting ratio assigned to the non-inverting input terminals +A1 and +A2.
In short, such a single DA conversion device 300 or the DA conversion device included in the data driver 13 of the display device 200 may include the following Gray code conversion circuit, decoder, and amplifier circuit.
The Gray code conversion circuit (130, 130a) receives digital data pieces composed of binary codes to be converted, and generates Gray code data pieces (VDG, IDG) by converting the digital data pieces into Gray codes.
The decoder (DEC, DECa) receives a plurality of reference voltages (V0 to Vx) having different voltage values and the Gray code data pieces, selects two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputs the same as first and second selection voltages, respectively.
The amplifier circuit (AP1, APa) has first and second input terminals (+A1, +A2), receives the above-mentioned first and second selection voltages at the first and second input terminals, and generates an output voltage by amplifying a voltage obtained by interpolating the first selection voltage and the second selection voltage, by a weighting ratio assigned to the first and second input terminals.
In the example shown in
Although the DA conversion circuit (DECa, APa) shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-170545 | Sep 2023 | JP | national |
