DIGITAL-TO-ANALOG CONVERSION UNIT, DRIVING APPARATUS AND PANEL DISPLAY APPARATUS USING THE SAME

Abstract

A digital-to-analog conversion unit, and a driving apparatus and a panel display apparatus using the same are provided. A driving voltage output from the digital-to-analog conversion unit can be a positive polarity voltage or a negative polarity voltage, wherein the driving voltage output from an output buffer is a positive polarity voltage and the driving voltage output from an output inverter is a negative polarity voltage. The apparatus only needs one set of grayscale voltage so that the layout area of the apparatus, and the flicker and the residual images of the display panel can be reduced.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of a conventional dot inversion driving method.

FIG. 2 is a timing diagram for a driving voltage of a conventional source driver.

FIG. 3 is a block diagram of a main structure for a conventional source driver.

FIG. 4 is a block diagram of the internal details of the conventional source driver in FIG. 3.

FIG. 5 is a detailed circuit diagram of a conventional grayscale voltage generator.

FIG. 6 is a schematic view of an analog voltage wiring to each source driver.

FIG. 7 is a detailed circuit diagram of a conventional analog voltage generator.

FIG. 8 is a voltage level diagram for an analog voltage of a conventional source driver with respect to the common voltage.

FIG. 9 is a timing diagram of a driving voltage according to an embodiment of the present invention.

FIG. 10 is a block diagram of a main structure of a driving apparatus according to a preferred embodiment of the present invention.

FIG. 11 is a block diagram of the internal details of the driving apparatus in FIG. 10.

FIGS. 12A and 12B are the detailed circuit diagram of a reference voltage generator and an analog voltage generator according to a preferred embodiment of the present invention.

FIG. 13 is a voltage level diagram for an analog voltage and a driving voltage with respect to the common voltage according to a preferred embodiment of the present invention.

FIG. 14 is a detailed circuit diagram of an output inverter according to a preferred embodiment of the present invention.

FIG. 15 is a detailed circuit diagram of another output inverter according to a preferred embodiment of the present invention.

FIG. 16 is a panel display apparatus according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 9 is a timing diagram of a driving voltage according to an embodiment of the present invention. In order to facilitate the inversion effect of the liquid crystal, in the present embodiment, a common voltage Vcom is a ground level used to divide the voltage polarities of driving voltages. As shown in FIG. 9, when the driving voltage is higher than the common voltage Vcom, it is a positive polarity voltage (e.g., 7 V). On the contrary, when the driving voltage is lower than the common voltage Vcom, it is a negative polarity voltage (e.g., −7 V). The positive polarity voltage is also a positive voltage, and the negative polarity voltage is a negative voltage. Therefore, from another point of view, the driving voltage of the display panel is achieved in the present embodiment in a manner of a negative polarity voltage (negative voltage).

FIG. 10 is a block diagram of a main structure of a driving apparatus 900 of a display panel according to an embodiment of the present invention. Referring to FIG. 10, the driving apparatus 900 comprises a grayscale voltage generator 901, a data latch unit 902, a digital-to-analog conversion unit 903, and a switch device 904. The digital-to-analog conversion unit 903 is coupled to the data latch unit 902 and the grayscale voltage generator 901, and the switch device 904 is coupled to the digital-to-analog conversion unit 903. The data latch unit 902 outputs multiple M-bit digital data according to a latch result, and the grayscale voltage generator 901 generates 2^M grayscale voltages. The digital-to-analog conversion unit 903 converts the input M-bit digital data to corresponding driving voltages. Then, the driving voltages are switched to the desirable output channels Ch₁-Ch_2N by the switch device 904, wherein M is a positive integer.

Referring to FIG. 11, it is a detailed block diagram of the grayscale voltage generator 901, the digital-to-analog conversion unit 903, and the switch device 904. The digital-to-analog conversion unit 903 comprises 2N digital-to-analog converters DAC₁-DAC_2N, N output buffers BF₉₁-BF_9N, and N output inverters IN₉₁-IN_9N. The switch device 304 comprises 2N switches SW₁-SW_2N, wherein N is a positive integer. The grayscale voltage generator 901 is coupled to the digital-to-analog converters DAC₁-DAC_2N. The (2j−1)^th digital-to-analog converter DAC₁-DAC_2N is coupled to the (i)^th output buffer BF₉₁-BF_9N, and the (2i)^th digital-to-analog converter DAC₁-DAC_2N is coupled to the (i)^th output inverter IN₉₁-IN_9N, wherein i is an integer and 1≦i≦N. In addition, a first terminal of the (2j−1)^th switch SW₁-SW_2N is coupled to the (j)^th output buffer BF₉₁-BF_9N, and a second terminal of the (2j−1)^th switch SW₁-SW_2N is coupled to the (j)^th output inverter IN₉₁-IN_9N. A first terminal of the (2j)^th switch SW₁-SW_2N is coupled to the (j)^th output inverter IN₉₁-IN_9N, and the second terminal of the (2j)^th switch SW₁-SW_2N is coupled to the (j)^th output buffer BF₉₁-BF_9N. A third terminal of each of the switches SW₁-SW_2N outputs a driving voltage, wherein j is an integer and 1≦j≦N.

The grayscale voltage generator 901 provides the 2^M grayscale voltage to each of the digital-to-analog converters DAC₁-DAC_2N. The digital-to-analog converters DAC₁-DAC_2N are used to convert the M-bit digital data into corresponding grayscale voltages. Then, the output buffers BF₉₁-BF_9N amplify the output of the digital-to-analog converters DAC₁-DAC_2N, and the output inverters IN₉₁-IN_9N are used to invert the voltage polarities of the voltages output by the digital-to-analog converters DAC₁-DAC_2N. In the embodiment, the output buffers BF₉₁-BF_9N are used to output a positive polarity voltage (positive voltage), and the output inverters IN₉₁-IN_9N are used to output a negative polarity voltage (negative voltage). Therefore, the same one of the output channels Ch₁-Ch_2N is switched by the switch device 904 for providing a positive polarity voltage or a negative polarity voltage.

For example, in a first time period, the odd-numbered output channels (Ch1, Ch3, . . . , Ch_2N−1) are required to output a positive polarity voltage, and the even-numbered output channels (Ch2, Ch4, . . . , Ch_2N) are required to output a negative polarity voltage. After being switched by the switch device 904, the odd-numbered output channels (Ch1, Ch3, . . . , Ch_2N−1) are coupled to the output of the output buffers BF₉₁-BF_9N, for example, indicated by the arrow 1101 in FIG. 11. The even-numbered output channels (Ch2, Ch4, . . . , Ch_2N) are coupled to the output of the output inverters IN₉₁-IN_9N. On the contrary, in a second time period, i.e., the next frame period, the polarities of the driving voltage in the same channel are required to be converted. At this time, after being switched by the switch device 904, the odd-numbered output channels (Ch1, Ch3, . . . , Ch_2N−1) are coupled to the output of the output inverters IN₉₁-IN_9N, for example, indicated by the arrow 1102 in FIG. 11. The even-numbered output channels (Ch2, Ch4, . . . , Ch_2N) are coupled to the output of the output buffers BF₉₁-BF_9N. Therefore, the digital-to-analog conversion unit 903 generates positive/negative polarity voltages from the same output channel by the switch device 904 switching the output thereof.

Compared with a conventional architecture, the grayscale voltage generator 901 only needs to generate one set of grayscale voltages, such that the circuit layout area is significantly reduced. For example, the grayscale voltage generator in a source driver of a conventional 8-bit display panel is required to generate the grayscale voltages with positive/negative polarities. Under this condition, as shown in FIGS. 5-7, the conventional grayscale voltage generator must generate two sets of grayscale voltages (V_G0+-V_G255+ and V_G0−-V_G255−), and two sets of analog voltages (V_A1-V_A8 and V_A9-V_A16) must be supplied to the grayscale voltage generator. Comparatively, the conventional source driver requires a large number of voltage-divider resistors R₁-R₅₁₀ therein, and a large number of analog voltage wirings connected to the external analog voltage generator 601. However, in the present embodiment, as shown in FIGS. 12A and 12B, the grayscale voltage generator in the source driver of the 8-bit display panel is required to generate only one set of grayscale voltages (V_G0-V_B255), and correspondingly is required to supply only one set of analog voltages (V_A1-V_A8) to the reference voltage generator 901. Therefore, in the circuit layout, not only the number of the voltage-divider resistors in the present embodiment is reduced, but also the consumption of the analog voltage wirings is also reduced.

Besides, as shown in FIG. 13, only one set of analog voltages (V_A21-V_A28) is required to be supplied to the reference voltage generator 901 in the present embodiment. Therefore, the grayscale voltages obtained from the reference voltages (V_A21-V_A28), the negative polarity voltages (V_dr1−-V_dr8−) obtained from the output inverters, and positive polarity voltages (V_dr1+-V_dr8+) obtained from the output buffers are considered with respect to the common voltage Vcom. The voltage difference of the positive/negative polarity voltage (V_dr1+ and V_dr1−, . . . , V_dr8+ and V_dr8−) of the same grayscale display with respect to the common voltage Vcom is not similar to that of the conventional architecture, and the circumstance that the offset of the analog voltages (V_A21-V_A28) results in the phenomena of the flicker and residual images will not occur.

FIG. 14 is a detailed circuit diagram of an output inverter according to an embodiment of the present invention, which comprises amplifiers 1401 and 1402, and resistors R₁₄₀₁ and R₁₄₀₂. For the convenience of illustration, the node voltage V₁₄ is marked. A first terminal of the resistor R₁₄₀₁ receives an input voltage V_in14. A first input terminal of the amplifier 1401 is coupled to a second terminal of the resistor R₁₄₀₁ and a first terminal of the resistor R₁₄₀₂, and a second input terminal of the amplifier 1401 is coupled to the ground. A second terminal of the resistor R₁₄₀₂ is coupled to an output of the amplifier 1401. A second input terminal of the amplifier 1402 is coupled to the output of the amplifier 1401. A first input terminal of the amplifier 1402 is electrically connected to an output of the amplifier 1402. In the present embodiment, the output inverter is used to output a negative polarity voltage, i.e., the negative voltage. Therefore, the resistors R₁₄₀₁, R₁₄₀₂ and the amplifier 1401 form an inverting amplifier architecture in the present embodiment for generating a negative voltage, expressed by Equation (1):

$\begin{array}{cc}{V}_{14}=-\frac{R_{1402}}{R_{1401}}V_{\mathrm{in}14}=V_{\mathrm{out}14}.& \left(1\right)\end{array}$

At this time, the negative voltage, i.e., node voltage V₁₄, is output to the switch set 904 via the single gain buffer stage formed by the amplifier 1402, and thus the output voltage V_out14 is also expressed by Equation (1) which has a voltage polarity being opposite to that of the input voltage V_in14. The output inverter operates between the common voltage Vcom and the negative voltage Vee. Comparatively, the output buffer operates between the positive voltage and the common voltage Vcom. The absolute values of the positive voltage and the negative voltage Vee are equal.

Another embodiment of the output inverter is illustrated as follows. As shown in FIG. 15, the output inverter comprises amplifiers 1501 and 1502, resistors R₁₅₅₁-R₁₅₀₄, and a variable resistor R₁₅₀₅. For the convenience of illustration, the node voltages V₁₅ and V_REF are marked herein. A first terminal of the resistor R₁₅₀₁ receives an input voltage V_in15. A first input terminal of the amplifier 1501 is coupled to a second terminal of the resistor R₁₅₀₁ and a first terminal of the resistor R₁₅₀₂, and a second input terminal of the amplifier 1501 is coupled to a second terminal of the resistor R₁₅₀₃. A first terminal of the variable resistor R₁₅₀₅ is coupled to the second terminal of the resistor R₁₅₀₃, and a second terminal of the variable resistor R₁₅₀₅ is coupled to a first terminal of the resistor R₁₅₀₄. The second terminal of the resistor R₁₅₀₂ is coupled to an output of the amplifier 1501. A second input terminal of the amplifier 1502 is coupled to the output of the amplifier 1501, and a first input terminal of the amplifier 1502 is electrically connected to an output of the amplifier 1502. The output inverter in the present embodiment is substantially the same as that of FIG. 14 in terms of the working principle and architecture. The amplifier 1501 and resistors R₁₅₀₁, R₁₅₀₂ form an inverting amplifier architecture in the present embodiment, so as to generate the node voltage V₁₅ with the polarity opposite to that of the input voltage V_in15, and then output the node voltages V₁₅ via the single gain buffer stage formed by the amplifier 1502. Compared with the above embodiment, the most significant difference lies in that the second input terminal of the amplifier 1501 for forming the inverting amplifier architecture is not coupled to the ground, but is biased at the node voltage V_REF. Therefore, the value of the node voltage V₁₅ is expressed by Equation (2), and besides being relevant to the resistors R₁₅₀₁, R₁₅₀₂, the node voltage V_REF is also one of the variable factors:

$\begin{array}{cc}{V}_{15}=-\frac{R_{1502}}{R_{1501}}\left(V_{\mathrm{in}15}-V_{\mathrm{REF}}\right)+V_{\mathrm{REF}}=V_{\mathrm{out}15}.& \left(2\right)\end{array}$

Herein, the voltage bias of the panel caused by the feed-through effect can be adjusted by fine tuning the node voltage V_REF. The value of the node voltage V_REF can be adjusted by the variable resistor R₁₅₀₅, and the reference voltages V_REF1501 and V_REF1502 can be defined according to the actual requirements of the panel.

In another aspect, the present invention further provides a panel display apparatus. As shown in FIG. 16, the panel display apparatus comprises a display panel 1601, a gate driving circuit 1602, and a driving apparatus 900. The gate driving circuit 1602 is electrically connected to the display panel 1601, and the driving apparatus 900 is electrically connected to the display panel 1601 through the output channels Ch1-Ch4. In the present embodiment, a panel display apparatus is achieved by the driving apparatus 900 of the embodiment of FIG. 10 according to the spirit of the present invention. The gate driving circuit 1602 is used to output at least a scan signal, so as to allow the driving apparatus 900 to provide at least a first driving voltage and a second driving voltage through the output channels Ch1-Ch4 in accordance with the scan signal. The first driving voltage and the second driving voltage are generated by first using the grayscale voltage generator 901 to generate multiple grayscale voltages with the same voltage polarity. Then, the digital-to-analog conversion unit 903 coupled to the grayscale voltage generator 901 determines whether or not to convert the grayscale voltages according to the received digital data, thereby providing the first driving voltage and the second driving voltage with opposite voltage polarities. Finally, the switch device 904 coupled to the digital-to-analog conversion unit 903 is used to switch the first driving voltage and the second driving voltage to the paths of the output channels Ch1-Ch4, wherein two adjacent output channels individually provide two voltages with different voltage polarities respectively (for example, the output channel Ch1 provides the first driving voltage, and the output channel Ch2 provides the second driving voltage). As for each of the output channels Ch1-Ch4, if a first driving voltage is provided in a frame period, a second driving voltage is provided in the next frame period. The above first driving voltage is a positive polarity voltage, and the second driving voltage is a negative polarity voltage. The detailed block diagram of the driving apparatus 900 and the relevant internal circuits are included in the embodiments of FIG. 11, FIG. 14, and FIG. 15.

To sum up, the output inverter is utilized as a main mechanism for inverting the voltage polarity in the present invention, such that the driving voltage output by the digital-to-analog conversion unit can be a positive polarity voltage or a negative polarity voltage. Thus, when the grayscale voltages supplied to the digital-to-analog conversion unit are reduced, the layout area of the driving apparatus of the display panel is effectively reduced, and the phenomena of the flicker and residual images of the display panel can also be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations thereof provided they fall within the scope of the following claims.

Claims

1. A driving apparatus for use in a display panel, comprising: a plurality of output channels for providing a first driving voltage and a second driving voltage;a data latch unit for outputting multiple M-bit digital data, wherein M is a positive integer;a grayscale voltage generator for generating 2M grayscale voltages, wherein the voltage polarities of the grayscale voltages are the same;a digital-to-analog conversion unit, coupled to the data latch unit and the grayscale voltage generator, comprising:a first digital-to-analog converter coupled to the data latch unit and the grayscale voltage generator;a second digital-to-analog converter coupled to the data latch unit and the grayscale voltage generator;an output buffer, coupled to the first digital-to-analog converter, for outputting the first driving voltage; andan output inverter, coupled to the second digital-to-analog converter, for outputting the second driving voltage;a switch device, coupled to the digital-to-analog conversion unit, for switching the first driving voltage and the second driving voltage to the paths of the output channels, wherein if the output channel provides the first driving voltage in a frame period, the output channel provides the second driving voltage in the next frame period.

2. The driving apparatus of claim 1, wherein the switch device comprises: a first switch having a first terminal coupled to the output buffer and a second terminal coupled to the output inverter, wherein in a first time period, the first terminal and a third terminal of the first switch are conducted, and in a second time period, the second terminal and the third terminal of the first switch are conducted; anda second switch having a first terminal coupled to the output inverter and a second terminal coupled to the output buffer, wherein in the first time period, the first terminal and a third terminal of the second switch are conducted, and in the second time period, the second terminal and the third terminal of the second switch are conducted.

3. The driving apparatus of claim 1, wherein the output inverter comprises: a first resistor;a first amplifier having a first input terminal coupled to a second terminal of the first resistor, and a second input terminal of the first amplifier coupled to the ground;a second resistor having a first terminal coupled to the first input terminal of the first amplifier, and a second terminal coupled to an output of the first amplifier; anda second amplifier having a first input terminal electrically connected to an output of the second amplifier, and a second input terminal coupled to the output of the first amplifier.

4. The driving apparatus of claim 1, wherein the output inverter comprises: a third resistor;a third amplifier having a first input terminal coupled to a second terminal of the third resistor;a fourth resistor having a first terminal coupled to the first input terminal of the third amplifier, and a second terminal coupled to an output of the third amplifier;a fifth resistor having a second terminal coupled to a second input terminal of the third amplifier;a variable resistor having a first terminal coupled to the second terminal of the fifth resistor;a sixth resistor having a first terminal coupled to a second terminal of the variable resistor; anda fourth amplifier having a first input terminal electrically connected to an output of the fourth amplifier, and a second input terminal coupled to the output of the third amplifier.

5. The driving apparatus of claim 1, wherein the voltage polarities of the first driving voltage and the second driving voltage are opposite.

6. The driving apparatus of claim 1, wherein the first driving voltage is a positive polarity voltage, and the second driving voltage is a negative polarity voltage.

7. The driving apparatus of claim 1, wherein the voltage polarities of the first driving voltage and the second driving voltage are determined depending on a common voltage.

8. The driving apparatus of claim 7, wherein the common voltage is a ground level.

9. The driving apparatus of claim 7, wherein the output buffer operates between the common voltage and a first voltage, and the output inverter operates between a second voltage and the common voltage.

10. The driving apparatus of claim 9, wherein the first voltage is a positive voltage, the second voltage is a negative voltage, and the absolute values of the first voltage and the second voltage are equal.

11. A digital-to-analog conversion unit, comprising: 2N digital-to-analog converters, wherein N is a positive integer;N output buffers having the (i)th output buffer coupled to the (2i−1)th digital-to-analog converter, wherein i is an integer and 1≦i≦N, and each of the output buffers individually outputs a first driving voltage; andN output inverters having the (i)th output inverter coupled to the (2i)th digital-to-analog converter, wherein each of the output inverters individually outputs a second driving voltage;wherein the voltage polarities of the first driving voltage and the second driving voltage are opposite.

12. The digital-to-analog conversion unit as claimed in claim 11, wherein each of the output inverters comprises: a first resistor;a first amplifier having a first input terminal coupled to a second terminal of the first resistor, and a second input terminal coupled to the ground;a second resistor having a first terminal coupled to the first input terminal of the first amplifier, and a second terminal coupled to an output of the first amplifier; anda second amplifier having a first input terminal electrically connected to an output of the second amplifier, and a second input terminal coupled to the output of the first amplifier.

13. The digital-to-analog conversion unit as claimed in claim 11, wherein each of the output inverters comprises: a third resistor;a third amplifier having a first input terminal coupled to a second terminal of the third resistor;a fourth resistor having a first terminal coupled to the first input terminal of the third amplifier, and a second terminal coupled to an output of the third amplifier;a fifth resistor having a second terminal coupled to a second input terminal of the third amplifier;a variable resistor having a first terminal coupled to the second terminal of the fifth resistor;a sixth resistor having a first terminal coupled to a second terminal of the variable resistor; anda fourth amplifier having a first input terminal electrically connected to an output of the fourth amplifier, and a second input terminal coupled to the output of the third amplifier.

14. The digital-to-analog conversion unit as claimed in claim 11, wherein the first driving voltage is a positive polarity voltage, and the second driving voltage is a negative polarity voltage.

15. The digital-to-analog conversion unit as claimed in claim 11, wherein the voltage polarities of the first driving voltage and the second driving voltage are determined depending on a common voltage.

16. The digital-to-analog conversion unit as claimed in claim 15, wherein the common voltage is a ground level.

17. The digital-to-analog conversion unit as claimed in claim 15, wherein the output buffers operate between the common voltage and a first voltage, and the output inverters operate between a second voltage and the common voltage.

18. The digital-to-analog conversion unit as claimed in claim 17, wherein the first voltage is a positive voltage, the second voltage is a negative voltage, and the absolute values of the first voltage and the second voltage are equal.

19. A panel display apparatus, comprising: a display panel;a gate driving circuit, electrically connected to the display panel, for outputting at least a scan signal; anda driving apparatus, electrically connected to the display panel through multiple output channels, for providing at least a first driving voltage and a second driving voltage through the output channels in accordance with the scan signal, wherein the driving apparatus comprises:a grayscale voltage generator for generating multiple grayscale voltages with the same voltage polarity; anda digital-to-analog conversion unit, coupled to the grayscale voltage generator, for determining whether or not to inverse the grayscale voltages according to the digital data received by the digital-to-analog conversion unit, and further at least providing the first driving voltage and the second driving voltage, wherein the voltage polarities of the first driving voltage and the second driving voltage are opposite; anda switch device, coupled to the digital-to-analog conversion unit, for switching the first driving voltage and the second driving voltage to the paths of the output channels, wherein, if the output channel provides the first driving voltage in a frame period, the output channel provides the second driving voltage in the next frame period.

20. The panel display apparatus as claimed in claim 19, wherein the digital-to-analog conversion unit comprises: a first digital-to-analog converter electrically coupled to the grayscale voltage generator;a second digital-to-analog converter electrically coupled to the grayscale voltage generator;an output buffer, coupled to the first digital-to-analog converter, for outputting the first driving voltage; andan output inverter, coupled to the second digital-to-analog converter, for outputting the second driving voltage.

21. The panel display apparatus as claimed in claim 20, wherein the switch device comprises: a first switch, having a first terminal coupled to the output buffer, and a second terminal coupled to the output inverter, wherein, in a first time period, the first terminal and a third terminal of the first switch are conducted, and in a second time period, the second terminal and the third terminal of the first switch are conducted; anda second switch having a first terminal coupled to the output inverter, and a second terminal coupled to the output buffer, wherein, in the first time period, the first terminal and a third terminal of the second switch are conducted, and in the second time period, the second terminal and the third terminal of the second switch are conducted.

22. The panel display apparatus as claimed in claim 19, wherein the first driving voltage is a positive polarity voltage, and the second driving voltage is a negative polarity voltage.

23. The panel display apparatus as claimed in claim 19, wherein the voltage polarities of the first driving voltage and the second driving voltage are determined depending on a common voltage.

24. The panel display apparatus as claimed in claim 23, wherein the common voltage is a ground level.