Claims
- 1. A method, comprising:
forming a current source with first and second transistors; producing a smaller output current with the first transistor than with the second transistor; inputting a reference voltage to the first transistor to adjust an output current produced by the current source; and adjusting the output current of the current source until a desired output current is achieved based on the reference voltage.
- 2. The method of claim 1, wherein the producing step comprises providing the first transistor with smaller dimensions than the second transistor.
- 3. The method of claim 1, wherein the inputting step comprises providing the reference voltage to a gate of the first transistor.
- 4. The method of claim 1, further comprising the step of providing a fixed gate voltage to the second transistor.
- 5. The method of claim 1, further comprising converting a reference current from a reference current source to generate the reference voltage.
- 6. The method of claim 1, further comprising forming an array of current sources and cyclically performing the producing, inputting, and adjusting steps for each current source in the array of current sources.
- 7. The method of claim 1, wherein the current source is calibrated by performing the producing, inputting, and adjusting steps.
Priority Claims (1)
Number |
Date |
Country |
Kind |
0111313.3 |
May 2001 |
GB |
|
CROSS REFERENCE TO RELATED APPLICATION
[0001] This patent application is a continuation of U.S. patent Ser. No. 10/326,168 (now U.S. Patent No.), filed Dec. 23, 2002, which is a continuation of Ser. No. 09/908,569, filed Jul. 20, 2001 (now U.S. Pat. No. 6,501,402), which are both incorporated herein by reference in their entireties.
Continuations (2)
|
Number |
Date |
Country |
Parent |
10326168 |
Dec 2002 |
US |
Child |
10835402 |
Apr 2004 |
US |
Parent |
09908569 |
Jul 2001 |
US |
Child |
10835402 |
Apr 2004 |
US |