The technology described in this patent document relates generally to video and data communications. More particularly, the technology relates to digital video cable drivers.
A digital video cable driver is used to transmit digital video signals over a transmission medium. When used in the motion picture or television industries the operating parameters of a digital video cable driver must typically comply with the standards published by the Society of Motion Picture and Television Engineering (SMPTE). Many video cable drivers employ a standard differential amplifier circuit having a differential pair of transistors in the output stage. This configuration is often used because of its simplicity and its inherent symmetry. However, when a large output swing is desired, such as in SMPTE applications, a cable driver with a standard differential amplifier circuit often has supply headroom issues, particularly when employing nanometer technologies. It would thus be advantageous to provide a digital video cable driver with more headroom at lower supply voltages.
In accordance with the teachings described herein, a digital video cable driver is provided that includes an input stage, an output stage and an amplification stage. The input stage converts a pair of differential input voltages into a control current. The output stage generates a digital output voltage for transmission over a cable. The amplification stage responds to the control current to control a voltage swing of the digital output voltage as a function of the control current. The amplification stage may include a transistor circuit that varies the digital output voltage in proportion to variations in the control current to cause the voltage swing, wherein the control current causes one or more transistors in the transistor circuit to remain in the linear region during operation of the digital video cable driver.
The input stage converts the differential input voltages (VIN1 and VIN2) into the control current (IC). The differential input voltages (VIN1 and VIN2) vary the control current (IC) as a function of the difference between the currents generated by the first current source (I1) and the second current source (I2). Specifically, when the first input voltage (VIN1) is in a logic high state (causing M1 to turn on) and the second input voltage (VIN2) is in a logic low state (causing M2 to turn off), then the control current (IC) is equal to the current generated by the first current source (I1). When the first input voltage (VIN1) is in a logic low state (causing M1 to turn off) and the second input voltage (VIN2) is in a logic high state (causing M2 to turn on), then the control current (IC) is limited by the second current source (I2), such that the control current is equal to the difference between the first and second current sources (IC=I1−I2).
The control current (IC) is coupled to the gate terminals of the transistor pair 40, 42 (M3 and M4) in the amplification stage. In addition, the control current (IC) is input to the source terminal of transistor M3, and the drain terminal of transistor M4 is coupled to the output node (VOUT) of the cable driver 30. Thus, the control current (IC) passes through the current carrying terminals of transistor M3 and is amplified by a gain (M) through the current carrying terminals of transistor M4. As a result, variations in the control current (IC) are reflected in the amplified current through transistor M4, which controls the voltage swing of the digital output voltage (VOUT).
In order to achieve a high data rate (e.g., for GHz operation), currents I1 and I2 are selected to prevent the transistors M3 and M4 in the amplification stage from staying in the linear region. That is, the difference between I1 and I2 is large enough that the control current (IC) during a logic level “1” (VOUT-High) is high enough to keep the transistors M3 and M4 in a saturated state.
An eye diagram 50 of the digital output voltage (VOUT) is illustrated at
Unloaded Condition:
V
AMP(unloaded)=I2*M*RL
V
OUT-HIGH(unloaded)=VDD−(I1−I2)*M*RL
V
OUT-LOW(unloaded)=VDD−I1*M*RL
Loaded Condition:
V
AMP(loaded)=I2*M*RL/2
V
OUT-HIGH(loaded)=VOUT-HIGH(unloaded)−VAMP(unloaded)/2+VAMP(loaded)/2
VOUT-LOW(loaded)=VOUT-HIGH(unloaded)−VAMP(unloaded)/2−VAMP(loaded)/2
To illustrate the operation of the cable driver 30, consider an example in which the following values are implemented in the circuit 30:
VDD=2.5V
M=2.5
I1=9.6 mA
I2=8.8 mA
RL=750Ω
In the above example, the resultant output voltage swing (VAMP) and digital output voltages (VOUT) are as follows:
Unloaded Condition:
VAMP(unloaded)=1.65 V
VOUT-HIGH(unloaded)=2.35 V
VOUT-LOW(unloaded)=0.70 V
Loaded Condition:
VAMP(loaded)=0.825 V
VOUT-HIGH(loaded)=1.938 V
VOUT-LOW(loaded)=1.113 V
As shown above, the output voltage swing (VAMP) in this example is 1.65 V when the circuit 30 is unloaded, and when terminated to a load (RL) through an ac-coupling capacitor (CL), the circuit results in a 825 mVpp swing. Significantly, this example configuration provides the 800 mV swing required by the SMPTE standards at the relatively low source voltage (VDD) of 2.5 V. Other advantages over a typical differential cable driver circuit may also be achieved by the digital video cable driver 30 architecture shown in
For instance, the use of a current folding circuit utilizing NMOS transistors provides additional headroom in comparison to a typical cable driver circuit with a differential output stage and enables the circuit to be integrated into CMOS, reducing the overall BOM cost of an SMPTE compliant driver. With this additional headroom, 900 mVpp-1000 mVpp output voltage swings are achievable within the constraints of a 2.5 V supply. In addition, the increased headroom allows for the use of a smaller transistor at the output stage. Further, by operating farther into the linear region due to the extra headroom, the sensitivity of the supply voltage on return loss may be reduced.
In addition, the provision of a digital output stage, along with the potential for integration into CMOS, provides the ability to turn off the amplification stage when there is no active input, thus improving ORL. The output stage can easily be placed in a power down mode, without any additional circuitry, by forcing the output to be in a logic high state causing the current drawn from the output state to be very low. Other advantages over a typical differential cable driver may include improved power consumption, a reduction in the necessary silicon footprint, and the availability of multiple positive outputs (see, e.g.,
In this example, the current folding circuit in the input stage varies the control current (IC) through the amplification stage as a function of the differential input voltages (VIN1 and VIN2). Specifically, when the first input voltage (VIN1) is in a logic low state (causing M1 to turn on) and the second input voltage (VIN2) is in a logic high state (causing M2 to turn off), then the control current (IC) is equal to the current generated by the first current source (I1). When the first input voltage (VIN1) is in a logic high state (causing M1 to turn off) and the second input voltage (VIN2) is in a logic low state (causing M2 to turn on), then the control current (IC) is limited by the second current source (I2), such that the control current (IC) is equal to the difference between the first and second current sources (IC=I1−I2).
The control current (IC) is coupled to the gate terminals of the transistor pair 80, 82 (M3 and M4) in the amplification stage. In addition, the control current (IC) controls the current flow through the current carrying terminals of transistor M3, which is reflected in the amplified current through transistor M4. Variations in the control current (IC) thus control the voltage swing of the digital output voltage (VOUT) at the drain terminal of transistor M4.
The input stage in this example operates the same as the input stage in the example of
This written description uses examples to disclose the invention, including the best mode, and also to enable a person skilled in the art to make and use the invention. The patentable scope of the invention may include other examples that occur to those skilled in the art. For example, other embodiments could include one or more bipolar transistors or a combination of biplolar and CMOS transistors.