Digital video decoder and method of decoding a digital video signal

Abstract

A digital video decoder and method therefor receives a digital video signal and performs motion compensation on the digital video signal in the frequency domain. The motion compensation is performed by forming, for each inter-coded picture in the digital video signal, a composite picture in the frequency domain representing a reference picture corresponding to the inter-coded picture, and then adding the composite picture to the corresponding inter-coded picture. Each macro block of the composite picture is formed based on corresponding macro blocks of at least one anchor picture stored in memory. The anchor pictures are stored as compressed bits via quantization and variable length coding of frequency domain blocks to reduce required memory capacity. The synthesis technique employed by the compositor to form the composite macro blocks accounts for both field and frame motion compensation with half-pel accuracy. The intra-coded pictures produced as a result of the motion compensation are then reformatted in a display order.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for decoding a digital video signal.

2. Description of the Related Art

Digital video signal processing is an area of science and engineering that has developed rapidly over the past decade. The maturity of the moving Picture Expert Group (MPEG) video coding standard represents a very important achievement for the video industry and provides strong support for digital compression and other techniques such as digital modulation and packetization, a s well as VLSI technology, the fundamentals of television have been reinvented for the digital age.

The first U.S. digital television transmission standard developed for broadcast of high and low definition television by a Grand Alliance of companies has been proposed to the Federal Communications Commission (FCC). High definition digital television broadcasts are typically referred to as HDTV, while low definition digital television broadcasts are generally referred to as SDTV. These terms will be used throughout this application, but are not tied to a particular format or standard. Instead, these terms are used to cover the high and low definition digital television of any coding standard (e.g., such as for VTRs and television).

In 1994 SDTV broadcasts became a reality when the first digital television services, broadcasted via satellite, went on the air. The Digital Satellite Service (DSS) units developed by Thomson Consumer Electronics, etc. have been distributed to more than 1 million homes. The highly sophisticated methods of transmitting and receiving digital television not only produce higher-quality television broadcasts, but also create new services, such as movies on demand, interactive programming, multimedia applications as well as telephone and computer services through the television.

Soon, HDTV will become a reality and join SDTV. Accordingly, in the near future, expect advanced television (ATV) broadcasts which include co-existent broadcasts of HDTV and SDTV.

When performing, for example, MPEG video encoding of HDTV, image blocks of 8.times.8 pixels in the spatial domain are converted into 8.times.8 DCT (discrete cosine transform) blocks of DCT coefficients in the DCT or frequency domain. Specifically, in most coding formats such as MPEG, the HDTV signal is divided into a luminance component (Y) and two chroma components (U) and (V). Furthermore, instead of U and V chroma blocks, some standards use color difference signal chroma blocks. For the purposes of discussion only, U and V chroma blocks will be used. Most formats such as MPEG specify different encoding sequences. In each encoding sequence a sequence header identifies the encoding sequence. Furthermore, in each encoding sequence, macro blocks of 8.times.8 DCT blocks of DCT coefficients are formed.

Encoding sequences for HDTV typically include the 4:2:0 encoding sequence, the 4:2:2 encoding sequence, and the 4:4:4 encoding sequence. In the 4:2:0 encoding sequence a macro block consists of four 8.times.8 luminance DCT blocks, one 8.times.8 U chroma DCT block, and one 8.times.8 V chroma DCT block. In the 4:2:2 encoding sequence a macro block consists of four 8.times.8 luminance DCT blocks, two 8.times.8 U chroma DCT blocks, and two 8.times.8 V chroma DCT blocks. Finally, in the 4:4:4 encoding sequences a macro block consists of four 8.times.8 luminance DCT blocks, four 8.times.8 U chroma DCT blocks, and four 8.times.8 V chroma DCT blocks. SDTV includes similar coding sequences, but the DCT blocks are 4.times.4 DCT blocks.

Besides variable length encoding, many standards such as MPEG provide for intra- and inter-coding. Intra-coding is where a field or frame of the digital video signal, referred to as a picture, is encoded based on the pixels therein. Several well known techniques exist for intra-coding. An intra-coded picture is typically referred to as an I-picture.

Inter-coding, sometimes referred to as predictive encoding, is where a picture is encoded based on a reference picture, referred to as an anchor picture. In inter-coding, each macro block (i.e., related luminance and chroma blocks) of the picture being encoded is compared with the macro blocks of the anchor picture to find the macro block of the anchor picture providing the greatest correlation therewith. The vector between the two macro blocks is then determined as the motion vector. The inter-coded digital video signal for the macro block being encoded will then include the motion vector and the differences between the macro block being encoded and the corresponding macro block of the anchor picture providing the greatest correlation.

For example, a series of pictures may have the display order I.sub.1 B.sub.1 B.sub.2 P.sub.1 B.sub.3 B.sub.4 P.sub.2 B.sub.5 B.sub.6 P.sub.3 B.sub.7 B.sub.8 I.sub.2 . . . . The transmitted HDTV signal, however, will have the pictures arranged in the order of encoding as follows: I.sub.1 P.sub.1 B.sub.1 B.sub.2 P.sub.2 B.sub.3 B.sub.4 P.sub.3 B.sub.5 B.sub.6 I.sub.2 B.sub.7 B.sub.8. P-pictures are encoded using the previous I-picture or P-picture as the anchor picture. In the above example, P-pictures P.sub.1, P.sub.2, and P.sub.3 were encoded using I-picture I.sub.1, P-picture P.sub.1, and P-picture P.sub.2, respectively, as the anchor picture.

The B-pictures may be forward encoded, backward encoded, or bi-directionally encoded. For instance, if B-picture B.sub.1 was encoded using I-picture I.sub.1 as the anchor picture, then B-picture B.sub.1 is backward or back encoded. Alternatively, if B-picture B.sub.1 was encoded using P-picture picture P.sub.1 as the anchor picture, then B-picture B.sub.1 is forward encoded. If B-picture B.sub.1 was encoded using both I-picture I.sub.1 and P-picture P.sub.1 (typically a weighted average thereof) as anchor pictures, then B-picture B.sub.1 is bi-directionally encoded.

The headers in the digital video signal indicate whether pictures are I, B, or P-pictures and the direction of encoding. These headers also indicate the group of picture (GOP) size N and the distance between anchor pictures M. The GOP size indicates the distance between I-pictures, which in the above example would be N=12. Since I-pictures and P-pictures are anchor pictures, the distance between anchor pictures in the above example would be M=3. Based on the information provided in the headers, the digital video signal can be properly decoded.

Unfortunately, conventional decoders must store two complete anchor pictures in the spatial domain to decode a digital video signal. Consequently, the memory requirements for conventional decoders are quite larger. Because the memory requirements of a digital decoder account for a large part of the overall device cost, the large memory requirements of conventional digital decoders adversely impacts the cost of such devices.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method and apparatus for decoding digital signals which overcomes the drawbacks of conventional decoders.

Another object of the present invention is to provide a method and apparatus for decoding digital signals which requires significantly less memory than conventional decoders.

The method and apparatus for decoding a digital video signal according to the present invention achieves the above objectives by decoding the digital video signal in the frequency domain. More specifically, in performing motion compensation to decode inter-coded pictures into intra-coded picture, the present invention stores two anchor pictures in the frequency domain as opposed to the spatial domain. Furthermore, the stored anchor picture shave been both quantized and variable length coded to further educe the amount of memory required to store the anchor pictures. The digital decoder further includes a compositer which produces composite macro blocks which, when added to an inter-coded macro block, form an intra-coded macro block. Using a synthesis technique which accounts for field and frame motion compensation, as well as, full and half-pel accuracy, the compositor forms the composite macro blocks entirely by processing anchor picture macro blocks in the frequency domain. Accordingly, the need for inverse frequency and frequency (e.g., DCT) converters has been eliminated.

The objectives of the present invention are achieved by providing an apparatus for decoding a digital video signal, comprising: motion compensation means for receiving a digital video signal and performing motion compensation on said digital video signal in the frequency domain; and a reformatter reformatting pictures in said digital video signal output by said motion compensation means such that said pictures are in a display order.

The objectives of the present invention are further achieved by providing a motion compensation means which forms, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said inter-coded picture to perform said motion compensation.

The objectives of the present invention are still further achieved by providing an apparatus for decoding a digital video signal, comprising: a converter receiving a digital video signal and converting, in the frequency domain, inter-coded pictures in said digital video signal into intra-coded in said digital video reformatter reformating pictures in said digital video signal output by said converter such that said pictures are in a display order.

The objectives of the present invention are also achieved by providing a method for decoding a digital video signal, comprising: (a) receiving a digital video signal; (b) performing motion compensation on said digital video signal in the frequency domain; and (c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order.

The objectives of the present invention are additionally achieved by providing the above method wherein step (b) comprises the steps of: (b1) forming, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture; and (b2) adding said composite picture to said inter-coded picture to perform said motion compensation.

The objectives of the present invention are further achieved by providing a method for decoding a digital video signal, comprising: (a) receiving a digital video signal; (b) converting, in the frequency domain, inter-coded pictures in said digital video signal into intra-coded pictures; and (c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order.

Other objects, features, and characteristics of the present invention; methods, operation, and functions of the related elements of the structure; combination of parts; and economies of manufacture will become apparent from the following detailed description of the preferred embodiments and accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 illustrates a conventional apparatus for decoding digital video signals;

FIG. 2 illustrates an apparatus, according to the present invention, for decoding digital video signals;

FIG. 3 illustrates an embodiment of the memory in the digital video signal decoder of FIG. 2;

FIGS. 4A-4D illustrate the formation of a composite macro block in the spatial domain; and

FIG. 5 illustrates a composite macro block with respect to anchor frame macro blocks.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

More particularly, with respect to the prior art, FIG. 1 illustrates a conventional decoder for decoding digital video signals. As shown in FIG. 1, a variable length decoder and dequantizer 10 receives a digital signal. A motion vector address generator 20 and an adder 18 are connected to the output of the variable length decoder and dequantizer 10. The motion vector address generator 20 sends output to a frame store 22. The frame store 22 has a first output connected to the adder 18 and a second output connected to the reformatter 24. Additionally, the frame store 22 has an input connected to the output of the adder 18. Besides the output of the frame store 22, the reformatter 24 also receives the output of the adder 18.

The operation of the conventional decoder illustrated in FIG. 1 will now be described. The variable length decoder and dequantizer 10 receives the digital video signal, and variable length decodes and dequantizes the digital video signal. The output of the VLD and dequantizer 10 is received by a motion vector address generator 20. The motion vector address generator 20 identifies the motion vectors for inter-coded pictures, and generates motion vector addresses corresponding thereto. The motion vector addresses are output to the frame store 22. The frame store 22 stores the two previous anchor pictures (e.g., I or P-pictures). The frame store 22 will output the macro blocks of an anchor picture addressed by the motion vector addresses. These macro blocks are received by an adder 18. The adder 18 also receives the output of the variable length decoder and dequantizer 10. Consequently, when a B or P-picture is being decoded, a complete I-picture can be obtained by adding the output of the variable length decoder and dequantizer 10, which represents the differences between the picture and an anchor picture, with the anchor picture to create a complete picture. When an I-picture is output from the variable length decoder and dequantizer 10, there is no need to add anchor picture information thereto, consequently the frame store 22 will not send output to the adder 18.

As discussed above, when B-pictures are bi-directionally encoded, a weighted average of two anchor frames is used to inter-code these pictures. The weighting is encoded into the motion vectors by the original encoder. When the frame store 22 receives the two motion vectors, the anchor frame macro blocks pointed thereby are averaged by the frame store 22 to form the weighted average macro block. The frame store 22 then outputs the weighted average macro block to the adder 18.

The frame store 22 also monitors the output of the output of the adder 18. When the frame store 22 determines that the adder 18 outputs an I or P-picture, the frame store 22 replaces the oldest stored anchor frame with the I or P-picture output by the adder 18.

The operation of forming I-pictures from B and P-pictures is referred to as motion compensation. When the pictures are frames, frame motion compensation is performed. When the pictures are fields, field motion compensation is performed. During original encodation, inter-coded even and odd fields are encoded independently based on either the even or odd fields of a previous frame.

The output of the adder 18 is received by a reformatter 24. The reformatter 24 is also connected to the frame store 22. Since the transmission, and therefore, reception order of the pictures is not in the proper display order, the reformatter 24 operates to reformat the order of the pictures into the proper display order.

To better understand the operation of the reformatter 24 illustrated in FIG. 1, assume that a digital video signal such as discussed above is received. The reformatter 24 determines what output should be sent as the decoded digital video signal according to the following rules: (1) if the picture received is the first anchor pictures received then no output will be sent; (2) if the picture received is an anchor picture but no the first anchor picture received, then the previously received anchor picture will be output; and (3) if the picture received is a B-picture, then the B-picture will be immediately output.

Therefore, upon receipt of I-picture I.sub.1, the reformatter 24 will not send any output. The next picture received will be P-picture P.sub.1. The adder 18 will then receive the output of the variable length decoder and dequantizer 10 and macro blocks from the I-picture I.sub.1 pointed to by the motion vectors detected by motion vector detector 20. Consequently, the adder 18 will generate a complete picture. Since this complete picture is an anchor picture, the frame store 22 will then store the complete picture P.sub.1. According to the rules discussed above, the reformatter 24 will then output from the frame store 22 the I-picture I.sub.1 (i.e., the previous anchor picture).

The next two pictures received are B-pictures B.sub.1 and B.sub.2. Complete pictures will be formed from these B-pictures in the same manner as discussed above with respect to P-picture P.sub.1, except that, depending on the direction of encoding, either the I-picture I.sub.1 and/or the P-picture P.sub.1 will be used as the anchor picture. Since the adder 18 outputs a B-picture, the reformatter 24 will immediately output the B-picture. Consequently, the output from the reformatter 24 will be I.sub.1 B.sub.1 B.sub.2.

Next, the P-picture P.sub.2 is received and processed in the same manner as P-picture P.sub.1. When the adder 18 outputs the complete P-picture P.sub.2, the frame store 22 will replace the I-picture I.sub.1 with the P-picture P.sub.2. The reformatter 24, according to the rules discussed above, will then output the P-picture P.sub.1. In this manner, the reformatter 24 will output the pictures in the proper display order.

As previously mentioned, the conventional digital video decoder of prior art FIG. 1 unfortunately requires storing two anchor pictures in the spatial domain to decode a digital video signal. Consequently, the memory requirement for the digital video decoder of FIG. 1 is quite large.

FIG. 2 illustrates an apparatus according to the present invention for decoding digital video signals. In contrast to the conventional digital video decoder of FIG. 1, the digital video decoder according to the present invention does not require memory capacity sufficient to store two anchor pictures in the spatial domain. Instead, the digital video decoder of FIG. 2 converts inter-coded pictures into I-pictures in the frequency or DCT domain.

Accordingly, the digital video decoder of FIG. 2 only requires storing two anchor pictures in the frequency domain. Additionally, the digital video decoder of FIG. 2 stores the variable length coded and quantized versions of these frequency domain anchor pictures. As a result, the memory requirements for storing these anchor pictures as compared to FIG. 1 are considerably reduced. The inventors estimate that the memory requirements of the digital video decoder of FIG. 2 are at least one-third less than the memory requirements for the prior art digital video decoder illustrated in FIG. 1. Since the requisite memory capacity for a digital video decoder is a large component of the cost therefore, this reduction in memory capacity results in a significant decrease in the cost of the resulting device.

The digital video decoder illustrated in FIG. 2 receives a digital video signal including intra-coded and inter-coded pictures, and outputs a digital video signal comprised of intra-coded pictures only. As illustrated in FIG. 2, the digital video signal to be decoded is received by a bit stream parser 60. A variable length decoder and dequantizer 58 receives one of the outputs of the bit stream parser 60. The variable length decoder and dequantizer 58 outputs pictures to an adder 74 and outputs motion vectors to a motion vector address generator 62. As indicated by dashed lines, the variable length decoder and dequantizer 58 outputs pictures to the adder 74 via an optional field-to-frame converter 69. Both the bit stream parser 60 and the motion vector address generator 62 supply output signals to an I and P-picture macro block bits memory 64 (hereinafter referred to as "memory 64"). A variable length decoder and dequantizer 67 is connected to an output of the memory 64, and has an output thereof connected to a compositer 68. Another variable length decoder and dequantizer 66 is connected to an output of the memory 64, and has an output thereof connected to the reformatter 78.

The compositer 68 also receives an output from the motion vector address generator 62. Besides receiving the output of the variable length decoder and dequantizer 58, the adder 74 also receives the output of the compositer 68. The output of the adder 74 is connected to the reformatter 78, and one of the outputs of the reformatter 78 serves as the output of the reformatter 78 is received by a quantizer 70 within the I-picture converter 76. A variable length encoder 72 is connected to the output of the quantizer 70, and a bit stream parser 59 is connected to the output of the variable length encoder 72. The bit stream parser 59 supplies another input of the memory 64.

It should be understood that in FIG. 2 the various data paths have been represented in greatly simplified form for clarity. In reality, many separate data paths into and out of the various components are required. Additionally, many data and control lines have been omitted entirely from FIG. 2 for clarity.

The operation of the embodiment illustrated in FIG. 2 will now be described. As discussed above, the digital video decoder receives a digital video signal, and converts all inter-coded pictures therein into I-pictures. For purposes of discussion, assume that the digital video signal to be decoded has the order of encodation as follows: I.sub.1 P.sub.1 B.sub.1 B.sub.2 P.sub.2 B.sub.3 B.sub.4 P.sub.3 B.sub.5 B.sub.6 I.sub.2 B.sub.7 b.sub.8, and when displayed, these pictures have the display order of I.sub.1 B.sub.1 B.sub.2 P.sub.1 B.sub.3 B.sub.4 P.sub.2 B.sub.5 B.sub.6 P.sub.3 B.sub.7 B.sub.8 I.sub.2.

As discussed above, a digital video signal including inter-coded pictures includes both picture data and a motion vector corresponding thereto. The bit stream parser 60 receives the digital video signal, and parses out the header information for each anchor picture. The header information includes the picture type, the picture timing stamp PTS, the slice header etc. The header information for each anchor picture is output by the bit stream parser 60 to the memory 64. The memory 64 stores the header information on a picture-by-picture basis. The bit stream parser 60 also outputs the digital video signal to the variable length decoder and dequantizer 58.

The variable length decoder and dequantizer 58 receives the digital video signal, variable length decodes and dequantizes the digital video signal, sends the decoded digital video signal to the adder 74, and sends the motion vectors to the motion vector address generator 62. When the pictures of the digital video signal could include fields, as opposed to, or in addition to frames, the digital video decoder includes a field-to-frame converter 69 which converts the separate even and odd fields for a frame into a single frame. This is accomplished by simple interlacing the even and odd fields.

As discussed in more detail below, the compositer 68 produces a composite macro block based on the output of the motion vector address generator 62 and the macro blocks output by the memory 64. The adder 74 adds the composite macro block to the macro block of the picture data currently output by the variable length decoder and dequantizer 58, or optionally the field-to-frame converter 69, to reconstruct a complete macro block. In this manner, both P-pictures and B-pictures are converted into I-pictures.

Of course, if an I-picture is currently being output by the variable length decoder and dequantizer 58, then the adder 74 will not receive anything from the compositer 68 to add thereto. The motion vector address generator 62 will have recognized the I-picture as an I-picture and disabled the compositer 68 from sending output to the adder 74.

As discussed in detail below, when the adder 74 outputs I-pictures or I-pictures which were formally P-pictures, the reformatter 78 outputs these anchor pictures to the memory 64 for storage via the quantizer 70, the variable length encoder 72, and the bit stream parser 59. The memory 64 only stores two anchor pictures at a time, and will replace the oldest stored anchor picture with the newly received anchor picture. Specifically, the I and P-pictures (i.e., anchor pictures) in I-picture format output from the reformatter 78 to the memory 64 are quantized by the quantizer 70, and variable length encoded by the variable length encoder 72.

Because variable length coding is lossless coding, only the distortion caused by the quantization step needs to be accounted for by the quantizer 70. Furthermore, tests have shown that if the quantizer 70 quantizes the anchor frames using the quantization scale determined by the original encoder, no noticeable distortion is introduced. The elimination of distortion, however, can be assured by performing quantization as discussed in detail below. Assuming that Q is the quantization scale determined by the original encoder, I is the intra macro block data before quantization and I' is the data after quantization, then ##EQU1## where the operation [.] is an integer operator, and I' can be seen as the reconstructed data.

Assume that Q.sub.r, is the quantizations scale used in the requantization, and I" is the data obtained after requantization, then ##EQU2## and, therefore, ##EQU3## In other words, if the requantization scale is chosen as an integer times the original quantization scale, requantization will not cause any additional distortion.

For uni-directionally inter-coded macro blocks (i.e., macro blocks from P-picture,

P'=I'+E', (4) where P' is the reconstructed data of the inter-coded macro block from the P-picture, I' represents the reconstructed reference data for motion-compensation (i.e., the composite macro block) and E' is the reconstructed prediction error (i.e., the macro block from the variable length decoder and dequantizer 58). Let Qi be the quantizer for I', Qp for P' and Qe for E', then expression (4) can be re-written as: ##EQU4## After requantization with quantizer scale Qr, ##EQU5## where P" is the requantized reconstructed data. Accordingly, ##EQU6## provided that both, ##EQU7## are satisfied. Therefore, if Qr is chosen according to the following expression, there is no additional distortion caused by the process of requantizing uni-directionally inter-coded macro blocks. Qr=GCD(Qi, QE), (9) where GCD stands for greatest common division. If the distortion eliminating equations are utilized by the quantizer 70, then the quantizer 70 may need to perform bit rate control to obtain the original bit rate of the digital video signal. This bit rate control can be performed using any well-known bit rate control technique.

Using the various headers within the digital video signal, the bit stream parser 59 identifies each macro block in an anchor picture. The bit stream parser 59 then separates the macro blocks for the anchor picture, and stores them in the memory 64. These anchor frames are stored in the DCT domain and have been variable length encoded and quantized. Consequently, the memory 64 can be much smaller than the memory needed to implement the frame store 22.

One possible embodiment of memory 64 is illustrates in FIG. 3. As shown in FIG. 3, the memory 64 resembles a memory stack. Each location in the memory stack only stores the data for one macro block. Because the macro blocks are variable length encoded and quantized, the macro blocks can be variable lengths. As illustrated, the macro block HB0 takes up only a portion of the first stack location, the same with macro blocks MB2 and MB2. The fourth macro block MB3, however, contains more data than a single stack location. In this instance, the macro block MB3 fills up an entire stack location and a portion of another stack location. The macro block MB4 following macro block MB3 is then stored in the next stack location. Accordingly, each macro block stored in the memory 64 will be stored beginning in a new stack location. In this manner, each macro block can be stored and retrieved independently of the other macro blocks. Preferably the memory 64 includes two such stacks for storing the macro blocks of two anchor frames. Alternatively, a single, large stack could be divided in half. Furthermore, the memory 64 links the macro blocks of an anchor picture to the previously stored header information therefor.

In the embodiment of FIG. 1, the macro blocks of the anchor pictures (I-pictures and P-pictures) used to form a complete picture were stored in the spatial domain. Accordingly, if the motion vectors caused a shift in the block structure of the anchor picture, the data for the new macro blocks could be easily obtained from the original macro block structure for the anchor picture as discussed in "Manipulation and Compositing of MC-DCT compressed Video" by Shih-Fu Chang, IEEE Journal on Selected Areas in Communication, Vol. 13, No. 1, January 1995 (hereinafter "the Chang article"); which is hereby incorporated by reference.

For instance, as discussed in the Chang article, FIG. 4A illustrates a macro block structure B shown by dashed lines and a macro block structure A illustrated by solid lines. Assume that the macro block structure B represents the macro block structure of an anchor picture stored in frame store memory 22 of FIG. 1, and that the macro block structure A represents the macro block structure as indicated by the motion vector supplied to the frame store memory 22. If the macro block indicated by the motion vector is the macro block indicated as B' in FIG. 4A, then the macro block is simply formed from the data of the four macro blocks in the macro block structure B such as shown in FIGS. 4B-4D. Since the macro blocks are stored in the spatial domain, that portion of the macro block structure B forming the macro block B' in the macro block structure A can simply be read out. Think of it as a picture on a display screen and a window is simply moved about that display screen.

By contrast, macro blocks in the frequency domain (i.e., DCT blocks) do not operate in the same fashion. Instead, the DCT coefficients represent different frequency components of the corresponding macro block in the spatial domain. Namely, the new macro block B' contains contributions from the lower left corner B.sub.13 of block B.sub.1, the lower right corner B.sub.24 of macro block B.sub.2, the upper right corner B.sub.31 of block B.sub.3 and the upper left corner B.sub.42 of macro block B.sub.4. While in the spatial domain, the four contributions can be supplemented by zeros as shown in FIG. 4C and added according to the equation B'=B.sub.13 +B.sub.24 +B.sub.31 +B.sub.42 as shown in FIG. 4D, this same method cannot be applied in the DCT domain. Instead, as discussed in the Chang article, the DCT macro block B' can be calculated according to the following expression: ##EQU8## where I.sub.h and I.sub.w are identity matrices with size h.times.h and w.times.w, respectively; and h and w are the number of rows and columns extracted.

Formation of Composite Macro Block

In a preferred embodiment, however, a different set of expressions is used to determine the composite macro block. First the formation of a composite macro block to perform frame-motion compensation will be described. Field-motion compensation will be described thereafter.

Frame-Motion Compensation Full Pixel Accuracy

FIG. 5 illustrates macro blocks a, b, c and d from the anchor frame in the spatial domain, and block e the macro block pointed to by the motion vector, albeit in the spatial domain. As shown in FIG. 5, the macro block e has an upper left hand coordinate of (m,n). The motion vector received by the motion vector address generator 62 points to this coordinate (m,n). Based on the motion vector, the motion vector address generator 62 instructs the memory 64 as to which macro blocks of the anchor frame to output to the compositer 68. The motion vector address generator 62 also outputs a signal to the compositer 68 indicating the coordinate (m,n).

Macro blocks a, b, c, d and e have the relationship shown below by expression (44). ##EQU9##

For instance, if (m,n=2,3) then whereas if (m,n)=(6,5) then ##EQU10##

Assume that arrays A, B, C, D and E are the corresponding DCT macro blocks of macro blocks a, b, c, d and e, respectively. Accordingly, E and e have the relationship shown in expression (12) below. ##EQU11##

Substituting a, b, c and d in for e in expression (12) based on expression (11) results in expression (13) below. ##EQU12##

Representing a, b, c and d with the corresponding DCT coefficients A, B, C and D, respectively, using expression (12) and substituting A, B, C, or D for E and a, b, c, or d for e results in expression (14) below. ##EQU13##

Changing the summing order and rewriting expression (14) results in expression (15) below. ##EQU14##

Expression (15) can be simplified to expression (16) below. ##EQU15## where M.sub.A, M.sub.B, M.sub.C and M.sub.D are the matrices which are independent of the DCT coefficients and only depend on the values of p, q, k, l, m and n. Therefore, matrices M.sub.A, M.sub.B, M.sub.C and M.sub.D can be precalculated according to the following expressions for 0.ltoreq.p, q, k, l<=7: ##EQU16##

Accordingly, using expressions (16) and (17a)-(17d), the DCT coefficients for the composite macro block E can be determined. As one skilled in the art will readily appreciate from the above disclosure, the expressions above provide a composite macro block for full pixel accuracy. In other words, the coordinate (m,n) is the coordinate for a pixel in the composite macro block e. The coordinate (m,n) does not, however, always fall on a pixel in a macro block of an anchor frame, Instead, this coordinate could fall between two pixels in the horizontal direction, between two pixels in the vertical direction, or between two pixels in the diagonal direction.

Frame-Motion Compensation--Half-Pel Accuracy Horizontal Half-Pel Accuracy

If coordinate (m,n) falls between two pixels in the horizontal direction, then motion compensation must be performed with half-pel (i.e., half pixel) accuracy in the horizontal direction.

Expression (18) below illustrates the relationship between the composite macro block e and the macro blocks a-d in the anchor frame in the spatial domain. ##EQU17##

Expressions (19a)-(19d) below are derived in the same manner as expressions (17a)-(17d) above using expression (18). ##EQU18## where Y represents expression (20) below ##EQU19##

Using expressions (16) and (19a)-(19d), the composite macro block E can be derived with horizontal half-pel accuracy.

Vertical Half-Pel Accuracy

If coordinate (m,n) falls between two pixels in the vertical direction, then motion compensation must be performed with half-pel (i.e., half pixel) accuracy in the vertical direction. Equation (54) below illustrates the relationship between the composite macro block e and the macro blocks a-d of the anchor frame in the spatial domain. ##EQU20##

Expression (22a)-(22d) below are derived in the same manner as expression (17a)-(17d) using expression (21). ##EQU21## where X represents expression (56) below. ##EQU22##

Using expression (16) and (22a)-(22d), the composite macro block E can be derived with vertical half-pel accuracy.

Diagonal Half-Pel Accuracy

If coordinate (m,n) falls between two pixels in the diagonal direction, then motion compensation must be performed with half-pel accuracy in the diagonal direction. Expression (24) below illustrates the relationship between the composite macro block e and the macro blocks a-d of the anchor frame in the spatial domain. ##EQU23##

Expressions (25a)-(25d) below are derived in the same manner as expressions (17a)-(17d) using expression (24). ##EQU24##

Using expressions (16) and (25a)-(25d), the composite macro block E can be derived with diagonal half-pel accuracy.

The compositer 68 uses expressions (16)-(25d) to form composite macro blocks in the DCT domain when the inter-coded pictures have been encoded on a frame-by-frame basis. Accordingly, when the adder 74 adds the composite macro blocks to the macro blocks of P and B-pictures output from the variable length decoder and dequantizer 58, frame-motion compensation is performed,

Field-Motion Compensation

The digital video signal can, however, also include fields. The even and odd fields of a frame may be inter-coded independently based on the even and odd fields of a previous frame. Namely, the even field may be inter-coded based on either the even or odd field of the previous frame regardless of whether the odd field was inter-coded based on the even or odd field of the previous frame. As discussed above, decoding inter-coded fields is referred to as field-motion compensation.

To perform field-motion compensation, the motion vector address generator 62 receives the odd field motion vector and the even field motion vector from the variable length decoder and dequantizer 58. The odd field motion vector points to a first coordinate (m,n) of a composite odd field macro block e, white the even field motion vector points to a second coordinate (m',n') of a composite even field macro block e'. Based on the first and second motion vectors, the motion vector address generator 62 instructs the memory 64 as to which of the anchor frame macro blocks to output to the compositer 68.

For purposes of discussion, assume that the motion vector address generator instructs the memory 64 to output anchor frame macro blocks A-D with respect to the odd field motion vector and output anchor frame macro blocks A'-D' with respect to the even field motion vector. The motion vector address generator 62 also outputs a signal to the compositer 68 indicating the coordinates (m,n) and (m',n'). Additionally, the signal output by the motion vector address generator 62 to the compositer 68 indicates whether frame or field motion compensation is to be performed. If field-motion compensation is to be performed, the compositer 68 then forms a frame composite macro block according to expressions (26)-(61) discussed below.

Because of the operation of the field-to-frame converter 69, the adder 74 receives macro blocks of a frame even when the HDTV signal includes fields. Therefore, the compositer 68 has to output frame composite macro blocks. Also, the macro blocks received from the memory 64 via the variable length decoder and dequantizer 67 are frame macro blocks. Accordingly, when performing field-motion compensation, the compositer 68 (1) separates the anchor frame macro blocks into even and odd fields, (2) forms respective even and odd field composite macro blocks, and (3) interlaces the even and odd field composite macro blocks to form a frame composite macro block. Operations (1), (2), and (3) are simultaneously performed by the compositer 68 according to expressings (26)-(61) discussed below.

Full-Pel Accuracy

With field-motion compensation, four possible encoding schemes exist:

(1) o.fwdarw.o o.fwdarw.e (2) e.fwdarw.o e.fwdarw.e (3) o.fwdarw.o e.fwdarw.e (4) o.fwdarw.e e.fwdarw.o where o.fwdarw.e means that the current even field was encoded based on the previous odd field. In other words, "o" stands for odd field and "e" stands for even field.

Case (1) o.fwdarw.o and o.fwdarw.e

Expression (26) below represents the relationship between the frame composite macro block e and the macro blocks a-d and a'-d' of the anchor frame in the spatial domain when the even and odd fields are encoded based on the odd field of the anchor frame. ##EQU25## The top half of expression (26) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (26) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (26), expression (27) below is derived in the same manner as expression (14). ##EQU26## where ##EQU27##

The quadruple summations including the terms A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in equation (27) represent the o.fwdarw.o portion of the frame composite macro block E, while the quadruple summations including the terms A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (27), the motion compensated frame macro block E can be derived for full-pel accuracy when the even and odd fields are encoded based on the odd field of the anchor frame.

As expressions (26) and (27) show, the frame composite macro block e can be represented in the spatial domain such that the frame composite macro block E can be derived without having to separately perform the following operations: (1) separate the frame anchor macro blocks into even and odd fields, (2) form respective even and odd field composite macro blocks, and (3) interlace the even and odd field composite macro blocks to form a frame composite macro block.

Case (2) e.fwdarw.o and e.fwdarw.e

Expression (29) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the even and odd fields are encoded based on the even field of the anchor frame. ##EQU28##

The top half of expression (29) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (29) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (29), expression (30) below is derived in the same manner as expression (14). ##EQU29##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (30) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (30) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (30), the motion compensated frame macro block E can be derived for full-pel accuracy when the even and odd fields are encoded based on the even field of the anchor frame.

Case (3) o.fwdarw.o and e.fwdarw.e

Expression (31) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame. ##EQU30##

The top half of expression (31) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (31) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (31), expression (32) below is derived in the same manner as expression (14). ##EQU31##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (32) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (32) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (32), the motion compensated frame macro block E can be derived for full-pel accuracy when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame.

Case (4) e.fwdarw.o and o.fwdarw.e

Expression (33) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame. ##EQU32##

The top half of expression (33) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (33) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (33), expression (34) below is derived in the same manner as expression (14). ##EQU33##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (34) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (34) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (34), the motion compensated frame macro block E can be derived for full-pel accuracy when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame.

Accordingly, using expressions (27), (30), (32), and (34), the DCT coefficients for the composite macro block E can be determined. As one skilled in the art will readily appreciate from the above disclosure, the expressions above provide a composite macro block for full pixel accuracy. In other words, the coordinates (m,n) and m',n') are the coordinates for a pixel in the composite macro block e. The coordinates (m,n) and (m',n') do not, however, always fall on a pixel in a macro block of the anchor frame. Instead, these coordinates could fall between two pixels in the horizontal direction, between two pixels in the vertical direction, or between two pixels in the diagonal direction.

Horizontal Half-Pel Accuracy

Case (1) o.fwdarw.o and o.fwdarw.e

Expression (35) below represents the relationship between the frame composite macro block e and the macro blocks a-d and a'-d' in the anchor frame in the spatial domain when the even and odd fields are encoded based on the odd field of the anchor frame. ##EQU34##

The top half of expression (35) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (35) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (35), expression (36) below is derived in the same manner as expression (14). ##EQU35## where ##EQU36##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (36) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (36) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (36), the motion compensated frame macro block E can be derived for horizontal half-pel accuracy when the even and odd fields are encoded based on the odd field of the anchor frame.

Case (2) e.fwdarw.o e.fwdarw.e

Expression (38) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the even and odd fields are encoded based on the even field of the anchor frame. ##EQU37##

The top half of expression (38) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (38) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (38), expression (39) below is derived in the same manner as expression (14). ##EQU38##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (39) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (39) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (39), the motion compensated frame macro block E can be derived for horizontal half-pel accuracy when the even and odd fields are encoded based on the even field of the anchor frame.

Case (3) o.fwdarw.o and e.fwdarw.e

Expression (40) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame. ##EQU39##

The top half of expression (40) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (40) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (40), expression (41) below is derived in the same manner as expression (41). ##EQU40##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (41) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (41) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (41), the motion compensated frame macro block E can be derived for horizontal half-pel accuracy when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame.

Case (4) e.fwdarw.o and o.fwdarw.e

Expression (42) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame. ##EQU41##

The top half of expression (42) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (42) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (42), expression (43) below is derived in the same manner as expression (14). ##EQU42##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (43) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (43) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (43), the motion compensated frame macro block E can be derived for horizontal half-pel accuracy when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame.

Vertical Half-Pel Accuracy

Case (1) o.fwdarw.o and o.fwdarw.e

Expression (44) below represents the relationship between the frame composite macro block e and the macro blocks a-d and a'-d' in the anchor frame in the spatial domain when the even and odd fields are encoded based on the odd field of the anchor frame. ##EQU43##

The top half of expression (44) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (44) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (44), expression (45) below is derived in the same manner as expression (14). ##EQU44##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (45) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (45) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (45), the motion compensated frame macro block E can be derived for vertical half-pel accuracy when the even and odd fields are encoded based on the odd field of the anchor frame.

Case (2) e.fwdarw.o and e.fwdarw.e

Expression (47) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the even and odd fields are encoded based on the even field of the anchor frame. ##EQU45##

The top half of expression (47) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (47) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (47), expression (48) below is derived in the same manner as expression (14). ##EQU46##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (48) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (48) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (48), the motion compensated frame macro block E can be derived for vertical half-pel accuracy when the even and odd fields are encoded based on the even field of the anchor frame.

Case (3) o.fwdarw.o and e.fwdarw.e

Expression (49) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame. ##EQU47##

The top half of expression (49) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (49) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (49), expression (50) below is derived in the same manner as expression (14). ##EQU48##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (50) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (50) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (50), the motion compensated frame macro block E can be derived for vertical half-pel accuracy when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame.

Case (4) e.fwdarw.o and o.fwdarw.e

Expression (51) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame. ##EQU49##

The top half of expression (51) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (51) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (51), expression (52) below is derived in the same manner as expression (14). ##EQU50##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (52) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (52) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (52), the motion compensated frame macro block E can be derived for vertical half-pel accuracy when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame.

Diagonal Half-Pel Accuracy

Case (1) o.fwdarw.o and o.fwdarw.e

Expression (53) below represents the relationship between the frame composite macro block e and the macro blocks a-d and a'-d' in the anchor frame in the spatial domain when the even and odd fields are encoded based on the odd field of the anchor frame. ##EQU51##

The top half of expression (53) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (53) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (53), expression (54) below is derived in the same manner as expression (14). ##EQU52##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (54) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (54) represent the o.fwdarw.o portion of the frame composite macro block E.

Using expression (54) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the even and odd fields are encoded based on the even field of the anchor frame. ##EQU53##

The top half of expression (56) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (56) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (56), expression (57) below is derived in the same manner as expression (14). ##EQU54##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (57) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (57) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (57), the motion compensated frame macro block E can be derived for diagonal half-pel accuracy when the even and odd fields are encoded based on the even field of the anchor frame.

Case (3) o.fwdarw.o and e.fwdarw.e

Expression (58) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame. ##EQU55##

The top half of expression (58) represents the o.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (58) represents the e.fwdarw.e portion of the frame composite macro block e.

Using expression (58), expression (59) below is derived in the same manner as expression (14). ##EQU56##

The summation terms including a.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (59) represent the o.fwdarw.o portion of the frame composite macro block E, while the summation terms including a'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (59) represent the e.fwdarw.e portion of the frame composite macro block E.

Using expression (59), the motion compensated frame macro block E can be derived for diagonal half-pel accuracy when the odd and even fields are encoded based on the odd and even fields, respectively, of the anchor frame.

Case (4) e.fwdarw.o and o.fwdarw.e

Expression (60) below represents the relationship between frame composite macro block e and the macro blocks a-d and a'-d' in the spatial domain when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame. ##EQU57##

The top half of expression (60) represents the e.fwdarw.o portion of the frame composite macro block e, while the bottom portion of expression (60) represents the o.fwdarw.e portion of the frame composite macro block e.

Using expression (60), expression (61) below is derived in the same manner as expression (14). ##EQU58##

The summation terms including A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq in expression (61) represent the e.fwdarw.o portion of the frame composite macro block E, while the summation terms including a'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq in expression (61) represent the o.fwdarw.e portion of the frame composite macro block E.

Using expression (61), the motion compensated frame macro block E can be derived for diagonal half-pel accuracy when the odd and even fields are encoded based on the even and odd fields, respectively, of the anchor frame.

With field motion compensation, both motion vectors do not always have the same accuracy, half or full-pel, in the same direction. For instance, the odd field portion vector could have full-pel accuracy, while the even field motion vector has half-pel accuracy in the horizontal direction. As another example, the odd field could have half-pel accuracy in the horizontal direction, while the even field motion vector has half-pel accuracy in the vertical direction.

The composite macro block expressions for these instances can be readily generated from those portions of the previously discussed expressions corresponding to the motion vectors. For instance, if the odd field is encoded based on the previous odd field and the motion vector therefor has half-pel accuracy in the horizontal direction, then the top half of expression (35) represents the first part of the frame composite macro block e.sub.ij, while the summation terms A.sub.pq, B.sub.pq, C.sub.pq, and D.sub.pq from expression (36) are used to generate the first part of the frame composite macro block E.sub.kl. Next, if the even field is encoded based on the previous even field and the motion vector therefore has half-pel accuracy in the vertical direction, then the bottom half of expression (49) represents the second part of the frame composite macro block e.sub.ij, while the summation terms A'.sub.pq, B'.sub.pq, C'.sub.pq, and D'.sub.pq from expression (50) are used to generate then second part of the frame composite macro block E.sub.kl.

As discussed above, B-pictures may be bi-directionally encoded. Accordingly, two motion vectors are associated with each field or frame of a bi-directionally encoded B-picture. The motion vector address generator 62 identifies and informs the compositer 68 when a picture is a bi-directionally inter-coded picture. In response, the compositer 68 forms composite anchor frame blocks with respect to each anchor frame pointed to by the motion vectors. The compositer 68 then averages the two composite macro blocks to form a weighted average composite macro block, and outputs the weighted average composite macro block to the adder 74.

The adder 74 adds the composite macro block to the macro block of the picture data currently output by the variable length decoder and dequantizer 58, or optionally the field-to-frame converter 69, to reconstruct a complete macro block. In this manner, both P-pictures and B-pictures are converted into I-pictures.

Of course, if an I-picture is currently being output by the variable length decoder and dequantizer 58, then the adder 74 will not receive anything from the compositer 68 to add thereto. The motion vector address generator 62 will have recognized the I-picture as an I-picture and disabled the compositer 68 from sending output to the adder 74.

The output of the adder 74 is received by a reformatter 78. The reformatter 78 is also connected to the memory 64 via the variable length decoder and dequantizer 66. Because all of the pictures in the HDTV signal are converted into I-pictures, if not already I-pictures, the reformatter 78 restores the order of the pictures in the digital video signal to the display order.

The reformatter 78 generates output according to the following rules: (1) if the picture received is the first anchor picture received, then no output will be sent as the output of the digital video decoder and the I-picture will be output to the memory 64 for storage; (2) if the picture received is an anchor picture but not the first anchor picture received, then the previously received anchor picture will be obtained from the memory 64 via the variable length decoder 66 and output as the output of the digital video decoder, and the current anchor frame will be output to the memory 64 for storage; and (3) if the picture received is a B-picture, then the B-picture will be immediately output.

Therefore, upon receipt of I-picture I.sub.1, the reformatter 78 will output the I-picture I.sub.1 to the memory 64 for storage via the quantizer 70, the variable length coder 72, and the bity stream parser 59. The next picture output by the adder 74 will be P-picture P.sub.1. Since this picture is an anchor picture, the memory 64 will then store the P-picture P.sub.1, albeit converted into an I-picture, under the control of the bit stream parser 59. And, the reformatter 78 will send the memory 64 a control signal to output the I-picture I.sub.1 (i.e., the previous anchor picture) to the reformatter 78, and the reformatter 78 will output the I-picture I.sub.1. The reformatter 78 will then receive and immediately output the B-pictures. Consequently, the output order from the reformatter 78 will be I.sub.1 B.sub.1 B.sub.2.

Next, the P-picture P.sub.2 is received and processed in the same manner as P-picture P.sub.1. Consequently, the bit stream parser 59 will replace the I-picture I.sub.1 with the P-picture P.sub.2 in the memory 64. The reformatter 78, according to the rules discussed above, will then receive P-picture P.sub.1 from the memory 64, and output P-picture P.sub.1. In this manner, the reformatter 78 will output the pictures in the proper display order, and these pictures will all be I-pictures. Therefore, the digital video decoder outputs the digital video signal comprised entirely of I-pictures in the display order.

Because the digital video decoder of FIG. 2 stores anchor frames which are in the DCT domain and which have been variable length encoded and quantized, the digital video decoder of FIG. 2 significantly reduces the amount of memory required to decode digital video signals including inter-coded pictures.

The above described embodiment may have several different forms of implementation. For instance, the embodiment could be implemented using a programmed microprocessor. Alternatively, each embodiment could be implemented using hard-wired logic.

While the present invention has been described with respect to specific coding sequences, it should be understood that the present invention is not limited to the coding sequences described. Additionally, the present invention is not restricted to use with a particular digital format such as MPEG or a particular level of definition such as high definition television. Instead, the present invention may be used with any format in any application where decoding of a digital video signal is desired.

Furthermore, while the invention has been described in connection with what is presently considered the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An apparatus for decoding a digital video signal, comprising:

means for performing motion compensation including a motion compensator for receiving a digital video signal and performing undistorted motion compensation on said digital video signal in frequency domain with sub-pel accuracy; and

means for reformatting including a reformatter reformatting pictures in said digital video signal output by said motion compensation such that said pictures are in a display order.

2. The apparatus of claim 1, wherein said motion compensator forms, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said inter-coded picture to perform said motion compensation.

3. The apparatus of claim 2, wherein said motion compensator comprises:

an anchor picture memory storing at least one anchor picture for forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture.

4. The apparatus of claim 3, wherein said anchor picture memory stores two anchor frames.

5. The apparatus of claim 3, wherein said anchor picture memory stores said anchor picture as compressed bits via quantization and variable length coding of frequency domain blocks.

6. The apparatus of claim 3, wherein said anchor picture memory stores an anchor picture having most recently undergone motion compensation.

7. The apparatus of claim 2, wherein said motion compensator outputs intra-coded pictures in said digital video signal without performing motion compensation thereon.

8. The apparatus of claim 3, wherein said motion compensator outputs intra-coded pictures in said digital video signal without performing motion compensation thereon.

9. The apparatus of claim 8, wherein said anchor frame memory stores an anchor picture which is an intra-coded picture in said digital video signal received by said motion compensator.

10. The apparatus of claim 1, wherein said motion compensator performs.

11. The apparatus of claim 3, wherein said anchor picture memory stores said anchor picture in a compressed format.

12. The apparatus of claim 1, wherein said reformatter reformats said pictures in the frequency domain.

13. The apparatus of claim 3, wherein said anchor picture memory stores said anchor picture as variable length coded bits in the frequency domain.

14. An apparatus for decoding a digital video signal, comprising:

motion compensation means for receiving a digital video signal and performing motion compensation on said digital video signal in the frequency domain; and

a reformatter reformatting pictures in said digital video signal output by said motion compensation means such that said pictures are in a display order; wherein

said motion compensation means forms, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said inter-coded picture to perform said motion compensation;

said motion compensation means comprises:

an anchor picture memory storing at least one anchor picture in said frequency domain; and

means for forming said composite picture based on said anchor picture and a motion vector associated with said inter-coded picture, said means for forming comprising:

motion vector generating means for separating said motion vectors from said inter-coded picture, and addressing portions of said anchor picture stored in said anchor picture memory based on said motion vectors; and

a compositor synthesizing, for each motion vector, portions of said anchor picture addressed based on said motion vectors to form said composite picture.

15. The apparatus of claim 14, wherein

said anchor picture memory stores said anchor picture on a macro block by macro block basis;

said motion vector generating means separates said motion vector associated with each macro block in said inter-coded picture, and addresses macro blocks of said anchor picture based on said motion vector;

said compositor synthesizes said addressed macro blocks to form a composite macro block based on said motion vector.

16. The apparatus of claim 15, wherein said motion compensation means further comprises:

an adder for adding each macro block in said inter-coded picture to a corresponding composite macro block output by said compositer.

17. The apparatus of claim 16, wherein

said adder receives said digital video signal, adds each macro block in said inter-coded picture to a corresponding composite macro block output by said compositer, and outputs intra-coded pictures in said digital video signal unchanged.

18. The apparatus of claim 17, wherein

said anchor picture memory stores a last two anchor pictures output from said adder.

19. The apparatus of claim 17, wherein said motion compensation means further comprises:

a quantizer for quantizing each anchor picture output by said adder;

a variable length coder variable length coding output of said quantizer;

parser means for storing output of said variable length coder in said anchor picture memory.

20. The apparatus of claim 19, wherein said quantizer quantizes each anchor picture such that distortion is eliminated.

21. An apparatus for decoding a digital video signal, comprising:

means for converting inter-coded to intra-coded pictures including a converter receiving a digital video signal and converting, in frequency domain with sub-pel accuracy, inter-coded pictures in said digital video signal into undistorted intra-coded pictures; and

means for reformatting including a reformatter for reformatting pictures in said digital video signal output by said converter such that said pictures are in a display order.

22. The apparatus of claim 21, wherein said converter performs motion compensation on said inter-coded picture sin said digital video signal to convert said inter-coded pictures into intra-coded pictures.

23. The apparatus of claim 22, wherein said converter forms, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said corresponding inter-coded picture to perform said motion compensation.

24. The apparatus of claim 23, wherein said motion compensator comprises:

an anchor picture memory storing at least one anchor picture;

means for forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture.

25. The apparatus of claim 24, wherein said anchor picture memory stores said anchor picture in a compressed format.

26. The apparatus of claim 21, wherein said reformatter reformats said pictures in the frequency domain.

27. An apparatus for decoding a digital video signal, comprising:

a converter receiving a digital video signal and converting, in the frequency domain, inter-coded pictures in said digital video signal into intra-coded pictures; and

a reformatter reformatting pictures in said digital video signal output by said converter such that said pictures are in a display order; wherein

said converter performs motion compensation in said frequency domain on said inter-coded pictures in said digital video signal to convert said inter-coded pictures into intra-coded pictures;

said converter forms, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said corresponding inter-coded picture to perform said motion compensation;

said converter comprises:

an anchor picture memory storing at least one anchor picture in said frequency domain;

means for forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture, said means for forming comprising:

motion vector generating means for separating said motion vectors from said inter-coded picture, and addressing portions of said anchor picture stored in said anchor picture memory based on said motion vectors; and

a compositor synthesizing, for each motion vector, portions of said anchor picture addressed base don said motion vectors to form said composite picture.

28. The apparatus of claim 27, wherein

said anchor picture memory stores said anchor picture on a macro block by macro block basis;

said motion vector generating means separates said motion vector associated with each macro block in said inter-coded picture, and addresses macro blocks of said anchor picture based on said motion vector;

said compositor synthesizes said addressed macro blocks to form a composite macro block based on said motion vector.

29. A method for decoding a digital video signal, comprising:

(a) receiving a digital video signal;

(b) performing motion compensation on said digital video signal in the frequency domain, including storing anchor pictures as compressed bits; and

(c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order.

30. The method of claim 29, wherein said step (b) comprises the steps of:

(b1) forming, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture; and

(b2) adding said composite picture to said inter-coded picture to perform said motion compensation.

31. The method of claim 30, wherein said (b1) comprises the steps of:

(b11) storing at least one anchor picture;

(b12) forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture.

32. The method of claim 31, wherein said step (b11) stores two anchor frames.

33. The method of claim 31, wherein said step (b11) stores said anchor picture quantized bits.

34. The method of claim 31, wherein said step (b11) stores an anchor picture having most recently undergone motion compensation.

35. The method of claim 30, wherein said step (b) further comprises the step of (b3) outputting intra-coded pictures in said digital video signal without performing motion compensation thereon.

36. The method of claim 31, wherein said step (b) further comprises the step of (b3) outputting intra-coded pictures in said digital video signal without performing motion compensation thereon.

37. The method of claim 36, wherein said step (b11) stores an anchor picture which is an intra-coded picture in said digital video signal received by said step (a).

38. The method of claim 29, wherein said step (b) performs and field motion compensation.

39. The method of claim 31, wherein said step (b11) stores said anchor picture in a compressed format.

40. The method of claim 29, wherein said pictures are reformatted in the frequency domain.

41. The method of claim 31, wherein said anchor picture is stored as variable length coded bits.

42. A method for decoding a digital video signal, comprising:

(a) receiving a digital video signal;

(b) performing motion compensation on said digital video signal in the frequency domain; and

(c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order; wherein

said step (b) comprises the steps of:

(b1) forming, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture; and

(b2) adding said composite picture to said inter-coded picture to perform said motion compensation, wherein said (b1) comprises the steps of:

(b11) storing at least one anchor picture in said frequency domain; and

(b12) forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture, said step (b12) comprises the steps of:

(b121) separating said motion vectors from said inter-coded picture;

(b122) addressing portions of said anchor picture stored in said step (b11) based on said motion vectors; and

(b123) synthesizing, for each motion vector, portions of said anchor picture addressed based on said motion vectors to form said composite picture.

43. The method of claim 42, wherein

said step (b11) stores said anchor picture on a macro block by macro block basis;

said step (b121) separates said motion vector associated with each macro block in said inter-coded picture;

said step (b122) addresses macro blocks of said anchor picture based on said motion vector;

said step (b123) synthesizes, in said frequency domain, said addressed macro blocks to form a composite macro block based on said motion vector.

44. The method of claim 43, wherein step (b2) adds each macro block in said inter-coded picture to a corresponding composite macro block output by said step (b123).

45. The method of claim 44, wherein said step (b2) comprises the steps of:

(b21) receiving said digital video signal;

(b22) adding each macro block in said inter-coded picture to a corresponding composite macro block output by said step (b123); and

(b23) outputting intra-coded pictures in said digital video signal unchanged.

46. The method of claim 45, wherein

said step (b11) stores a last two anchor pictures output from said adder.

47. The method of claim 46, wherein said step (b) further comprises:

(b3) quantizing each anchor picture output by said step (b2);

(b4) variable length coding output of said step (b3); and wherein

said step (b11) stores output of said step (b4).

48. The method of claim 47, wherein said step (b3) quantizes each anchor picture such that distortion is eliminated.

49. A method for decoding a digital video signal, comprising:

(a) receiving a digital video signal;

(b) converting, in the frequency domain, inter-coded pictures in said digital video signal into intra-coded pictures, including storing anchor pictures as compressed bits; and

(c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order.

50. The method of claim 49, wherein said step (b) performs motion compensation on said inter-coded pictures in said digital video signal to convert said inter-coded pictures into intra-coded pictures.

51. The method of claim 50, wherein said step (b) comprises the steps of:

(b1) forming, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture; and

(b2) adding said composite picture to said inter-coded picture to perform said motion compensation.

52. The method of claim 51, wherein said (b1) comprises the steps of:

(b11) storing at least one another picture;

(b12) forming said composite picture based on said anchor picture and motion vector associated with said inter-coded picture.

53. The method of claim 52, wherein said step (b11) stores said anchor picture in a compressed format.

54. The method of claim 49, wherein said pictures are reformatted in the frequency domain.

55. A method for decoding a digital video signal, comprising:

(a) receiving a digital video signal;

(b) converting, in the frequency domain, inter-coded pictures in said digital video signal into intra-coded pictures; and

(c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order; wherein

said step (b) performs motion compensation in said frequency domain on said inter-coded pictures in said digital video signal to convert said inter-coded pictures intra-=coded pictures, and comprises the steps of:

(b1) forming, for each inter-coded picture in said digital video signal, a composite picture in said frequency domain representing a reference picture corresponding to said inter-coded picture; and

(b2) adding said composite picture to said inter-coded picture to perform said motion compensation;

wherein said (b1) comprises the step of:

(b11) storing at least one anchor picture in said frequency domain;

(b12) forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture; and

(b121) separating said motion vectors from said inter-coded picture;

(b122) addressing portions of said anchor picture stored in said step (b11) based on said motion vectors;

(b123) synthesizing, for each motion vector, portions of said anchor picture addressed based on said motion vectors to form said composite picture.

56. The method of claim 55, wherein

said step (b11) stores said anchor picture on a macro block by macro block basis;

said step (b121) separates said motion vector associated with each macro block in said inter-coded picture;

said step (b122) addresses macro blocks of said anchor picture based on said motion vector;

said step (b123) synthesizes, in said frequency domain, said addressed macro blocks to form a composite macro block based on said motion vector.

57. An apparatus for decoding a digital video signal, comprising:

motion compensation means for receiving a digital video signal and performing motion compensation on said digital video signal; and

a reformatter reformatting pictures in said digital video signal output by said motion compensation means such that said pictures are in a display order; wherein

said motion compensation means forms, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture, and adds said composite picture to said inter-coded picture to perform said motion compensation;

said motion compensation means comprises:

an anchor picture memory storing at least one anchor picture; and

means for forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture; and

said anchor picture memory stores said anchor pictures as compressed bits via quantization and variable length coding.

58. A method for decoding a digital video signal, comprising:

(a) receiving a digital video signal;

(b) performing motion compensation on said digital video signal; and

(c) reformatting pictures in said digital video signal output by said step (b) such that said pictures are in a display order; wherein

said step (b) comprises the steps:

(b1) forming, for each inter-coded picture in said digital video signal, a composite picture representing a reference picture corresponding to said inter-coded picture; and

(b2) adding said composite picture to said inter-coded picture to perform said motion compensation;

said (b1) comprises the steps of:

(b11) storing at least one anchor picture; and

(b12) forming said composite picture based on said anchor picture and motion vectors associated with said inter-coded picture; and

said step (b11) stores said anchor pictures as compressed bits via quantization and variable length coding.