Patent Application
20120062204
The present invention relates generally to voltage converters and in particular to a digital voltage converter driven by a tracking analog-to-digital converter.
Voltage converters are electrical circuits that are configured to receive an input voltage and based thereupon to provide an output voltage different than the input voltage. Voltage converters may comprise DC-to-DC converters, AC-to-DC converters, etc., for example.
DC-to-DC converters typically convert power from one DC voltage to another DC voltage (e.g., from 3V to 5V or from 5V to 3V). DC-to-DC converters are usually regulated devices, taking a possibly varying input voltage, and providing a stable, regulated output voltage, often up to some current (amperage) limit. In this way, DC-to-DC converters can in some instances be thought of as a “black box” that receives one voltage from a battery, for example, and converts it to another voltage that is used to power an integrated circuit.
This basic DC-to-DC conversion functionality makes DC-to-DC converters widely used for power conversion in many electronic systems, such as communications devices, among others.
One or more implementations of the present disclosure will now be described with reference to the attached drawings, where like reference numerals are used to refer to like elements throughout. Nothing in this detailed description is admitted as prior art.
It will be appreciated that although the following detailed description often describes a disclosed voltage converter in terms of a DC-to-DC converter circuit, that the disclosed invention is not limited to DC-to-DC converters/converter circuits. Rather, the disclosed use of a tracking ADC in a voltage converter circuit may broadly apply to voltage converter circuits having DC-to-DC converters or AC-to-DC converters, for example.
DC-to-DC converters are important components in many modern portable electronic devices that rely upon battery based power sources, such as cellular phones and laptop computers. In modern technology there is a trend to use digital DC-to-DC converters, which operate in the digital domain. Digital DC-to-DC converters offer many advantages over analog DC-to-DC converters such as consuming less silicon area, being more testable, more repeatable, more programmable, etc.
Digital DC-to-DC converter circuits may use an analog-to-digital converter (ADC) to drive the voltage output of a DC-to-DC converter. ADCs comprising flash converters, window flash converters, or sigma delta converters may generate a signal that drives digital DC-to-DC converters. However, these digital ADC options contain undesirable attributes. For example, a flash converter is fast, but contains hardware that utilizes large chip area and power. Accordingly, a digital voltage converter circuit configured to provide a digitized output with minimum hardware and power consumption is disclosed herein.
As provided herein, the disclosed voltage converter circuit (e.g., DC-to-DC converter circuit, AC-to-DC converter circuit) comprises a tracking ADC configured to drive a voltage converter. The tracking ADC is configured to receive an analog feedback voltage, from the output of the voltage converter, and to compare it to an analog reference voltage. The results of the comparison are used to generate a digital ADC output signal, comprising a digital code, that drives (e.g., adjusts) the output voltage of the voltage converter. In particular, the digital ADC output signal drives operation of the voltage converter by indicating whether the output of the voltage converter will be adjusted (e.g., by telling the voltage converter to increase its output voltage or to decrease its output voltage). Although a tracking ADC has a slow response time and is typically not a pre-designed hardware circuit block of general use it may be implemented into a voltage converter to provide an ADC that has low power consumption and chip area.
The digital DC-to-DC converter 102 is configured to receive the digital ADC output signal S1 and is driven by the digital ADC output signal S1 to adjustably generate a stepped-up “boost” output voltage or a stepped down “buck” output voltage VOUT, therefrom. In particular, the digital DC-to-DC converter 102 checks if the digital code of the received digital ADC output signal S1 indicates whether the output voltage of the DC-to-DC converter should be increased or decreased to achieve a desired output voltage VOUT.
The tracking ADC 204a may comprise a feedback loop having a digital-to-analog converter (DAC) 206, a comparator 208, and a logic circuit 210a. The DAC 206 is configured to receive a digital ADC feedback signal S1′, having a digital code, output from the logic circuit 210a. In various embodiments, the digital ADC feedback signal S1′ may comprise the digital ADC output signal S1, output from logic circuit 210a, or some variation thereof. The DAC 206 will generate an analog reference voltage VREF based upon the digital code of the received digital ADC feedback signal S1′. For example, a digital ADC feedback signal S1′ having a digital code comprising an integer value of “100” may be received by DAC 206, resulting in DAC 206 generating and outputting an analog reference voltage VREF of 1V.
The comparator 208 comprises a first input node and a second input node. The first input node is configured to receive the analog reference voltage VREF output from DAC 206. The second input node is configured to receive an analog feedback voltage VFB output from the DC-to-DC converter 202a. The comparator 208 is configured to compare the reference voltage VREF to the feedback voltage VFB, and based upon the comparison to output a comparator signal Sc to the logic circuit 210a. In one embodiment, the comparator signal Sc indicates whether the reference voltage VREF is smaller than the feedback voltage VFB (e.g., SC=“1”) or larger than the feedback voltage (e.g., SC=“0”).
The logic circuit 210a receives the comparator signal Sc and based thereupon generates the digital ADC output signal S1. As shown in DC-to-DC converter circuit 200, the digital ADC output signal S1 may be a digital representation of the feedback voltage VFB that indicates what adjustment (e.g., an increase or decrease) to the output of the DC-to-DC converter 202a VOUT should be made.
The digital ADC output signal S1 is provided to the DC-to-DC converter 202a. The DC-to-DC converter 202a may comprise a regulator configured to compare the digital code comprised within the received digital ADC output signal S1 to a target code value Scode and to take an appropriate action (e.g., raise or lower the output voltage VOUT) based upon the comparison. Since the digital code is a digital representation of the feedback voltage VFB, the regulator will attempt to modify the output voltage VOUT so that the digital code achieves the desired voltage (e.g., target code value Scode). For example, if digital ADC output signal S1 has a first code that is larger than a target code value Scode it may indicate to the DC-to-DC converter 202a that it is outputting a voltage that is larger than a desired voltage, and that the output voltage VOUT should be decreased. Similarly, if the digital ADC output signal S1 has a second, different, code that is smaller than the target code value Scode it may indicate to the DC-to-DC converter 202a that it is outputting a voltage that is smaller than the desired voltage, and that the output voltage VOUT should be increased.
In one embodiment, the logic circuit 210a may comprise an up/down counter. (See, e.g.,
As shown in
If the tracking ADC 204a is off-target, as shown at the beginning of the graph (region 308), the digital ADC output signal S1 has to catch up with the analog feedback voltage VFB and therefore the ADC output signal S1 may iteratively be adjusted over multiple feedback cycles (e.g., toggling up/down to produce a ramp of the codes in-between the starting code and a code corresponding to the analog feedback voltage). In particular, during the ramp up stage (region 308), the ADC output signal S1 attempts to adjust the reference voltage VREF 306 towards the feedback voltage VFB 302. Since feedback voltage VFB 302 is larger than the reference voltage VREF 306, the comparator 208 will output a comparator signal Sc having a high data state (e.g., “1”) that results in a digital ADC output signal S1 304 having an incremented digital code. Continual incrementation of the digital code will cause the reference voltage VREF 306 to quickly increase until it has caught up to the analog feedback voltage VFB 302.
Once the digital ADC output signal S1 304 has caught up with the analog feedback voltage VFB 302, it will achieve a steady state, shown in region 310 (e.g., following the much slower transient produced by the DC/DC). In the steady state (region 310), the up/down counter may toggle between two adjacent reference voltages VREF 306 since the up/down counter is continuously incrementing or decrementing the digital code of the ADC output signal S1 304.
In the steady state (region 310), since the digital code of ADC output signal S1 304 represents the feedback voltage, the digital code may also regulate the output voltage VOUT of the DC-to-DC converter. For example, the digital ADC output signal S1 304 will be received by the DC-to-DC converter and the digital code is compared to a target code value Scode. If the target code value Scode is larger than the digital code of the digital ADC output signal S1, the DC-to-DC converter will increase its output voltage. The increased output voltage is fed back to the comparator 208 which once again performs a comparison. Similarly, if the target code value Scode is smaller than the digital code of the digital ADC output signal S1, the DC-to-DC converter will decrease its output voltage.
It will be appreciated that the DC-to-DC converter 202a may typically comprise an inductor that is responsible for energy conversion and that provides for an output signal that passes through a large capacitor 212. The capacitor 212 will build up charge over time due to the output current of the DC-to-DC converter 202a. When the output current cannot satisfy the needs of a load, the capacitor 212 will discharge, thereby keeping the output voltage of the DC-to-DC converter VOUT relatively constant. The use of a large capacitor (e.g., 10 pF) may keep the output voltage of the DC-to-DC converter stable even in the presence of load jumps (e.g., a varying active load) and/or line jumps. For example, in modern applications, the switching frequency of a DC-to-DC regulator might be on the order of 1 MHz whereas internal clock speeds might be on the order of 100 MHz or more. In such applications, because of the capacitor 212, the small movements of voltages (e.g., codes) within one switching period are possible without causing significant problems with the DC-to-DC output.
In one embodiment, wherein the DC-to-DC converter circuit 200 is used in a system that performs dynamic voltage scaling, a DAC may be shared between a voltage scaling circuit and the DC-to-DC converter circuit. For example, in
In one embodiment, the digital DC-to-DC converter 202b may comprise a regulator configured to regulate the output voltage VOUT compared to a zero (“0”) input. In such an embodiment, the DC-to-DC converter 202b will try to regulate the output voltage VOUT to counteract any deviation of the digital ADC output signal S1 from a code value of zero. To accomplish this, the DC-to-DC converter 202b may be configured to compare the digital code of ADC output signal S1 with a target code value Scode of zero and to take appropriate action based on the comparison. In one embodiment, DC-to-DC converter circuit 214 may be configured to have an ADC output signal S1 shifted by an amount VT with respect to DC-to-DC converter circuit 200 (
In order to understand the operation of the block diagram shown in
Digital codes may be used to represent errors (e.g., positive, negative, zero) in various ways. In one embodiment, digital codes having a bit indicating a positive or negative value may be used to represent errors. For example, a digital code of ‘1001’ corresponding to +1 indicates a slight positive error, a digital code ‘1010’ corresponding to +2 indicates a larger positive error, a digital code of ‘1011’ corresponding to +3 indicates an even larger positive error, a digital code of ‘1000’ or ‘0000’ indicates no error, a digital code of ‘0001’ corresponding to −1 indicates a slight negative error, etc. In an alternative embodiment, the relationship of a digital code to a target code may be used to represent errors. For example, for a target code corresponding to a decimal value of “100”, a digital code corresponding to a decimal value of “101” would indicate a slight positive error, a digital code corresponding to a decimal value of “102” would indicate a larger positive error, a digital code corresponding to a decimal value of “100” would indicate no error, a digital code corresponding to a decimal value of “99” would indicate a slight negative error, a digital code corresponding to a decimal value of “98” would indicate a larger negative error, etc. One of ordinary skill in the art will appreciate that alternative methods for representing errors using digital codes may be used for the converter circuit provided herein.
As shown in
More particularly, during operation the logic circuit 210b will increment or decrement to try to produce a digital ADC output signal S1 having a digital code that is equal to “0”. In the process it will adjust the output voltage VOUT so that the digital signal VT′ corresponds to the output voltage VOUT. For example, if the tracking ADC is off target, (e.g., if a target code value Vt=100, a feedback voltage VFB=1V, and a ADC output signal S1=300 instead of S1=0, cause a target code value Vt′=400 to produce a reference voltage VREF=4V) the logic circuit 210b will decrement the digital code of the digital ADC output signal S1 (e.g., until it reaches a digital code value of “0”) until that the feedback voltage VFB and the reference voltage VREF are substantially at equilibrium.
Once at equilibrium, the ADC output signal will toggle between values, as shown in
At time T0 (
At time T1 (
In one embodiment, the tracking ADC 204b of
As illustrated in
More particularly, during operation, an error analysis unit 622 is configured to receive the digital ADC output signal S1 comprising a digital code. The error analysis unit 622 performs analysis of the digital code and therefrom generates an error signal 624 that enables the switching control circuit generate a control signal that adjusts the output voltage level VOUT. In one embodiment, the error analysis unit 622 compares the received digital code to a target code value Scode and generates an error signal 624 based upon the comparison.
If the error analysis unit 622 determines from the received digital code that the output voltage level VOUT is to be increased, the error signal 624 can enable the switching control circuit 626 to change the control signal 628 to increase the output voltage level VOUT. Conversely, if the error analysis unit 622 determines from the received digital code that the output voltage level VOUT is to be decreased, the error signal 624 can enable the switching control circuit 626 to change the control signal 628 and decrease the output voltage level VOUT.
The switching control unit will receive the error signal 624 and therefrom generate a control signal 628. The switching control circuit 626 may provide a control signal 628 having a duty cycle, for example. As used herein, the term “duty cycle” describes a fraction of time that the control signal 628 is in an active state relative to an inactive state (or vice versa). For example, a 30% duty cycle can indicate that the control signal 628 is in a continuous active state for 30% of a control signal period and is in a continuous inactive state for the remaining 70% of the control signal period.
The switching regulator 630 receives the control signal 628. Based on the control signal 628, the switching regulator 630 provides a DC output signal VOUT at the output terminal 620. The switching regulator 630 therefore acts as a voltage regulator that uses a switching element to adjust the output voltage VOUT. In various embodiments, the DC-to-DC converter 602 may also include regulation and filtering components to insure a steady output.
In one embodiment, a regulator 708 comprised within DC-to-DC converter circuit 700 will try to enforce a sequence of digital ADC output signals S1 (e.g., output from the tracking ADC 704) to have digital code values of +0.5 and −0.5, which in average give 0. In another embodiment, digital ADC output signals S1 having digital codes toggling between (0,1,0,1) or (0,−1,0,−1) may lead to post processing values of +0.5 or −0.5 after averaging. This feature may be used to eliminate dead zones during operation.
It will be appreciated that the post processing block 706 indicates a post processing functionality that may take place in various places in the DC-to-DC converter circuit 700. In one embodiment, the post processing block 706 could be part of a regulator 708 that may be comprised within the DC-to-DC converter 702. In an alternative embodiment, the post processing block 706 may be part of the tracking ADC 704. As part of the tracking ADC 704, the post processing block 706 can make use of the quasi continuous information that is output from the tracking ADC 704, as the tracking ADC 704 following the reference signal at each clock cycle.
Furthermore, in various embodiments the post processing block may be configured to perform a wide range of post processing actions. For example, in one embodiment, the post processing block 706 may be configured to read out 4 or 8 samples and average them to get an average digital ADC output signal S1. In another embodiment, the post processing block 706 may be configured to generate a weighted average of the digital ADC output signal S1. For example, to emphasize the signal characteristics present at the end of a cycle the post processing block may multiply the digital ADC output signal S1 with a weighting value that is a function of time (e.g., weighting value, w(t)=A+b*t, where b>0 and where t is the time within a given cycle) so that ADC output signals received at the end of a cycle are multiplied by a larger weighting factor than ADC output signals received at beginning of a cycle.
While these methods are illustrated and described below as a series of acts or events, the present disclosure is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts are required and the waveform shapes are merely illustrative and other waveforms may vary significantly from those illustrated. Further, one or more of the acts depicted herein may be carried out in one or more separate acts or phases.
Furthermore, the claimed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter (e.g., the circuits shown in
At 802 an analog feedback voltage is provided to a tracking ADC. The analog feedback voltage may be provided from the output of a DC-to-DC converter and in various embodiments may comprise the output voltage of the DC-to-DC converter or some part of the output voltage. In one embodiment, a comparator circuit comprised within a tracking ADC is configured to receive the analog feedback voltage at a first input and an analog reference voltage at a second input.
A digital target value signal may optionally be provided to the tracking ADC at 804. The target value signal may comprise a digital code that indicates (i.e., is a digital representation) of a desired DC-to-DC converter output voltage value that is requested by a user. In one embodiment, the digital target value signal may be converted to a voltage (e.g., by a DAC configured to generate a voltage based upon the digital target value signal). In one embodiment, the voltage may comprise the analog reference voltage.
At 806 the analog feedback voltage is compared to an analog reference voltage. The comparison may be performed by a comparator and results in a comparator signal that indicates whether the reference voltage is smaller than the feedback voltage (e.g., SC=“1”) or whether the reference voltage is larger than the feedback voltage (e.g., SC=“0”).
A digital ADC output signal, having a digital code, is generated by the tracking ADC in response to the comparison between the feedback voltage and a reference voltage at 808. The comparison produces a digital ADC output signal that results in a reference voltage that matches the feedback voltage as closely as possible. In particular, the digital ADC output signal may be incremented or decremented based upon the comparator signal (e.g., SC=“1” or “0”). The digital ADC output signal drives operation of the DC-to-DC converter by indicating an adjustment that is to be made to the output of the DC-to-DC converter (e.g., by telling the DC-to-DC converter to increase its output voltage or to decrease its output voltage). In one embodiment, the reference voltage may be based upon the digital target value signal.
The digital signal is provided to a DC-to-DC converter at 810. In one embodiment, the digital signal may be received by an analysis circuit configured to perform analysis of the digital code.
At 812 the digital code, comprised within the digital signal, is compared to a target code value. Based upon the comparison, the output voltage of the DC-to DC converter may be appropriately adjusted (e.g., raise or lower the output voltage VOUT). For example, if digital ADC output signal S1 has a first code that is larger than a target code value Scode it indicates to the DC-to-DC converter that it is outputting a voltage that is larger than the desired voltage and that the output voltage should be decreased. Similarly, if the digital ADC output signal S1 has a second, different, code that is smaller than the target code value Scode it indicates to a DC-to-DC converter that it is outputting a voltage VOUT that is smaller than the desired voltage and that the output voltage should be increased.
At 814 the output voltage of the DC-to-DC converter is adjusted. The output voltage of the DC-to-DC converter is adjusted in response to the comparison of the digital code to the target code value. For example, if the feedback voltage is lower than its target value the tracking ADC will produce codes lower than the target code Scode (e.g., as described in steps 806 and 808). After comparing these codes with Scode (e.g., as described in step 812) the DC-to-DC converter increases its output voltage.
It will be appreciated that method 800 may be iteratively performed to achieve a desired output voltage. For example, the adjustment to the output voltage of the DC-to-DC converter may be small so as to not achieve the desired output voltage in a single iteration of the method. For example, during a soft start interval, the method may provide for a DC output signal that is gradually ramped up to predetermined desired voltage level.
Although examples of techniques that are consistent with some implementations have been illustrated and described with respect to one or more implementations above, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, although a tracking ADC is illustrated as driving a digital DC-to-DC converter, the inventive concept of using a tracking ADC may also be applicable to AC-to-DC power converters. Furthermore, although various ADCs and digital codes are used within this disclosure these are only used to facilitate reader understanding and are not intended to limit the scope of the invention.
Furthermore, although the comparator provided herein is described as a two valued comparator, it will be appreciated that the comparator is not limited to a two valued comparator. For example, the tracking ADC provided herein may utilize one or more comparators configured to implement three comparator values during operation. One such exemplary three valued comparator system may have a comparator configured to receive digital signals from a logic circuit, wherein if the logic circuit outputs a digital error signal having a code with a “0”, it indicates to the DC-to-DC converter that it is outputting the desired voltage, if the logic circuit outputs a digital error signal having a code that is a negative number (e.g., “−1”) it indicates to the DC-to-DC converter that it is outputting a voltage that is larger than the desired voltage, and if the logic circuit outputs a digital error signal having a code that is a positive number (e.g., “1”) it indicates to the DC-to-DC converter that it is outputting a voltage that is smaller than the desired voltage.
Moreover, certain terms are used throughout the specification to refer to particular system components. As one skilled in the art will appreciate, different companies can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function herein. In this document the terms “including” and “comprising” are used in an open ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” (and variations thereof) is intended to mean either an indirect or direct electrical connection. Thus, if a first element couples to a second element, that connection may be a direct electrical connection, or may be an indirect electrical connection via other elements and connections.
Although various numeric values are provided herein, these numeric values are merely examples should not be used to limit the scope of the disclosure. Also, all numeric values are approximate.
In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.
