When a frame error is detected in received ADPCM code l(k) by error detector 22 using a cyclic redundancy check, a frame error detection signal is outputted to determination time adjustment section 20. In the event that a frame error is detected, determination time adjustment section 20 outputs an error detection signal indicating a frame period (for example, a period from a few hundred to a few thousand samples) where click noise suppression processing is effective to code substituter 21 and adaptive predictor 12.
When an error detection signal is received from determination time adjustment section 20, in the event that predetermined conditions are satisfied based on the values of a high-speed scale factor yu(k), low speed scale factor yl(k) and ADPCM code l(k), the code substituter 21 substitutes ADPCM code l(k) with predetermined code l′(k) across a frame period indicated by the error detection signal from the determination time adjustment section 20. The details of processing for substituting ADPCM code l(k) with predetermined code I′(k) are disclosed in Japanese Patent Laid-open Publication No. 2006-50476 and are not described here.
ADPCM code l(k) is for performing encoding and transfer after a differential signal d(k) for a prediction signal and a quantized PCM signal is quantized on the transmission side. Namely, at the adaptive quantizer on the transmission side, the differential signal d(k) is converter to a logarithm taking 2 as a base, and is then normalized by scale factor y(k). The value of the log2 (d(k))−y(k) obtained in this way is then quantized, and ADPCM code l(k) is generated by code substitution.
The adaptive de-quantizer 11 then generates a quantization differential signal dq(k) based on ADPCM code l(k) (or l′(k)) and quantization scale factor y(k), and outputs the quantization differential signal dq(k) to the adaptive predictor 12 with a limit function, regenerative signal calculator 13, and tone and changing point detector 17.
The adaptive predictor 12 with a limit function generates a prediction signal se(k) and polar prediction coefficient a2(k) based on quantization differential signal dq(k) and speed variable tr(k). The adaptive predictor 12 with a limit function executes limiting processing for suppressing click noise for an internal variable (partial prediction signal) for generating the prediction signal se(k) across a frame period indicated by an error detection signal from the determination time adjustment section 20.
The regenerative signal calculator 13 generates a regenerative signal sr(k) based on the quantization differential signal dq(k) and prediction signal se(k).
Output limiter 14 compresses a regenerative signal sr(k) to a PCM signal so(k).
Quantization scale factor adapter 15 generates scale factor y(k), high-speed scale factor yu(k) and low-speed scale factor yl(k) based on the ADPCM code l(k) (or l′(k)) and adaptive speed control variable al(k).
The scale factor y(k), high-speed scale factor yu(k) and low-speed scale factor yl(k) are generated as shown in the following equation.
y(k)=al(k)·yu(k−1)+[1−al(k)]·yl(k−1)
yu(k)(1−2−5)·y(k)+2−5·W [I(k)]
yl(k)(1−2−6)·yl(k)+2−6·yu(k)
The value of w[l(k)] is defined as shown in
Quantization scale factor adapter 15 outputs the scale factor y(k) to adaptive de-quantizer 11 and outputs low-speed scale factor yl(k) to the tone and changing point detector 17. Further, quantization scale factor adapter 15 outputs a high-speed scale factor yu(k−1) for one sample previous and low-speed scale factor yl(k−1) to code substituter 21.
Adaptive speed controller 16 generates an adaptive speed control variable al(k) based on the scale factor y(k), ADPCM code l(k) (or l′(k)), speed variable tr(k), and control variable td(k). The tone and changing point detector 17 generates a speed variable tr(k) and control variable td(k) based on the polar prediction coefficient a2(k), quantization differential signal dq(k), and low-speed scale factor yl(k).
The above signals are all sampled digital signals with the character k within parenthesis for each signal indicating sampling time.
Prediction signal se(k) is calculated as follows.
Here, sez(k) is calculated as follows.
Further, regenerative signal sr(k) is defined as follows.
s
r(k−i)=se(k−i)+dq(k−i)
With either prediction coefficient, sequential updating employing the simplified gradient method takes place.
In
The A1 display converter 80 converts a polar prediction coefficient A1 to floating point representation. The SR1 display converter 81 converts a regenerative signal SR1 to floating point representation. The multiplier 82 multiplies the polar prediction coefficient A1 and the regenerative signal SR1. WA1MANT display converter 85 converts the multiplication results from a floating point representation to an absolute value display. WA1MAG display converter 86 converts the multiplication results from an absolute value display to a two's compliment display and outputs this as prediction signal WA1.
WA1MANT display converter 85 then converts the floating point representation to an absolute value display in accordance with the following equation.
When WA1EXP<=26,
WA1MAG=(WA1MANT<7)>>(26−WA1EXP)
When WA1EXP>26,
WA1MAG=(WA1MANT<<7)<<(WA1EXP−26)
WA1EXP indicates a floating point representation exponent section (maximum value 28) for prediction signal WA1, WA1MANT indicates a floating point representation mantissa section (eight bit) for prediction signal WA1, and WA1MAG indicates an absolute value display (fifteen bit) for prediction signal WA1.
Here, the amount of left shift of WA1MANT is considered. WA1MAG is 15 bit data and no problems occur if the amount of left shift of WA1MANT of the eight bits of data is up to seven bits. However, in the event that a maximum value of 28 is taken and the value of WA1EXP is 27 or 28, WA1MANT is shifts eight or nine bits to the left. The most significant bit of WA1MANT is therefore shifted out due to the value of WA1MANT
The prediction signal WA1 calculator 58 with a limit function therefore executes the limit processing shown in
If a frame error has not occurred (step 501; NO), determination unit 83 determines whether or not the value of WA1EXP is 26 or less (step 502). If the value of WA1EXP is 26 or less (step 502; YES), WA1MANT display converter 85 executes calculation of WA1MAG=(WA1MANT<<7)>>(26-WA1EXP) (step 503). On the other hand, if the value of WA1EXP is 27 or 28 (step 502; NO), WA1MANT display converter 85 executes the calculation of WA 1 MA G (WA1MANT<<7)<<(WA1EXP−26) (step 504).
If a frame error occurs (step 501; YES). determination unit 83 determines whether the value of WA1EXP is 27 and the value of WA1MANT is larger than 0x7F, or the value of WA1EXP is 28 and the value of WA1MANT is larger than 0x3F (step 505). In the event that the value of WA1EXP is 27 and the value of WA1MANT is 0x7F or less, or in the event that the value of WA1EXP is 28 and the value of WA1MANT is 0x3F or less, the processing of step 502 is executed.
In the event that the value of WA1EXP is 27 and the value of WA1MANT is larger than 0x7F, or the value of WA1EXP is 28 and the value of WA1MANT is larger than 0x3F (step 505; YES), when the calculation of WA1MAG=(WA1MANT<<7)<<(WA1EXP−26) is executed, the uppermost bit of WA1MANT shifts out to the left and WA1MAG limiter 84 therefore substitutes a predetermined limit value (for example, 0x7F00) in WA1MAG
The adder 90 adds prediction signals WB1 to WB6 and outputs the results of this addition as SEZI. The SEZI shifter 96 shifts SEZI one bit to the right, and outputs the result as SEZ. The adder 91 adds SEZ1 and WA2 and outputs the results of this addition as preSEI. The adder 92 adds preSEI and WA1 and outputs the results of this addition as SEI. The SEI shifter 95 shifts SEZ one bit to the right, and outputs the result as SE.
The process of adding preSEI and WA1 is now considered. As described above, under certain conditions (step 505; YES), a limit value is substituted at WA1MAG In doing so, when preSEI and WA1 are added, it is possible that SEI may overflow.
The prediction signal adder 78 with a limit function therefore executes the limit processing shown in
In the event that an error detection signal is received (step 702; YES), the determination unit 93 determines whether or not the most significant bits of preSEI and WA1 are 9, and that the most significant bit of SEI is 1 (step 703). In the event that the most significant bits of preSEI and WA1 are 0 and the most significant bit of SEI is 1 (step 703; YES), it is shown that SEI code is determined as a result of the overflow, and SEI limiter 94 substitutes a positive limit value (for example, 0x7FF) in SEI (step 704).
In the event that the most significant bits for preSEI and WA1 respectively are 0 and the most significant bit of SEI is 0 (step 703; NO), the determination unit 93 determines whether or not the most significant bits of preSEI and WA1 are 1 and the most significant bit of SEI is 0 (step 705). In the event that the most significant bits of preSEI and WA1 are 1 and the most significant bit of SEI is 0 (step 705; YES), it is shown that SEI code is determined as a result of the overflow, and SEI limiter 94 substitutes a negative limit value (for example, 0x800) in SEI (step 706).
In the event that the most significant bits of preSEI and WA1 are 1 and the most significant bit of SEI is not 0 (step 705; NO), prediction signal adder 78 with a limit function omits the processing routine.
According to this embodiment, in the event that encoding errors occur for various input signals, it is possible to suppress click noise occurring due to code that could not be predicted or click noise occurring due to correct code after a few hundred samples to a few thousand samples from a frame errors are detected for, and it is possible to suppress deterioration of communication quality.
Number | Date | Country | Kind |
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2006-190775 | Jul 2006 | JP | national |