Patent Application
20140266103
Embodiments of the present invention relate generally to aspects of voltage regulation, and more specifically to digitally assisted regulation for an integrated capless low-dropout (LCO) voltage regulator.
Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as communication and multimedia programs. A processing system for such products may include multiple processors, complex memory systems including multi-levels of caches and memory for storing instructions and data, controllers, peripheral devices such as communication interfaces, and fixed function logic blocks configured, for example, on a single chip. At the same time, portable products have a limited energy source in the form of batteries that are often required to support high performance operations by the processing system and increasingly large memory capacities as functionality increases. Such concerns extend to personal computer products which are also being developed with efficient designs to operate with reduced overall energy consumption.
In such portable systems, one or more low-dropout (LDO) voltage regulators, also referred to as LDO regulators, are generally embedded on a power management chip to regulate one or more voltages for circuits on one or more chips. Each LDO regulator of the multiple LDO regulators is used to regulate a voltage for circuits in a specific power domain. Also, each power domain may experience a wide range of loads that vary over a wide range of frequencies. For example, in a portable cell phone device having integrated functions, such as video capture, modem functions, and a user interface, the processor's clock frequencies are adjusted to the task at hand to optimize power usage. Since tasks vary according to phone usage, the loads an LDO regulator must respond to are always changing and may change at a high frequency depending on program use of various on-chip functions.
A particular problem associated with changing loads, for example on bringing up a circuit, such as a digital signal processor circuit, from a sleep state, is voltage undershoot, where a supply voltage to the circuit drops below an operating voltage level. If the voltage drop is large enough, the circuit may experience incorrect operation, for example by changing an existing state of operation. One approach to addressing this problem has been to use a large external capacitor on an LDO regulator's output to stabilize its voltage. As a consequence, embedding an LDO regulator in a power domain with a target circuit requires an external pin for the large external capacitor. Also, for efficient operation of the LDO regulator, the external pin is required to be of low inductance, a difficult package and design requirement. A large inductance will impede the current flow and cause voltage undershoot that may render the system to be not functional. Since impedance equals inductance (L)*dl/dt, the rate of change of the current, a large impedance limits the current flowing onto chip from an external cap. Once charge from on chip caps are depleted to the extent that it is not filled and the load current is not supplied either by an LDO regulator due to limited bandwidth or by the external cap due to large lead inductance, the processor supply drops below a required level which could cause circuit timing errors and thus functional errors.
For example,
Among its several aspects, the present disclosure recognizes that it is desirable to provide more efficient methods and apparatuses for embedded voltage regulation to reduce or remove undershoot voltage problems that occur on load changes. To such ends, an embodiment of the invention addresses a method for low-dropout regulation. A digital to analog converter (DAC) is enabled in response to an advance notification signal supplied by a system circuit, wherein the advance notification signal indicates a change in load requiring increased current is to begin in a predetermined period. A current provided by the DAC is combined with a current provided by a low-dropout (LDO) regulator to supply the system circuit, wherein voltage undershoot to the system circuit is reduced or removed as addressed further below.
Another embodiment addresses an apparatus for low-dropout regulation. A low-dropout (LDO) regulator is configured to provide linear regulation of voltage and current. A digital assisted regulator is coupled to the LDO regulator and configured to provide digital assisted regulation of voltage and current. A system circuit is coupled to the digital assisted regulator and to the LDO regulator to receive supply voltage and current. The system circuit has an advance notification circuit that is configured to notify the digital assisted regulator of an impending load change in time for the digital assisted regulator to supply current to the system circuit required by the load change.
Another embodiment addresses an apparatus for system assisted low-dropout regulation. A system circuit having an advance notification circuit is configured to generate an advance notification signal that a load change is to occur in a predetermined time period. A low-dropout (LDO) regulator is configured for providing linear regulation of voltage and current to the system circuit, coupled to the system circuit to receive the advance notification signal and expand the bandwidth of the LDO regulator during the time of the load change in response to the advance notification signal.
Another embodiment addresses a computer readable non-transitory medium encoded with computer readable program data and code. A digital to analog converter (DAC) is enabled in response to an advance notification signal supplied by a system circuit, wherein the advance notification signal indicates a change in load requiring increased current is to begin in a predetermined period. A current provided by the DAC is combined with a current provided by a low-dropout (LDO) regulator to supply the system circuit, wherein voltage undershoot to the system circuit is reduced or removed.
Another embodiment addresses an apparatus for low-dropout regulation. Means is utilized for digital assisted regulation of a voltage and current. Means is utilized for linear regulation of a voltage and current coupled to the digital regulation means and configured to operate in conjunction with the digital regulation means. Means is utilized for providing an advance notification to the digital regulation means of an impending load change in time to supply current to the system circuit required by the load change.
A further embodiment addresses an apparatus for system assisted low-dropout regulation. Means is utilized to generate an advance notification signal that a load change is to occur in a predetermined time period. Means is utilized to receive the advance notification signal and expand the bandwidth of the LDO regulator during the time of the load change in response to the advance notification signal.
It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
Various aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein:
The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention.
To address the problems of package pin requirements, board real estate for external large capacitors, voltage undershoot, and the like, a different approach to providing voltage regulation is utilized as shown in
The digital controller 204 and transistor assembly 207 are configured to operate as an integrated current digital to analog controller (IDAC) and in parallel with the LDO regulator 205 and current ADC 206. For example, the transistor assembly 207 is coupled to an LDO output device 216 at the supply voltage Vdd
In another embodiment, the IDAC 204 and transistor assembly 207 balances the current it provides, according to the current ADC circuit 206, with the current provided by the LDO regulator. The IDAC 204/207 takes input from the current ADC 206 to supply the static or slow varying current which is required. The IDAC 204/207 is used to combine with the LDO 205 to extend the LDO capacity based on a predetermined current threshold that the LDO 205 supplies. The current from LDO can be divided into 3 ranges. When the current demanded is in excess of the high predetermined threshold, the current ADC 206 generates an output code 11 and the IDAC controller 204 switches more units ON in the transistor assembly 207 to reduce an amount of current being supplied from LDO 205. This process continues until the LDO current drops below the high threshold and the current ADC 206 generates an output code 01. In another operating scenario, if the LDO 205 sources current less than a lower threshold, the current ADC 206 generates an output code 00. Based on this code of 00, the IDAC controller 204 keeps turning OFF units in the transistor assembly 207 until the current ADC 206 generates an output code 01 or until all the IDAC units in the transistor assembly 207 are OFF. For static current, the range of current LDO delivers is predetermined. The IDAC 204/207 greatly extends the static current capacity to support the supply of current dissipated by on chip leakage, such as leakage in access to 300 mA for example which may occur at a fast-fast (FF) process corner and at 110 degrees Celsius. This combination provides an advanced ready state to allow a quick response time of the IDAC 204/207 to assist the LDO regulator 205 with drastic and fast dynamic load changes which may occur. Thus, the combination of a digital assisted regulator with an LDO regulator addresses the problems of package pin requirements, board real estate for external large capacitors, and voltage undershoot and extends the current delivery capacity to make the LDO stable in a much larger load current range than an analog LDO could handle alone. The LDO regulator is designed for a prespecified current capacity while the IDAC regulator current capacity can be extended without causing stability concerns.
The current ADC 206 can be configured with a single threshold comparator to supply a single bit or a plurality of threshold comparators to provide a plurality of bits depending on the granularity of control desired. As the LDO regulator current increases as determined by the Iref current 222 monitored by the current ADC 206, the current ADC 206 converts the current going through LDO 205 into digital bits for the digital controller 204 to monitor. If the LDO starts to source too much current, the digital controller 204 increases the IDAC current at the transistor assembly 207, such that the LDO current falls back below or to a predetermined max value. The inverse is also true; when the LDO 205 is sourcing too little current, the IDAC current is reduced until the LDO sources more than a predetermined minimum current. If the load current from the processor load 224 is smaller than the minimum current, the transistor assembly 207 is completely turned off and all the current is supplied from the LDO 205. The LDO 205 also sources any fast transient current that may occur.
The transistor assembly 207 is a configuration of a plurality of transistors controlled in groups to increase or decrease current. For example, the transistor assembly 207 may be made up of sixty four groups of twenty five transistors in each group, such that each group of transistors is controlled by the digital controller 204 through the Ctrl signals 228. Groups of transistors are also referred to as units. The transistor assembly 207 is sized in reference to the size of the LDO pass transistor 216. The devices are matched with the same small unit in terms of gate length/width/fingers/multiplicity. The transistor unit size is chosen such that when combined with the current ADC step size and clock frequency a smooth current flow is provided. Thus, there is no contention of the analog control loop and the digital control loop. The number of transistors in each IDAC group is determined by an expected max current that the transistor assembly 207 is expected to handle. The number of transistors is generally not limited by any other factors. Only a small number of groups of the transistor assembly 207, however, is used for the undershoot control. The digital controller 204 is controlled with shift registers, for example. A small number, such as 48 IDAC units, are fully turned on when the advance notification signal 218 is received to reduce the voltage drop due to a current change. This small number is able to make a fast transition and thus shorten a time that the system takes to transition to normal regulation. The other transistors of the IDAC unit will be turned on by the digital controller 204 based on detected leakage current. Using various numbers of groups of transistors in the transistor assembly 207 allows the digital controller 204 to ramp voltages either up or down depending on the required response. In a similar manner, as the LDO regulator current decreases in response to load current, the digital controller 204 decreases the output current supplied by the transistor assembly 207 as determined by the current ADC 206. For example, with a two bit current ADC 206 comprised of two threshold comparators, an output code of “00” indicates decrease IDAC output until the output code become 01 and with an output code of “01” keep the IDAC current at present level. The IDAC output would supply a predetermined current capacity and with an output code of “11” the IDAC output would increase until the code becomes 01. Currently, an ADC 206 output code of “10” is reserved in a current implementation and will not occur.
In anticipation of the system circuit turning on, at time 125 ns 306, the advance notice signal 218 is turned on. The digital controller 204 upon receiving the pre-ON advance notice signal 218, drives the transistor assembly Ctrl signals 228 to turn on the transistor assembly 207, this is highlighted by transition 308. In response to the Ctrl signals 228 turning from a completely off code during period 306 to a fully on code during period 316, the Vdd_load 209 ramps up to a full on level such as 1.0 volt in this scenario as highlighted by transition 310. The system circuit 208 turns on at a specified time period delay 312 from the generation of the advance notice signal 218, for example 50 ns later. The delay 312 would be different in different systems and is chosen such that a selected portion of the transistor assembly 207 is fully on before the load increases. The delay 312 may also have to take into account ramping the Vdd_load voltage up to the desired level. The load current Iload 224 to the system circuit 208 ramps up from the 50 μA level to 200 milliampere (mA) level in approximately 20 ns 314. Such a rapid current surge generally causes a significant voltage undershoot in prior art systems such as the LDO regulator 104 shown in
After a time delay 316, that allows any effect of the load change to be settled out, the digital controller 204 reduces the Ctrl signal 228 driving the transistor assembly 207, for example by turning a subset of groups of transistors in the transistor assembly 207 off in response to the current ADC 206. By having less transistors driving the transistor assembly 207, the Vdd_load 209 is reduced to an operating voltage level, such as 0.8 volts, required by the system circuit 208 and the voltage level is controlled by the LDO 205. The delay 318 to ramp the voltage down to operating levels is determined by the IDAC 204/207 design and load current levels according to system requirements. The advance notice signal 218 is also removed which may occur after sufficient time to ensure the digital controller 204 has received the notification of the upcoming load change. For example, the advance notification signal 218 may be an event trigger pulse that generally lasts two or three clock cycles. The system now operates in a balanced mode with part of the current supplied by the transistor assembly 207 and part by the LDO regulator 205.
In an illustrative example, the GPT processor 536 and CoP 538 are configured to access data or program instructions stored in the memories of the L1 I & D caches 549, the L2 cache/TCM 550, and in the system memory 508 to provide data transactions as required for system operation.
The wireless interface 528 may be coupled to the processor complex 506 and to the wireless antenna 516 such that wireless data received via the antenna 516 and wireless interface 528 can be provided to the MSS 540 and shared with CoP 538 and with the GPT processor 536. The camera interface 532 is coupled to the processor complex 506 and is also coupled to one or more cameras, such as a camera 522 with video capability. The display controller 530 is coupled to the processor complex 506 and to the display device 520. The coder/decoder (Codec) 534 is also coupled to the processor complex 506. The speaker 524, which may comprise a pair of stereo speakers, and the microphone 526 are coupled to the Codec 534. The peripheral devices and their associated interfaces are exemplary and not limited in quantity or in capacity. For example, the input device 518 may include a universal serial bus (USB) interface or the like, a QWERTY style keyboard, an alphanumeric keyboard, and a numeric pad which may be implemented individually in a particular device or in combination in a different device.
The GPT processor 536 and CoP 538 are configured to execute software instructions 510 that are stored in a non-transitory computer-readable medium, such as the system memory 508, and that are executable to cause a computer, such as the dual core processors 536 and 538, to execute a program to provide data transactions as required by system operation. The GPT processor 536 and the CoP 538 are configured to execute the software instructions 510 and operate on data that are accessed from the different levels of cache memories, such as the L1 instruction and data caches 549, and the system memory 508.
In a particular embodiment, the system core 504 is physically organized in a system-in-package or on a system-on-chip device. In a particular embodiment, the system core 504, organized as a system-on-chip device, is physically coupled, as illustrated in
The portable device 500 in accordance with embodiments described herein may be incorporated in a variety of electronic devices, such as a set top box, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, tablets, a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or any combination thereof.
The various illustrative logical blocks, modules, circuits, elements, or components described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic components, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration appropriate for a desired application.
The dual core processors 536 and 538 of
While the invention is disclosed in the context of illustrative embodiments for use in processor systems, it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below. For example, a fixed function implementation may also utilize various embodiments of the present invention.
