Patent Application
20210408724
Embodiments generally relate to memory structures. More particularly, embodiments relate to dual inline memory module (DIMM) retention assemblies for compression mount technology (CMT) and land grid array (LGA) connector loading.
Current DIMM form factors use a card edge connector. For example, a typical Double Data Rate 5 (DDR5) connector latch design merely secures the DIMM into position. As a result, signal integrity performance (e.g., bandwidth) may decrease and pin counts (e.g., capacity) may be limited.
The various advantages of the embodiments will become apparent to one skilled in the art by reading the following specification and appended claims, and by referencing the following drawings, in which:
Turning now to
The memory module 32 may be part of a memory device that includes non-volatile memory and/or volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of data stored by the medium. In one embodiment, the memory structure is a block addressable storage device, such as those based on NAND or NOR technologies. A storage device may also include future generation nonvolatile devices, such as a three-dimensional (3D) crosspoint memory device, or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the storage device may be or may include memory devices that use silicon-oxide-nitride-oxide-silicon (SONOS) memory, electrically erasable programmable read-only memory (EEPROM), chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thiristor based memory device, or a combination of any of the above, or other memory. The term “storage device” may refer to the die itself and/or to a packaged memory product. In some embodiments, 3D crosspoint memory may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In particular embodiments, a memory module with non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD235, JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standard (the JEDEC standards cited herein are available at jedec.org).
Volatile memory is a storage medium that requires power to maintain the state of data stored by the medium. Examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of the memory modules complies with a standard promulgated by JEDEC, such as JESD79F for Double Data Rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, or JESD79-4A for DDR4 SDRAM (these standards are available at jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
Additional Notes and Examples:
Example 1 includes a performance-enhanced computing system comprising a memory module, a motherboard, and a latch assembly coupled to the memory module and the motherboard, the latch assembly including a connector coupled to the motherboard, a first lever coupled to the connector via a first pivot point, an L-shaped load member extending through an opening in the first lever, a second lever coupled to the L-shaped load member via a second pivot point, and a spring to bias the L-shaped load member away from the opening in the first lever.
Example 2 includes the computing system of Example 1, wherein the L-shaped load member includes a protrusion extending away from the spring.
Example 3 includes the computing system of Example 2, wherein in a latched position, the first lever rotates toward the memory module and the spring engages the protrusion with a recess in the memory module.
Example 4 includes the computing system of Example 1, wherein in an open position, the second lever causes the L-shaped load member to compress the spring and the first lever rotates away from the memory module.
Example 5 includes the computing system of Example 1, wherein the connector is a land grid array connector.
Example 6 includes the computing system of Example 1, wherein the connector is a compression mount technology connector.
Example 7 includes the computing system of any one of Examples 1 to 6, wherein the first lever is an L-shaped lever and the second lever is a longitudinal lever.
Example 8 includes a latch assembly comprising a connector, a first lever coupled to the connector via a first pivot point, an L-shaped load member extending through an opening in the first lever, a second lever coupled to the L-shaped load member via a second pivot point, and a spring to bias the L-shaped load member away from the opening in the first lever.
Example 9 includes the latch assembly of Example 8, wherein the L-shaped load member includes a protrusion extending away from the spring.
Example 10 includes the latch assembly of Example 9, wherein in a latched position, the first lever rotates toward a memory module and the spring engages the protrusion with a recess in the memory module.
Example 11 includes the latch assembly of Example 8, wherein in an open position, the second lever causes the L-shaped load member to compress the spring and the first lever rotates away from a memory module.
Example 12 includes the latch assembly of Example 8, wherein the connector is a land grid array connector.
Example 13 includes the latch assembly of Example 8, wherein the connector is a compression mount technology connector.
Example 14 includes the latch assembly of any one of Examples 8 to 13, wherein the first lever is an L-shaped lever and the second lever is a longitudinal lever.
Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems on chip (SoCs), SSD/NAND controller ASICs, and the like. In addition, in some of the drawings, signal conductor lines are represented with lines. Some may be different, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.
Example sizes/models/values/ranges may have been given, although embodiments are not limited to the same. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller size could be manufactured. In addition, well known power/ground connections to IC chips and other components may or may not be shown within the figures, for simplicity of illustration and discussion, and so as not to obscure certain aspects of the embodiments. Further, arrangements may be shown in block diagram form in order to avoid obscuring embodiments, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the embodiment is to be implemented, i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments, it should be apparent to one skilled in the art that embodiments can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and carry no particular temporal or chronological significance unless otherwise indicated.
As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrases “one or more of A, B or C” may mean A; B; C; A and B; A and C; B and C; or A, B and C.
Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.
