BACKGROUND
The present disclosure relates generally to dimming controllers and dimming methods, and, more particularly, to dimming controllers suitable of receiving a dimming signal no matter it is a pulse-width-modulation (PWM) signal or a direct-current (DC) signal.
Light emitting diode (LED), due to its characteristics in high power efficiency, compact product size, and long lifespan, has been widely adapted by lighting appliances and backlight modules. Until recently, most of cold cathode fluorescent lamps (CCFL) in the backlight modules of TV or computer display panels, for example, are replaced by LED modules.
LED modules usually need dimming controllers to perform light dimming, so as to adjust the luminance of a display panel for example. There are two different methods in the art to dim the luminance of a LED module: PWM dimming and DC dimming. PWM dimming, also named digital dimming, employs a PWM or digital signal that jumps quickly back-and-forth between levels of “0” and “1” in logic to determine the duty cycle of a LED module, the ratio of the time when the LED module emits light to the cycle time of the PWM signal. For example, when the PWM signal is “1” in logic, the luminance of the LED module is in its maximum, and when the PWM signal is “0”, it is zero, not emitting light. In other words, PWM dimming makes a LED module blinking. In contrast, DC dimming, also known as analog dimming or resistive dimming, makes a LED module emitting light continuously while the luminance of the LED module corresponds to the voltage level of a DC or analog signal.
For having more market share, a dimming controller should accommodate a dimming signal no matter the dimming signal is of PWM or of DC, and provide appropriate luminance control.
BRIEF DESCRIPTION OF THE DRAWINGS
Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted.
The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 illustrates dimming controller 10 that controls the luminance of light-emitting device LT via power transistor MNDRV;
FIG. 2 demonstrates dimming controller 10a;
FIG. 3 shows the correlation between dimming signal SDIM, saw-wave signal SSAW and PWM signal SPWM;
FIG. 4 exemplifies the waveform of dimming signal SDIM;
FIG. 5 shows dimming methods 60a in use of dimming controller 10a in FIG. 2;
FIG. 6 demonstrates dimming controller 10b;
FIG. 7 shows dimming methods 60b in use of dimming controller 10b in FIG. 6;
FIG. 8 demonstrates dimming controller 10c;
FIG. 9 shows dimming method 60c in use of dimming controller 10c in FIG. 8;
FIG. 10 demonstrates dimming controller 10d; and
FIG. 11 shows dimming method 60d in use of dimming controller 10d in FIG. 10.
DETAILED DESCRIPTION
According to embodiments of the invention, FIG. 1 illustrates dimming controller 10 that controls the luminance of light-emitting device LT via power transistor MNDRV.
Power transistor MNDRV could be a NMOS transistor, acting as a current driver providing current with a proper magnitude to light-emitting device LT. Light-emitting device LT could be one or plurals of light-emitting diodes connected in series or in parallel. Dimming controller 10 provides driving signal SDRV to the control gate of power transistor MNDRV. The current flowing through light-emitting device LT is monitored by dimming controller 10, as it is sensed by current-sense resistor RCS to provide current-sense signal VCS at current-sense node CS. Dimming controller 10 receives dimming signal SDIM from input node DIM to provide driving signal SDRV accordingly.
As shown in FIG. 1, the configuration of dimming controller 10 enables three different kinds of external connection to perform dimming control. For the first one, external circuit (not shown) generates and provides DC voltage VDC used as dimming signal SDIM to input node DIM, and the voltage level of DC voltage VDC represents the luminance of light-emitting device LT. For the second one, variable resistor RDIM connects between input node DIM and ground voltage GND, and the resistance of variable resistor RDIM is converted by dimming controller 10 into DC voltage VDC representing the luminance of light-emitting device LT. How the resistance of variable resistor RDIM is converted into DC voltage VDC at input node DIM will be detailed later on. For the third one, external circuit generates and provides PWM signal SDIM-PIM used as dimming signal SDIM to input node DIM, and the duty cycle of PWM signal SDIM-PWM represents the luminance of light-emitting device LT.
In other words, dimming signal SDIM could be of DC or of PWM. Dimming signal SDIM could be categorized into one of two types: DC and PWM.
FIG. 2 demonstrates dimming controller 10a, which could be dimming controller 10 in FIG. 1 according to embodiments of the invention. Dimming controller 10a has type identifier 12, DC-to-PWM converter 16, multiplexer 17a, LED driver 14a, and constant current source 31.
DC-to-PWM converter 16 is a signal converter and, if dimming signal SDIM is identified as of DC, DC-to-PWM converter 16 converts dimming signal SDIM into PWM signal SPWM. Shown in FIG. 2, DC-to-PWM converter 16 has signal generator 20, operational amplifier 24 and comparator 22. Please refer to FIG. 3, showing the correlation between dimming signal SDIM, saw-wave signal SSAW and PWM signal SPWM. Configured as a unity-gain buffer, operational amplifier 24 reproduces the voltage level of dimming signal SDIM at the non-inverting input of comparator 22. Signal generator 20 provides the inverting input of comparator 22 saw-wave signal SSAW, which, like a clock, is periodically reset to its original starting voltage. Comparator 22 compares saw-wave signal SSAW with dimming signal SDIM to generate PWM signal SPWM. As shown in FIG. 3, PWM signal SPWM is “0” in logic when saw-wave signal SSAW exceeds dimming signal SDIM, and “1” in logic when saw-wave signal SSAW is lower than dimming signal SDIM.
Type identifier 12 is connected to input node DIM, for identifying whether dimming signal SDIM at input node DIM is of DC or of PWM, and accordingly provides selection signal SSEL to control multiplexer 17a. Type identifier 12 in FIG. 2 makes selection SDIM “1” in logic if it identifies dimming signal SDIM as of PWM, and “0” in logic if it identifies dimming signal SDIM as of DC.
According to embodiments of the invention, selection signal SSEL is determined in response to edges of dimming signal SDIM. FIG. 4 exemplifies the waveform of dimming signal SDIM that has two falling edges FA1 and FA2, and a rising edge RA1. Type identifier 12 provides selection signal SSEL based on whether there are an enough number of significant edges within a predetermined period of time. An edge is significant to be an edge of a PWM signal when its tilt is large enough. For example, if there are more than 4 rising or falling edges found within a window of 8 ms and each of these edges has a slope whose absolute value exceeds 0.1V/us, type identifier 12 identifies dimming signal SDIM as of PWM, making selection signal SSEL “1” in logic. Two criteria must be satisfied to make selection signal SSEL “1” in logic, for example. The first one is the count of rising or falling edges in a window of 8 ms must be larger than 4. The second one is each of these edges has a slope whose absolute value exceeds 0.1V/us. In the opposite, once type identifier 12 cannot find 4 edges, each having a tilt large enough, within a window of 8 ms for example, it identifies dimming signal SDIM as of DC, making selection signal SSEL “0” in logic.
Taking the waveform in FIG. 4 for example, type identifier 12, according to an embodiment of the invention, deems falling edge FA1 starting when dimming signal SDIM goes down below reference voltage VREF-H and starts a window of delay time TDELAY. At the end of delay time TDELAY, type identifier 12 compares dimming signal SDIM with reference voltage VREF-L, so as to know whether the absolute slope value of falling edge FA1 exceeds (VREF-H−VREF-L)/TDELAY or not. Analogously, type identifier 12 deems rising edge RA1 starting when dimming signal SDIM goes up over reference voltage VREF-L and starts another window of delay time TDELAY. At the end of delay time TDELAY, type identifier 12 compares dimming signal SDIM with reference voltage VREF-H, so as to know whether the absolute slope value of rising edge RA1 exceeds (VREF-H−VREF-L)/TDELAY. In another embodiment of the invention, type identifier 12 checks whether or not the falling time for dimming signal SDIM going down from reference voltage VREF-H to reference voltage VREF-L is longer than delay time TDELAY, so as to know whether a falling edge is significant enough to be a falling edge of a PWM signal. The rising time for dimming signal SDIM rising from reference voltage VREF-L to reference voltage VREF-H is also compared with delay time TDELAY to know whether a rising edge could be deemed as a rising edge of a PWM signal. If there are an enough number of edges each having an absolute slope value larger than (VREF-H−VREF-L)/TDELAY, then dimming signal SDIM looks like a PWM signal, and selection signal SSEL becomes “1”. Otherwise, dimming signal SDIM should be a DC signal, and selection signal SSEL becomes “0”.
Multiplexer 17a in FIG. 2 has digital buffer 18 and multi-input, single-output switch 26. Digital buffer 18 is a signal buffer that reproduces and provides dimming signal SDIM to multi-input, single-output switch 26 if dimming signal SDIM is identified as of PWM. Controlled by type identifier 12, multiplexer 17a has two inputs receiving PWM signal SPWM and dimming signal SDIM respectively. When type identifier 12 identifies dimming signal SDIM as of DC, multiplexer 17a is controlled to select PWM signal SPWM and forward it to LED driver 14a, while isolating dimming signal SDIM from LED driver 14a. When type identifier 12 identifies dimming signal SDIM as of PWM, multiplexer 17a isolates PWM signal SPWM from LED driver 14a, and digital buffer 18 passes dimming signal SDIM on to multi-input, single-output switch 26, which, as controlled by selection signal SSEL, forwards dimming signal SDIM to LED driver 14a. What multiplexer 17a outputs to LED driver 14a is always a PWM signal, which is either dimming signal SDIM or PWM signal SPWM, where PWM signal SPWM represents dimming signal SDIM when dimming signal SDIM is of DC.
Selection signal SSEL shown in FIG. 2 controls multiplexer 17a only, but the invention is not limited to however. According to embodiments of the invention, when dimming signal SDIM is identified as of PWM, DC-to-PWM conversion is unnecessary, so type identifier 12 sends selection signal SSEL to disenable or shut down DC-to-PWM converter 16, saving electric power. In the opposite, if dimming signal SDIM is identified as of DC, digital buffer 18 is optionally shut down or disenabled to save electric power.
LED driver 14a receives a PWM signal only, and controls power transistor MNDRV to regulate current flowing through light-emitting device LT in response to what multiple-input, single-output switch 26 outputs. If the output of multiple-input, single-output switch 26 is “1” in logic, level shifter 28 outputs reference voltage VREF, and operational amplifier 30 makes the current through light-emitting device LT about VREF/RCS, where RCS is the resistance of current-sense resistor RCS. If the output of multiple-input, single-output switch 26 is “0” in logic, level shifter 28 outputs 0V, and operational amplifier 30 makes the current through light-emitting device LT about 0.
Constant current source 31 provides constant current ISET, which, if there is variable resistor RDIM connected between input node DIM and ground voltage GND, goes through variable resistor RDIM to generate at input node DIM DC voltage VDC used as dimming signal SDIM. Accordingly, constant current ISET converts the resistance of variable resistor RDIM into DC voltage VDC. While DC voltage VDC or PWM signal SDIM-PWM is directly supplied or defined from an external circuit with low output impedance, constant current ISET could not affect DC voltage VDC or PWM signal SDIM-PWM since constant current ISET is very small in magnitude.
FIG. 5 shows dimming method 60a in use of dimming controller 10a in FIG. 2.
In step 62, dimming controller 10a receives at input node DIM dimming signal SDIM, which could be a PWM signal or a DC signal.
In step 64 following step 62, type identifier 12 identifies whether dimming signal SDIM is of PWM or of DC, to generate selection signal SSEL, which controls multiplexer 17a.
Step 68a follows step 64 if dimming signal SDIM is identified as of DC. DC-to-PWM converter 16 converts dimming signal SDIM into PWM signal SPWM.
Step 70a, in response to selection signal SSEL generated in step 64, makes multiplexer 17a select PWM signal SPWM and forwards it to LED driver 14a, which drives light-emitting device LT accordingly. Meanwhile, the signal path for dimming signal SDIM from input node DIM, via digital buffer 18, and to LED driver 14a is disconnected. In one embodiment of the invention, step 70a disenables or shuts down digital buffer 18.
Step 72a, in response to selection signal SSEL that indicates dimming signal SDIM as a PWM signal, makes multiplexer 17a select dimming signal SDIM and forward it via digital buffer 18 and multiple-input, single-output switch 26 to LED driver 14a driving light-emitting device LT. Meanwhile, multiplexer 17a isolates PWM signal SPWM from LED driver 14a.
Dimming controller 10a in FIG. 2 and dimming method 60a in FIG. 5 have advantages as follows. If dimming signal SDIM is of DC, PWM signal SPWM representing dimming signal SDIM is generated for LED driver 14a to drive light-emitting device LT. If dimming signal SDIM is of PWM, dimming signal SDIM is forwarded honestly to LED driver 14a, which faithfully and quickly responds to turn ON or OFF light-emitting device LT. No matter dimming signal SDIM is a PWM signal or a DC signal, dimming controller 10a can always provide a proper PWM signal to LED driver 14a to drive light-emitting device LT appropriately.
FIG. 6 demonstrates dimming controller 10b, which could be dimming controller 10 in FIG. 1 according to embodiments of the invention. Dimming controller 10b has type identifier 12, PWM-to-DC converter 19, multiplexer 17b, LED driver 14b, and constant current source 31. Several devices or circuits in FIG. 6 have been disclosed or taught by FIG. 2 and the relevant paragraphs, and their function and operation are not repeatedly detailed for brevity.
PWM-to-DC converter 19 is a signal converter and, if dimming signal SDIM is of PWM, it is capable of converting dimming signal SDIM into DC signal SDC. Shown in FIG. 6, PWM-to-DC converter 19 has digital buffer 18, resistor R1 and capacitor C1. Digital buffer 18 reproduces the logic value of dimming signal SDIM and provides it to resistor R1. Resistor R1 and capacitor C1 together form a low-pass filter, capable of generating DC signal SDC whose voltage level represents the duty cycle of dimming signal SDIM.
Multiplexer 17b in FIG. 6, controlled by type identifier 12, has two inputs receiving DC signal SDC and dimming signal SDIM respectively. Multiplexer 17b has operational amplifier 24 and multiple-input, single-output switch 26. When type identifier 12 identifies dimming signal SDIM as of DC, operational amplifier 24, acting as a unity-gain buffer and a signal buffer, reproduces dimming signal SDIM at its output and forwards dimming signal SDIM to multiple-input, single-output switch 26, which continuously forwards dimming signal SDIM to LED driver 14b, but blocks DC signal SDC from reaching LED driver 14b. When type identifier 12 identifies dimming signal SDIM as of PWM, multi-input, single-output switch 26 in FIG. 6, as controlled by selection signal SSEL, forwards DC signal SDC to LED driver 14b and blocks dimming signal SDIM from reaching LED driver 14b. What multiplexer 17b outputs to LED driver 14a is always a DC signal, which is either dimming signal SDIM or DC signal SDC, where DC signal SDC represents dimming signal SDIM if dimming signal SDIM is of PWM.
LED driver 14b receives a DC signal only, and controls power transistor MNDRV to regulate current flowing through light-emitting device LT in response to what multiple-input, single-output switch 26 outputs. If the output of multiple-input, single-output switch 26 has voltage level VOUT, operational amplifier 30 makes the current through light-emitting device LT about VOUT/RCS.
FIG. 7 shows dimming method 60b in use of dimming controller 10b in FIG. 6. Some steps in FIG. 7 are the same or similar with corresponding steps in FIG. 5, so they are not repeatedly detailed here since they are comprehensible in view of related disclosure in the previous paragraphs.
Step 72b, in response to selection signal SSEL that indicates dimming signal SDIM is a DC signal, makes multiplexer 17b select dimming signal SDIM and forward it via multiple-input, single-output switch 26 to LED driver 14b driving light-emitting device LT. Meanwhile, selection signal SSEL causes multiplexer 17b to isolate DC signal SDC from LED driver 14b.
Step 68b follows step 64 if dimming signal SDIM is identified as of PWM. PWM-to-DC converter 19 converts dimming signal SDIM into DC signal SDC.
Step 70b, in response to selection signal SSEL generated in step 64, follows step 68b. Step 70b makes multiplexer 17b select DC signal SDC and forward it to LED driver 14b, which drives light-emitting device LT accordingly. Meanwhile, the signal path for dimming signal SDIM from input node DIM, via operational amplifier 24, and to LED driver 14b is interrupted.
Selection signal SSEL shown in FIG. 6 controls multiple-input, single-output switch 26 only, but the invention is not limited to however. According to embodiments of the invention, if dimming signal SDIM is identified as of PWM, operational amplifier 24 is optionally shut down or disenabled to save electric power. Similarly, when dimming signal SDIM is identified as DC, type identifier 12 sends selection signal SSEL to disenable or shut down digital buffer 18, saving electric power.
Dimming controller 10b in FIG. 6 and dimming method 60b in FIG. 7 have advantages as follows. If dimming signal SDIM is of DC, dimming signal SDIM is forwarded honestly to LED driver 14b, which faithfully and analogically adjusts the current through light-emitting device LT. The current through light-emitting device LT is VOUT/RCS if the voltage level of dimming signal SDIM is VOUT. While dimming signal SDIM is identified as PWM, DC signal SDC, representing the duty cycle of dimming signal SDIM, is generated and forwarded to LED driver 14b to drive light-emitting device LT. No matter dimming signal SDIM is a PWM signal or a DC signal, dimming controller 10b can always provide a proper DC signal to LED driver 14b to drive light-emitting device LT appropriately.
This invention is not only useful for driving LEDs however, but could be also applicable for driving other kinds of lighting apparatuses.
FIG. 8 demonstrates dimming controller 10c, which could be dimming controller 10 in FIG. 1 according to embodiments of the invention. Dimming controller 10c has type identifier 12, PWM-to-DC converter 19, multiplexer 17b, DC-to-PWM converter 16a, LED driver 14a, and constant current source 31. Several devices or circuits in FIG. 8 have been disclosed or taught by FIG. 2 or 6 and the relevant paragraphs, and their function and operation are not repeatedly detailed for brevity.
PWM-to-DC converter 19 is a signal converter, capable of converting dimming signal SDIM, if it is identified as of PWM, into DC signal SDC. Shown in FIG. 8, PWM-to-DC converter 19 includes digital buffer 18 and low-pass filter 15. Digital buffer 18 provides at an end of resistor R1 temporary PWM signal SBPWM, which reproduces the logic value of dimming signal SDIM. Resistor R1 and capacitor C1 together form low-pass filter 15, low-pass filtering temporary PWM signal SBPWM to generate DC signal SDC whose voltage level represents the duty cycle of dimming signal SDIM.
The logic value of temporary PWM signal SBPWM always follows that of dimming signal SDIM, but temporary PWM signal SBPWM might differ from dimming signal SDIM in logic voltage level. For example, the logic voltage level of “0” in logic for both temporary PWM signal SBPWM and dimming signal SDIM is 0V, but the logic voltage level of “1” in logic for temporary PWM signal SBPWM could be different from that for dimming signal SDIM. Dimming signal SDIM, which originates from an external circuit, could be 1V, 3V or 5V to represent “1” in logic, meaning the logic voltage level of dimming signal SDIM for “1” in logic is 1V, 3V or 5V. The logic voltage level of temporary PWM signal SBPWM for “1” in logic is predetermined internally by digital buffer 18, and could be a constant, 5V for example. Therefore, digital buffer 18 acts as a level shifter, and makes the logic voltage level of temporary PWM signal SBPWM for logic “1” a predetermined constant regardless of the logic voltage level of dimming signal SDIM.
Multiplexer 17b in FIG. 8, controlled by type identifier 12, has two inputs receiving DC signal SDC and dimming signal SDIM respectively. Multiplexer 17b has operational amplifier 24 and multiple-input, single-output switch 26. When type identifier 12 identifies dimming signal SDIM as of DC, operational amplifier 24, acting as a unity-gain buffer and a signal buffer, reproduces dimming signal SDIM and forwards it to multiple-input, single-output switch 26, which selects the output of operational amplifier 24 as DC signal SDDC and provides it to DC-to-PWM converter 16a. Operational amplifier 24 transfers dimming signal SDIM to multiple-input, single-output switch 26 if dimming signal SDIM is of DC. When type identifier 12 identifies dimming signal SDIM as of PWM, multi-input, single-output switch 26 in FIG. 6, as controlled by selection signal SSEL, selects DC signal SDC as DC signal SDDC and provides it to DC-to-PWM converter 16a while blocking dimming signal SDIM from reaching DC-to-PWM converter 16a. What multiplexer 17b outputs to DC-to-PWM converter 16a is always a DC signal, which is either dimming signal SDIM or DC signal SDC, where DC signal SDC represents dimming signal SDIM if dimming signal SDIM is of PWM.
In FIG. 8 exist DC signal path PTHDC and PWM signal path PTHPWM, based on which the DC signal SDDC is generated in response to dimming signal SDIM at input node DIM. DC signal path PTHDC goes from input node DIM, through operational amplifier 24 and multi-input, single-output switch 26, and to the non-inverting input of comparator 22. PWM signal path PTHPWM goes from input node DIM, through digital buffer 18, low-pass filter 15 and multi-input, and single-output switch 26, and to the non-inverting input of comparator 22. If type identifier 12 identifies dimming signal SDIM as of DC, type identifier 12 makes multi-input, and single-output switch 26 enable DC signal path PTHDC and interrupt PWM signal path PTHPWM. If type identifier 12 identifies dimming signal SDIM as of PWM, type identifier 12 makes multi-input, and single-output switch 26 enable PWM signal path PTHPWM and interrupt DC signal path PTHDC.
Apparently, both digital buffer 18 and low-pass filter 15 are located on PWM signal path PTHPWM, while operational amplifier 24 is located on DC signal path PTHDC.
DC-to-PWM converter 16a converts DC signal SDDC into PWM signal SCPWM. Shown in FIG. 8, DC-to-PWM converter 16a has signal generator 20 and comparator 22. Signal generator 20 provides the inverting input of comparator 22 saw-wave signal SSAW, which, like a clock, is periodically reset to its original starting voltage. Comparator 22 compares saw-wave signal SSAW with DC signal SDDC to generate PWM signal SCPWM, analogous to what is taught in FIG. 3. The frequency of PWM signal SCPWM is a constant determined by saw-wave signal SSAW, and has nothing to do with the frequency of dimming signal SDIM at input node DIM. Furthermore, the logic voltage level of PWM signal SCPWM for logic “1” or “0” could be conveniently customized to fit in the input requirement of LED driver 14a.
LED driver 14a in FIG. 8 controls power transistor MNDRV in response to PWM signal SCPWM, so as to control the current flowing through light-emitting device LT.
FIG. 9 shows dimming method 60c in use of dimming controller 10c in FIG. 8. Some steps of dimming method 60c are the same or similar with corresponding steps of dimming methods 60a and 60b, so they are not repeatedly detailed here since they are comprehensible in view of related disclosure in the previous paragraphs.
Step 72b, in response to selection signal SSEL that indicates dimming signal SDIM is a DC signal, makes multiplexer 17b enable DC signal path PTHDC to generate DC signal SDDC in response to dimming signal SDIM. Step 72b also interrupts PWM signal path PTHPWM, so multi-input, single-output switch 26 isolates DC signal SDDC from DC signal SDC.
Step 67 in FIG. 9 follows when type identifier 21 identifies dimming signal SDIM as of PWM. Digital buffer 18 reproduces the logic value of dimming signal SDIM to provide temporary PWM signal SBPWM, which has a predetermined logic voltage level corresponding to a certain logic value.
In FIG. 9, step 68b follows step 67 and low-pass filer 15 converts temporary PWM signal SBPWM into DC signal SDC.
Step 70c of FIG. 9 follows step 68b. Step 70c makes multiplexer 17b select DC signal SDC to be DC signal SDDC. In other words, DC signal path PTHDC is enabled to generate DC signal SDDC in response to dimming signal SDIM, and PWM signal path PTHPWM is interrupted.
In step 74, DC-to-PWM converter 16a converts DC signal SDDC into PWM signal SCPWM.
Step 76, performed by LED driver 14a, controls power transistor MNDRV to control the current flowing through light-emitting device LT.
Dimming controller 10c in FIG. 8 and dimming method 60c in FIG. 9 have advantages as follows. Regardless whether dimming signal SDIM is of PWM or of DC, dimming controller 10c could always generate corresponding PWM signal SCPWM, which has a constant frequency and a predetermined logic voltage level, to dim the light-emitting device LT properly.
Multi-input, single-output switch 26 in dimming controller 10a, 10b or 10c is used to select one of two dimming signals with a common signal type. In dimming controller 10a, multi-input, single-output switch 26 selects one of two PWM signals. In dimming controller 10b and 10c, multi-input, single-output switch 26 selects one of two DC signals. This invention is not limited to, however. Multi-input, single-output switch 26 in other embodiments of the invention could select one of two dimming signals with different signal types.
FIG. 10 demonstrates dimming controller 10d, which could be dimming controller 10 in FIG. 1 according to embodiments of the invention. Several devices or circuits in FIG. 10 have been disclosed or taught by dimming controller 10c in FIG. 8 and the relevant paragraphs, and their function and operation are not repeatedly detailed for brevity. Dimming controller 10d could have the same benefits or advantages with dimming controller 10c.
Please note that dimming controller 10c in FIG. 8 has low-pass filter 15 connected between multi-input, single-output switch 26 and digital buffer 18. Dimming controller 10d in FIG. 10, unlike dimming controller 10c, has low-pass filter 15 connected between multi-input, single-output switch 26 and comparator 22. In view of signal transmission, low-pass filter 15 in FIG. 8 provides signals to multi-input, single-output switch 26, while low-pass filter 15 in FIG. 10 receives signals from multi-input, single-output switch 26.
In FIG. 10, multiplexer 17b, which includes operational amplifier 24 and multi-input, single-output switch 26, selects one of dimming signal SDIM and temporary signal SBPWM, in response to selection signal SSEL output from type identifier 12. The selected one is outputted as output SDXX to low-pass filter 15 which accordingly generate DC signals SDDC.
As shown in FIG. 10, when type identifier 12 identifies dimming single SDIM as of DC, multiplexer 17b selects DC signal path PTHDC to generate DC signal SDC. Multi-input, single-output switch 26 selects the output from operational amplifier 24 to be output SDXX, which reproduces dimming single SDIM and is now a DC signal. Meanwhile, even though delays could occur due to signal propagation, low-pass filter 15 has no impact to the voltage level of dimming signal SDIM, and can provide DC signal SDDC that faithfully reproduces the voltage level of the dimming signal SDIM.
In the other hand, when type identifier 12 in FIG. 10 identifies dimming single SDIM as of PWM, multiplexer 17b selects PWM signal path PTHPWM to generate DC signal SDDC. Meanwhile, digital buffer 18 acts as a level shifter, and makes the logic voltage level of temporary PWM signal SBPWM for logic “1” a predetermined constant regardless of the logic voltage level of dimming signal SDIM. Multi-input, single-output switch 26 now selects temporary PWM signal SBPWM to be output SDXX, which is now a PWM signal. Low-pass filter 15 in response low-pass filters output SDXXto generate DC signal SDDC. In other words, low-pass filter 15 PWM-to-DC converts output SDXX or temporary PWM signal SBPWM into DC signal SDDC.
FIG. 11 shows dimming method 60d in use of dimming controller 10d in FIG. 10. Some steps of dimming method 60d are the same or similar with corresponding steps of dimming method 60c, so they are not repeatedly detailed here since they are comprehensible in view of related disclosure in the previous paragraphs.
Dimming method 60d, unlike dimming method 60c, have step 70d following step 67, where step 70 selects temporary PWM signal SBPWM to be output SDXX.
Dimming method 60d has step 68c followings both steps 72b and 70d. In step 68c, low-pass filter 15 low-pass filters output SDXX to generate DC signal SDCS.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art) . Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20190335556
