The present invention is related to radio transmitters, and more particularly to a diode ring structure for harmonic mixers.
In conventional radio systems, linear modulation is employed at the transmitter side to translate the signal frequency spectrum of an intermediate frequency (IF) signal to a higher frequency spectrum around a carrier frequency. The carrier frequency is higher than the frequency of the IF signal, and is better suited to propagate through a communication medium. This process, also known as heterodyning, can be accomplished by multiplying the signal, [1+x(t)]cos(ω1t), by a sinusoid, e.g., cos(ω2t), generated by a local oscillator (LO) as illustrated, for example, by the following equation: 2[1+x(t)]cos(ω1t)cos(ω2t)=x(t)cos(ω1+ω2)t+x(t)cos(ω1−ω2) t+2cos(ω2t)+
The multiplication, which is typically performed by a mixer, generates the sum and difference of frequencies of the signals. Hence, the multiplication translates the frequency of the signal to two new frequencies. The block diagram of
The output spectrum can be obtained with the use of a filter after the mixer or with an image rejection mixer through a process known as Single Side Band (SSB) generation. An image rejection mixer is typically composed of two common mixers connected through a hybrid that provide a proper phasing for image rejection. The SSB generation ideally should suppress all unwanted signals and transmit only the desired information. In real circuits, however, there is always a certain amount of leakage, requiring the use of a filter to maintain the level of unwanted signals within standards. It should be noted, however, that the better the suppression of the image rejection mixer, the easier it is to design the filter and the lower its cost.
Therefore, it is desirable to provide an image rejection mixer having the best suppression characteristics for the unwanted signals that can be obtained with a certain technology.
In an exemplary embodiment according to the present invention, a sub-harmonic mixer is provided. The sub-harmonic mixer includes an input for receiving a first signal having a first frequency and a second signal having a second frequency, an output for outputting a third signal having a third frequency, and at least one diode ring array, each having a plurality of diode rings arranged in parallel. At least one diode ring array receives the first signal and the second signal, generates a fourth signal having twice the second frequency, and multiplies the fourth signal to the first signal to generate the third signal.
When operating as an up-converter, for example, the first frequency may be an IF frequency, the second frequency may be an LO frequency, and the third frequency may be an RF frequency. When operating as a down-converter, for example, the first frequency may be an RF frequency, the second frequency may be an LO frequency, and the third frequency may be an IF frequency.
In another exemplary embodiment of the present invention, a transmitter including a sub-harmonic mixer and an oscillator is provided. The sub-harmonic mixer has at least one diode ring array, each having a plurality of diode rings arranged in parallel. The sub-harmonic mixer receives an intermediate frequency (IF) signal and translates the IF signal to a transmission signal having a transmission frequency. The oscillator generates a local oscillator (LO) frequency signal having an LO frequency. The sub-harmonic mixer receives the LO frequency signal, generates a signal having twice the LO frequency, and multiplies the signal having twice the LO frequency to the IF signal using said at least one diode ring array to generate the transmission signal.
In yet another exemplary embodiment of the present invention, a method of generating a transmission signal having a transmission frequency from an intermediate frequency (IF) signal is provided. A local oscillator (LO) frequency signal having an LO frequency is generated. A signal having twice the LO frequency is generated using a sub-harmonic mixer including at least one diode ring array, each having a plurality of diode rings arranged in parallel The signal having twice the LO frequency is multiplied to the IF signal using a sub-harmonic mixer to generate the transmission signal.
In still another exemplary embodiment of the present invention, a receiver includes a sub-harmonic mixer having at least one diode ring array, each having a plurality of diode rings arranged in parallel. The sub-harmonic mixer receives a transmission signal having a transmission frequency and translates the transmission signal to an intermediate frequency (IF) signal. An oscillator generates a local oscillator (LO) frequency signal having an LO frequency. The sub-harmonic mixer receives the LO frequency signal, generates a signal having twice the LO frequency, and applies the signal having twice the LO frequency to the transmission signal using said at least one diode ring array to generate the IF signal.
These and other aspects of the invention may be understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, wherein:
In exemplary embodiments of the present invention, an image rejection mixer including sub-harmonic mixers (i.e., a sub-harmonic image rejection mixer) greatly reduces the level of LO leakage, compared to a fundamental image rejection mixer. One or more sub-harmonic mixers, each may simply be referred to as a “mixer” or a “harmonic mixer” hereinafter, are implemented on Monolithic Microwave Integrated Circuit (MMIC), and are based on the switching function of a ring of “anti-parallel” diodes. The sub-harmonic image rejection mixer may also be referred to as a “mixer” or a “sub-harmonic mixer” herein. The term anti-parallel as used herein refers to the fact that the two diodes in the diode ring are in a parallel relationship, but are oriented in opposite directions of each other.
The sub-harmonic mixer includes a number of parallel diode rings (i.e., a diode ring array), each including two diodes that are electrically connected in anti-parallel. The sub-harmonic image rejection mixer includes two such diode ring arrays. The diode rings are pumped at a local oscillation (LO) frequency. The sub-harmonic mixer generates a signal having 2×LO frequency, and multiplies it to an intermediate frequency (IF) signal to generate the RF (i.e., transmission) signal “centered around” (i.e., “having”) the RF frequency. The RF frequency is a sum of or a difference between the 2×LO frequency and the intermediate frequency. The RF frequency may be approximately equal to 2×LO frequency when the LO frequency is significantly higher than the IF.
This topology generates a substantially symmetrical waveform with very low content of even harmonics, in particular of 2×LO frequency. The sub-harmonic mixer in the exemplary embodiments of the present invention demonstrates both high isolation and good linearity.
The RF signal (i.e., transmission signal) having the RF frequency is the output signal that is obtained by applying the LO frequency signal to the sub-harmonic mixer. Since the diode is a non-linear element, it generates internally the frequency component 2×LO, which is multiplied with the IF signal and is the one generating the transmission signal. The fundamental LO signal is substantially rejected in the sub-harmonic mixer of the present invention.
The sub-harmonic mixer or the sub-harmonic image rejection mixer, for example, may be applied in Ka-band and/or higher frequency bands, for example, in 36-44 Giga Hertz (GHz) range. Since the LO frequency is approximately one half of the RF frequency, a high output power level of the LO amplifier (i.e., LO driver amplifier) is only required at lower frequencies, which may lead to the reduced cost for the transmitter and receiver.
The LO frequency signal is amplified by an LO amplifier 108. The LO amplifier 108 is implemented on an MMIC 106 together with a sub-harmonic mixer 110. In other embodiments, the LO amplifier may be implemented on a separate chip from the sub-harmonic mixer 110. In still other embodiments, the LO amplifier may be not used. The IF signals, IF1 and IF2, are mixed in the sub-harmonic mixer 110 with the amplified LO frequency signal having a frequency ω2/2. In more detail, the sub-harmonic mixer 110 generates a signal having twice the frequency of the LO frequency signal (i.e., 2×LO frequency signal), and multiplies it to the IF1 and IF2 signals to generate the mixed signal. The mixed signal may then be filtered by a filter 114 to remove other components from the mixed signal to generate the RF signal having frequency ω1+ω2, which is transmitted by an antenna 116. In other embodiments, the filter 114 may also be implemented on the MMIC 106.
The sub-harmonic mixer 110 includes a diode ring array 112, which receives the IF1 and IF2 signals and the LO signal. The mixer 110 generates a transmission signal having the frequency of the RF signal. In practice, the sub-harmonic mixer 110 generates two signals, one having the frequency of LO frequency+IF and another having the frequency of 2×LO frequency+IF, but only the latter is transmitted as the RF signal, since the former is substantially rejected internally to the diode ring array 112. The sub-harmonic mixer 110 can also select the other sideband, i.e., (2×LO frequency−IF), for transmission by proper selection of ports on the IF 90° hybrid.
The sub-harmonic mixer 110 (and the MMIC 106), for example, may be fabricated using diodes made from field emission transistor (FET) based technologies, and may be capable of reducing the level of 2×LO leakage far below the level obtained by conventional structures while providing high linearity. By way of example, the MMIC 106 may be fabricated using 0.25 μm gate length Pseudomorphic High Electron Mobility Transistor (PHEMT) technology available from Fujitsu.
It can be seen in
It can be seen in
The diode ring array 112 of
The diode ring array 130 as shown in
An RF port 131 is on one side of the diode rings 135 and an LO+IF port 132 is on the other side. A diplexer can be used to separate the LO from IF. A filter 133 is disposed between the diode rings 135 and the port 131, and a filter 134 is disposed between the diode rings and the port 132. While the diode rings are connected in parallel with respect to one another, since they are electrically connected between ports 131 and 132, thereby forming a signal path between input and output ports, the diode ring array 130 may be referred to as “series-connected,” which means that all diode rings are in series with the signal flowing in the circuit. In other words, for the series-connected diode ring array 130, all diode rings are connected on one side to either an RF or LO line and on the other side either to the LO or RF line.
Ideally, all harmonics of the fundamental LO frequency should be generated within the ring. If the ring is symmetrical, all even harmonics should cancel in the ring, and only odd harmonics should be present outside of it at the RF port. The isolation of the second harmonic local oscillator frequency, which falls within the wanted RF bandwidth, at the RF port of the sub-harmonic mixer should ideally be infinite.
In practice, however, every diode can be viewed as a combination of the current source and the junction capacitance, as shown in
The current source 148 is one of the elements used to effect the switching function. To make an ideal switch, on-resistance should be a short circuit during 50% of the duty cycle and open circuit for the complementary cycle. Unfortunately, these conditions are only approximately met by real diodes. The on-resistance is different from zero, degrading conversion loss, and the reverse leakage current is different from open circuit, degrading isolation. Additionally, the junction capacitance 150 in parallel contributes to further degradation of switching performance.
In the realization of planar diodes in FET or HEMT technologies, there are many unavoidable parasitics and it is difficult to build perfectly symmetrical diodes. Those are responsible for a non-ideal switching function of the diodes. As a result, leakage power at the second harmonic of the LO is generated. The list of parasitics that influence the operation of a diode as ideal switch, is manifold: it includes the junction capacitance and the reverse leakage current; the unsymmetrical layout of diodes in FET or HEMT technologies and the difference between anode and cathode connections. They all contribute to an imbalance in the diode ring.
Further, in planar IC technology, the layout of two diodes on a ring configuration is not fully symmetrical. Therefore, the circuit impedance is different depending on whether LO is connected to anode or cathode. Simulation for a diode ring considering the equivalent circuit of
A common way to increase the isolation is to reduce the diode size. The parasitic capacitance and reverse leakage currents become smaller and the differences in anode and cathode asymmetries are reduced. Now the pumped diode ring becomes comparable to the ideal switch function. However, a reduced linearity of the sub-harmonic mixer also results from the diode size reduction.
As described above, in exemplary embodiments of the present invention, instead of having one diode ring with large size diodes, several rings are connected in parallel. Due to the parallel combination of the diode rings, the effective total diode size is increased. As a consequence, the power performance is recovered and good linearity can be achieved. The amount of second harmonic LO power, that still leaks from each individual ring, adds up at the output, but it is considerably lower than the one generated by a single ring of equivalent diode size.
For comparison, when only one diode ring (R=1) with long width is used (i.e., N=3 fingers and width of W=33.33 μm), the total effective size is also: Weff=R×(2>N×W)=1×2×3×33.33 μm≅200 μm. The large individual diode has a larger junction capacitance and a larger reverse leakage current than the single finger diode in exemplary embodiments of the present invention. Besides, the layout connections of the anode and cathode may also be different. This results in a high second harmonic leakage current. A second harmonic LO leakage level of a sub-harmonic image rejection mixer built with this diode ring is shown as a plot 160 in
A sub-harmonic image rejection mixer built with the diode ring array 112 has a total effective diode size which is similar to the mixer built with the diode ring having larger diodes, namely, 200 μm. The level of the second harmonic LO leakage is shown in
Therefore, it can be seen in
An IF hybrid 203 receives the IF signal having frequency ω1, and generates two quadrature signals, IF1 and IF2, having the frequency ω1 that are offset in phase by 90 degrees of each other. The IF1 and IF2 signals are provided to the diode ring arrays 211 and 212, respectively.
The LO frequency signal having the frequency ω2/2 is amplified by the LO amplifier 208, and then divided by a power divider 209, which may include, for example, a Wilkinson power divider having a reduced size. In other embodiments, the LO amplifier may be implemented on a separate chip. In still other embodiments, the LO amplifier may be not used. The power divider 209 may also include any other suitable divider known to those skilled in the art. The divided signals having reduced power are provided to diode ring arrays 211 and 212, respectively. The outputs of the diode ring arrays 211 and 212 are combined, for example, by a 90° RF hybrid 213 in quadrature to generate an RF signal having frequency ω1+ω2. The 90° RF hybrid 213, for example, may include a Lange coupler or any suitable 90° RF hybrid known to those skilled in the art.
The diode ring array 211 or 212 of
In actual implementation, each of the four diode rings 220 in the diode ring arrays 211 and 212 is connected to a via hole for (e.g., optimum) RF, LO and IF return. On the other side the diode rings are connected to a single point, i.e., the connection point P. This arrangement allows equal sharing in magnitude and phase of applied voltage by each diode ring. In the individual ring, each diode has a gate width of 25 μm. Calculating the total effective size of the diodes, those four rings with two diodes each represent a diode ring with 200 μm gate width. During the implementation of the sub-harmonic image rejection mixer 210, spiral inductors and Metal-Insulator-Metal (MIM) capacitors may be used in the matching networks.
The LO amplifier 208, for example, may have two stages with device sizes, respectively, of 4×50 μm2 and 6×50 μM2, and may operate with a single supply voltage. To achieve the required bandwidth, distributed line elements in combination with MIM capacitors may be used. The inter-stage matching may conjugate match both stages for maximum gain. The output network may be optimized to deliver high output power. The selected load impedance can be extracted from load pull measurements of the transistor.
The local oscillator 204 and/or the LO amplifier 208 should present low second harmonic to minimize 2×LO feedthrough. In one specific implementation, the obtained level is close to −40 dBc compared to the fundamental power. This level may be further reduced by a tuned Wilkinson power combiner, and/or by the matching filter 229 described in reference to
The measured up-converter results confirm the results obtained from down-converter operation.
The LO generator operating from 18 to 22 GHz, which corresponds to a 2×LO frequency of 36 to 44 GHz, showed very low second harmonic at the output power level of +22 dBm. The 2×LO power level 252 measured at the RF bonding pad, i.e., at the mixer output, of the mixer with a parallel-connected diode ring array is depicted in
The result for the mixer with a series-connected diode ring array represented in
The measured input 1 dB compression points for up- and down-converter operation is shown in
In the receiver 300, the mixer 310 is used for down-conversion of an RF signal to an IF signal. An antenna 316 receives the RF signal having the transmission frequency ω1+ω2, which is subsequently filtered by a filter 314. The filtered RF signal is provided to an RF hybrid 313, which generates quadrature signals, RF1 and RF2, that are at 90 degrees offset in phase of each other, and each having the frequency ω1+ω2. An LO 304 generates an LO frequency signal having the frequency ω2/2. The LO frequency signal is amplified by an LO amplifier 308. The LO amplifier may be implemented on a separate chip or may be not used in other embodiments.
The power divider 309 divides the LO frequency signal and provides the divided LO frequency signals to the diode ring arrays 311 and 312, respectively. The diode ring arrays 311 and 312 also receive RF1 and RF2 signals, respectively. The image rejection mixer 310 generates IF1 and IF2 signals having frequency ω1, and delivers them to an off-chip 90° IF hybrid 303 to generate an IF signal. The IF signal is then processed by the IF processing circuitry 316.
It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential character hereof. The present description is therefore considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the appended claims, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced therein.