Patent Grant
8570005
Aspects of this disclosure relate to distributed power systems, particularly a photovoltaic power harvesting system and, more particularly to a direct current link circuit connected between a photovoltaic array and a 3-phase inverter circuit.
In a conventional photovoltaic power harvesting system configured to feed a single phase or a three phase alternating current (AC) power grid, dual (positive and negative) direct current (DC) power may be generated first from solar panels. The three phase inverter powered by the dual (positive and negative) DC power produces three phase AC power at the output of the three phase inverter. Conventionally, sufficiently high DC voltage may be provided to the input of the three phase inverter by connecting solar panels in series. However, in order to increase overall power conversion efficiency, the sum of positive and negative DC rails required by the inverter may be over 600 volts.
In North America, an input of voltage over 600 volts may create an issue with safety agency approval under regulation UL1741. An approach to avoid the safety issue may include inputting less than 600 volts to a boost circuit or transformer-isolated circuit to generate dual DC rails internally for the inverter input. The additional boost or transformer-isolated circuit increases cost and complexity especially since the additional power converter module generally requires dedicated control and protection features. Additionally, the boost or transformer-isolated circuit may also generate electromagnetic interference (EMI) and may cause reduction in overall efficiency of conversion of DC power to three phase AC power.
Thus there is need for and it would be advantageous to have a DC link circuit with a low voltage input, which does not cause significant reduction in overall efficiency of conversion of DC power to three phase AC power and which provides a sufficiently high DC input voltage to the AC inverter to generate an AC output of the inverter of required magnitude.
Embodiments include a method for converting power from a floating source of DC power to a dual direct current (DC) output. The floating source of DC power includes a positive input terminal and a negative input terminal. The dual DC output includes a positive output terminal, a negative output terminal and a ground terminal. The method includes charging a charge storage device connected in parallel to the positive input terminal and the negative input terminal. The charging may be supplied from the floating source of DC power. The discharging of the charge storage device may be performed by first switching the negative input terminal through a resonant circuit to the negative output terminal during a first half of the period of the resonant circuit, and second, switching the positive input terminal through the resonant circuit to the positive output terminal during a second half of the period of the resonant circuit. During the first switching, a negative return current path may be provided from the negative output terminal to the negative input terminal. During the second switching, a positive current path may be provided from the positive input terminal to the positive output terminal. During the discharging, a negative return current path may be provided from the negative output terminal to the negative input terminal. The negative return current path allows only negative current to flow from the negative input terminal to the negative output voltage terminal. During the discharging, current flow may be blocked from the positive output terminal to the positive input terminal. The resonant circuit may include an inductor connected in series with a capacitor. A positive current path may be provided from the positive input terminal to the positive output terminal. The positive current path allows only positive current to flow from the positive input terminal to the positive output voltage terminal.
Other embodiments include a device for converting power from a floating source of DC power to a dual direct current (DC) output. The device includes a positive input terminal and a negative input terminal connectible to the floating source of DC power, a positive output terminal, a negative output terminal and a ground terminal connectible to the dual DC output. The positive output terminal, the negative output terminal and the ground terminal may feed an inverter. The inverter may be either a two level inverter or a three level inverter. A charge storage device may be connected in parallel to the positive input terminal and the negative input terminal. The charge storage device may be charged from the positive input terminal and the negative input terminal. A resonant circuit may be also connected between the charge storage device and the dual DC output. The resonant circuit may include an inductor connected in series with a capacitor. The charge storage device may discharge through the resonant circuit by switching through to either the negative output terminal or the positive output terminal. The charge storage device may be either a capacitor or a battery. The device may include a positive current path from the positive input terminal of the floating source of direct current DC power to the positive output terminal. The positive current path may include a diode with a cathode connected to the positive output terminal and an anode connected to the positive input terminal. The device may further include a negative return current path from the negative input terminal of the floating source of direct current DC power to the negative output terminal. The negative return current path may include a second diode including an anode connected to the negative output terminal and a cathode connected to the negative input terminal.
Other embodiments may include a device for converting power from a floating source of DC power to a dual direct current (DC) output, the device includes; a positive input terminal and a negative input terminal connectible to the floating source of DC power, a positive output terminal, a negative output terminal and a ground terminal connectible to the dual DC output. A charge storage device may be connected in parallel to the positive input terminal and the negative input terminal. The charge storage device may be charged from the positive input terminal and the negative input terminal. A resonant circuit may be also connected between the charge storage device and the dual DC output. The charge storage device may discharge through the resonant circuit by switching the negative input terminal to the resonant circuit. A switch may be connected between the positive input terminal and the resonant circuit, wherein the switch when closed discharges the charge storage device through the resonant circuit to the negative output terminal. The switch may include an integral diode with a cathode connected to the negative output terminal and an anode connected to the resonant circuit. When the switch is open, the charge storage device may be charged from the positive input terminal. The charge storage device may be charged from the positive input terminal and the negative input terminal and discharged through the resonant circuit by switching the switch. A second switch connected between the negative input terminal and the resonant circuit. The second switch when closed discharges the charge storage device through the resonant circuit to the positive output terminal. When the second switch is open, the charge storage device may be charged from the positive input terminal. The second switch may include a second integral diode with an anode connected to the negative input terminal and a cathode connected to the resonant circuit. The charge storage device may be charged from the positive input terminal and a negative input terminal and discharged through the resonant circuit by switching the second switch. The switch and the second switch may include a silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), mechanically operated single pole double pole switch (SPDT), SPDT electrical relay, SPDT reed relay, SPDT solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC) or a triode for alternating current (TRIAC).
Further embodiments include a device for converting power from a floating source of DC power to a dual direct current (DC) output, the device includes; a positive input terminal and a negative input terminal connectible to the floating source of DC power, a positive output terminal, a negative output terminal and a ground terminal connectible to the dual DC output. A charge storage device may be connected in parallel to the positive input terminal and the negative input terminal. The charge storage device may be charged from the positive input terminal and the negative input terminal. The charge storage device discharges through the resonant circuit by switching the negative input terminal to the resonant circuit. The resonant circuit may be connected between the charge storage device and the dual DC output. The resonant circuit may include a first insulated gate bipolar transistor (IGBT) with a first collector attached to the positive input terminal, a first emitter, a first diode including a first anode and a first cathode. The first cathode may be connected to the first collector and the first anode may be connected to the first emitter. A first base may be attached to a first drive circuit. A second IGBT with a second collector may be attached to the first emitter to provide a third node. A second emitter may be connected to the negative input terminal. A second diode with a second cathode may be connected to the second collector and a second anode may be connected to the second emitter. A second base may be attached to a second drive circuit. A DC output may include positive terminal. A second capacitor may be connected between the DC output positive terminal and electrical ground. A DC output may include negative terminal. A third capacitor may be connected between the DC output negative terminal and electrical ground and an inductor connected between the third node and electrical ground.
Certain embodiments are illustrated by way of example, and not by way of limitation, in the accompanying figures, wherein like reference numerals refer to the like elements throughout:
Reference will now be made in detail to features of the present invention, examples of which are illustrated in the accompanying figures. The features are described below to explain the present invention by referring to the figures.
Before explaining features of the invention in detail, it is to be understood that the invention is not limited in its application to the details of design and the arrangement of the components set forth in the following description or illustrated in the figures. The invention is capable of other features or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. For example, the definite articles “a” and “an” used herein, such as in “a switch” and “a DC output” have the meaning of “one or more,” e.g., “one or more switches” and “one or more DC outputs.”
It should be noted, that although the discussion herein relates primarily to photovoltaic systems, the present invention may, by non-limiting example, alternatively be configured using other distributed power systems including (but not limited to) wind turbines, hydro turbines, fuel cells, storage systems such as battery, super-conducting flywheel, and capacitors, and mechanical devices including conventional and variable speed diesel engines, Stirling engines, gas turbines, and micro-turbines.
The term “switch” as used herein refers to any of: silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), mechanically operated single pole double pole switch (SPDT), SPDT electrical relay, SPDT reed relay, SPDT solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), and triode for alternating current (TRIAC).
The term “positive current” as used herein refers to a direction of flow of a current from a higher potential point in a circuit to a lower potential difference point in the circuit. The term “negative current” as used herein refers to a flow of return current from a negative DC output to a negative input terminal.
The term “zero current switching” (or “ZCS”) as used herein is when the current through a switch is reduced to substantially zero amperes prior to when the switch is being turned either on or off.
The term “power converter” as used herein applies to DC-to-DC converters, AC-to-DC converters, DC-to-AC inverters, buck converters, boost converters, buck-boost converters, full-bridge converters and half-bridge converters or any other type of electrical power conversion/inversion known in the art.
The terms “power grid” and “mains grid” are used herein interchangeably and refer to a source of alternating current (AC) power provided by a power supply company and/or a sink of AC power provided from a distributed power system.
The term “period of a resonant circuit” refers to a time period of a substantially periodic waveform produced by the resonant circuit. The time period is equal to the inverse of the resonant frequency of the resonant circuit.
The term “low input voltage” is used herein refers to a floating (i.e., not referenced to a ground potential) DC voltage input across two terminals of less than 600 Volts or other voltage as specified by a safety regulation.
The term “dual DC” input or output refers to positive and negative terminals that may referenced to a third terminal, such as ground potential, electrical ground or a neutral of an alternating current (AC) supply which may be connected to electrical ground at some point.
The term “two level inverter” as used herein, may refer to its output. The AC phase output of the two level inverter has two voltage levels with respect to a negative terminal. The negative terminal is common to the AC phase output and the direct current (DC) input to the two level inverter. The alternating current (AC) phase output of the two level inverter may be a single phase output a two phase output or a three phase output. Therefore, the single phase output has two voltage levels with respect to the negative terminal. The two phase output has two voltage levels with respect to the negative terminal for each of the two phases. The three phase output has two voltage levels with respect to the negative terminal for each of the three phases.
Similarly, the term “three level inverter” as used herein may refer to an alternating current (AC) phase output of the three level inverter. The AC phase output has three voltage levels with respect to a negative terminal. The negative terminal is common to the AC phase output and the direct current (DC) input to the three level inverter. The alternating current (AC) phase output of the three level inverter may be a single phase output a two phase output or a three phase output. Therefore, the single phase output has three voltage levels with respect to the negative terminal. The two phase output has three voltage levels with respect to the negative terminal for each of the two phases. The three phase output has three voltage levels with respect to the negative terminal for each of the three phases.
The three level inverter compared with the two level inverter may have a cleaner AC output waveform, may use smaller size magnetic components and may have lower losses in power switches, since more efficient lower voltage devices may be used. Three level inverter circuits may have dual (positive and negative) direct current (DC) inputs.
Reference is made to
Reference is now made to
Reference is now made to
IGBT1 and IGBT2 may be gated alternately such that when IGBT1 is turned on, IGBT2 is off and vice versa by respective drive circuits G1 and G2. IGBT1 and IGBT2 may be gated alternately with less than a 50% duty cycle so as to avoid cross-conduction between IGBT1 and IGBT2 (i.e. to avoid IGBT1 and IGBT2 being on at the same time). A floating voltage provided from array 111 substantially provides a positive voltage on node V+ and a negative voltage on node V− with respect to the ground. The voltages on node V+ and node V− may be substantially equal to the magnitude of the floating voltage. Step 303, which charges capacitor C1 may continue during alternate gating of switches IGBT1 and IGBT2.
When switch IGBT1 is turned on (and IGBT2 turned off), current flows from array 111 and a discharge current flows (step 305a) from storage capacitor C1 through collector and emitter of IGBT1, through inductor L1, into capacitor C3 and the input load of inverter 103a between ground (node D) and node V−. Inductor L1 and capacitor C3 form a series resonant circuit. The diode across IGBT1 is reverse biased with respect to the voltage at positive input terminal A. The input voltage to inverter 103a with respect to ground (node D) and node V− may be derived across capacitor C3. The resonant frequency of inductor L1 and capacitor C3 is given by Eq. 1 and the corresponding resonant periodic time T given in Eq. 2.
fo=½π(L1×C3)½ Eq.1
T=1/fo Eq.2
When IGBT1 initially turns on, there may be both zero current through inductor L1 and through the collector and emitter of IGBT1. After IGBT1 initially turns on, the current through L1 and the current through the collector and emitter of IGBT1 may increase and then fall sinusoidally. When IGBT1 turns off (the on period of the switch corresponds to half of the resonant periodic time T) there may be close to zero current through inductor L1 and through the collector and emitter of IGBT1.
A negative current path between node V− and negative input terminal B may be completed through diode CR2 corresponding to half of the resonant periodic time T.
Step 303 continues as capacitor C1 is still being charged by the floating DC voltage of array 111 by virtue of capacitor C1 being directly connected across array 111 at positive and negative input terminals A and B. When IGBT2 is turned on (and IGBT is turned off), current flows from array 111 and a discharge current (step 305b) from storage capacitor C1 through diode CR1 through the input load of inverter 103a between ground (node D) and node V+, through C2, through inductor L1 and through the collector and emitter of IGBT2. Inductor L1 and capacitor C2 form a series resonant circuit. The diode across IGBT2 may be reverse biased with respect to the voltage at negative input terminal B. The input voltage to inverter 103a with respect to ground (node D) and node V+ is derived across capacitor C2. Capacitor C2 may have the same value as capacitor C3; therefore, the resonant frequency of inductor L1 and capacitor C2 and corresponding resonant periodic time T may be substantially the same. When IGBT2 initially turns on, there may be both zero current through inductor L1 and through the collector and emitter of IGBT2 and may be substantially zero power loss at turn on of IGBT2. After IGBT2 initially turns on, the current through L1 and the current through the collector and emitter of IGBT2 may increase and then fall sinusoidally. When IGBT2 turns off (the on period of the switch corresponds to half of the resonant periodic time T) there may be close to zero current in inductor L1 and close to zero current through the collector and emitter of IGBT2. Therefore, there may be zero power loss at turn off of IGBT2. A positive current path between node V+ and positive input terminal A is completed through diode CR1 corresponding to half of the resonant periodic time T. Zero current switching (ZCS) may, therefore, be provided for both turn on and turn off of both switches IGBT1 and IGBT2.
Zero current switching (ZCS) may permit the use and implementation of slower switching speed transistors for IGBT1 and IGBT2, which may have a lower voltage drop between collector and emitter. Thus, both switching losses and conduction losses may be reduced. Similarly, slower integrated diodes of IGBT1 and IGBT2 with lower voltage drop may be used. Slower diodes CR1 and CR2 may also be used. Resonant current shape through the collector and emitter of IGBT1 and IGBT2 may also reduce the turn-on losses in the diodes CR1 and CR2, as well as generated electromagnetic interference (EMI).
Although selected features of the present invention have been shown and described, it is to be understood the present invention is not limited to the described features. Instead, it is to be appreciated that changes may be made to these features without departing from the principles and spirit of the invention, the scope of which is defined by the claims and the equivalents thereof.
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| Number | Date | Country | |
|---|---|---|---|
| 20130063119 A1 | Mar 2013 | US |
