Examples described herein refer to synthetic signal generation, and more particularly, to synthetic frequency signal generation.
Multi-standard radios, such as cell phones and other electronic devices, require multiple signals having different frequencies to be able to transmit and receive information from different frequency bands. Due to carrier aggregation in cellular communication technologies, newer radio will be capable of operating multiple radios simultaneously. Present topologies have an individual synthesizer associated with each different frequency signal.
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
Multi-standard radios, such as cell phones and other electronic devices, require multiple signals having different frequencies to be able to transmit and receive information from different frequency bands. Due to carrier aggregation in cellular communication technologies, newer mobile devices will be capable of operating multiple radios simultaneously. Present topologies have a separate oscillator and synthesizer associated with each different frequency signal. Current multi-radio architectures pressure the devices to be larger to accommodate the additional oscillators. The additional oscillators also use additional power that can substantially reduce the time between recharging of the energy storage device of mobile devices without making accommodations for a larger energy storage device.
Recent developments in standards and technology have introduced the concept of carrier aggregation and amplifiers integrated with the transmitters or transceivers. These technological improvements have come with costs. For example, the oscillator in each radio PLL of current designs can experience “pulling” from the high power modulated power amplifier outputs. “Pulling” from the power amplifier to the local oscillator (e.g., re-modulation) can result in degraded modulation quality and spectral performance. The pulling problem can be exacerbated with multi-input/multi-output (MIMO) transmitters where the multiple independently modulated power amplifiers at the same frequency can “pull” the transmitter modulation PLLs. The oscillator in the PLLs for each MIMO or carrier aggregation branch can pull one another as well.
The present inventors have recognized a synthetic frequency synthesis architecture that allows multiple frequency generation using a central frequency synthesizer such as a single central phase-locked loop (PLL), for example. The architecture allows selection of a central PLL frequency to be at a power efficient frequency. Frequencies for each radio of the device can be generated with a power efficient direct digital frequency synthesizer using the output of the central PLL. The direct digital frequency synthesizers can use time and voltage information to reduce phase noise, improve performance, and decouple the traditional mechanism that allows the power amplifier to “pull” the local oscillator. An unexpected development of solving the “pulling” problem, the inventors have also recognized that a central PLL architecture that exploits the digital phase shifting capabilities of a digital-to-time converter (DTC) can significantly reduce circuit real estate in transmitter/receiver radios and more so in MIMO devices having multiple transmitters, multiple receivers, or combinations of multiple transmitters and multiple receivers.
The receiver 503 can include an amplifier 511, demodulator 544, a receiver DTC 545, a analog-to-digital converter (ADC) 546 and a processor 547, such as a receiver DSP. In certain examples, an antenna coupled to the receiver 503 can receive a wireless signal. The amplifier 511 can amplify the wireless signal; or certain portions of the wireless signal. The demodulator 544 can extract information from the wireless signal using a frequency provided by the receiver DTC 545. The ADC 546 can convert the information from an analog form to digital information for further processing by the processor 547. The processor 547 can provide at least a portion of the information to a host processor such as the baseband processor. In certain examples, the receiver DTC 545 uses the central frequency information generated by the central frequency synthesizer 515 to provide the demodulation frequency for the demodulator 544. In certain examples, pulling effects of the power amplifier 510 on the central frequency synthesizer 515 are significantly reduced or eliminated because the power amplifier 510 is prevented from coupling to the digitally implemented DTCs 543, 545 and there is no inductive coil as can be found with other architectures. In certain examples, the transmit DTC 543 and the receive DTC 545 can be employed to provide a frequency shift for generating transmit and receive frequencies. Exploiting this capability of the DTC allows transmission and reception frequencies to be different from the frequency of the central frequency synthesizer 515. Furthermore, in addition to eliminating a mechanism for allowing “pulling” of a transmitter or receiver local oscillator, the example architecture can unexpectedly provide real estate savings over traditional transceivers. Traditional transceivers typically have a local oscillator for each transmitter and receiver. Such oscillators can take up significant room on their own and then may require addition room to provide adequate separation between the oscillators or other components that can influence the frequency of the oscillators. The digital nature of the example architecture and the sharing of a central frequency synthesizer can eliminate the large components (e.g. coils) of the traditional local oscillator and can allow transmitter and receiver phase modulation to be done in a small, low-noise, digital environment.
In certain examples, a central synthesizer architecture can provide the opportunity to optimize the frequency of the central synthesizer. For example, the central synthesizer frequency can be selected to minimize cross talk between different device systems implemented or operated simultaneously in a mobile phone. In certain examples, the example central frequency synthesizer architecture can allow power scaling based on performance requirements of a certain RF mode. For example, current allocation and resolution, for example of one or more DTCs, can be adjusted depending on the operating mode of one or more of the radios of a mobile device. More specifically, for example, current consumption and DTC resolution can be decreased if a MIMO device is operating in a Bluetooth-only mode.
Emerging radio standards or protocols for connectivity (e.g., 802.11ac) and cellular (e.g., LTE-Rel10 and beyond) can incorporate contiguous and non-contiguous channel bonding/carrier aggregation features to support wide effective channel bandwidths while maintaining backward compatibility with legacy networks and existing spectrum allocation. This incorporation can allow peak data rates on the order of 100 Mbps-5 Gbps, and higher, to be supported on the up-links and down-links to mobile devices. In certain examples, architecture according to the present subject matter can allow mobile devices to also support transmit (TX) multi-input, multi-output (MIMO) capabilities to further improve channel capacity in these standards.
Digital polar transmitters are a promising approach for radio implementations on low-cost SoC CMOS because they can offer the potential for higher efficiency, minimize the required number of area-intensive passives, and port easily to new process nodes. PLL based phase modulators are typically used to generate the desired TX signals but suffer limitations when used for wider bandwidth (e.g., >20 MHz.) signals. Carrier aggregation can simultaneously generate transmit signals at non-harmonically related channel frequencies. Since, the spectrum allocation for cellular services varies by geography, a “world-phone” may need to generate transmit signals in many different bands, even if they do not need to operate simultaneously. Generating these modulated transmit signals in multiple independent PLLs, one for each carrier frequency, can result in significant area and power penalties. With the integration of power amplifier (PA) on the same die as the RF transceiver, the oscillator in each PLL can experience “pulling” from the high power modulated PA outputs. PA LO pulling (re-modulation) can result in degraded modulation quality and spectral performance. This problem can be exacerbated with TX-MIMO, where the multiple independently modulated PAs at the same frequency can pull the TX modulation PLLs. The oscillators in the PLLs for each MIMO or carrier aggregation branch can pull one another as well.
Existing or proposed schemes to alleviate pulling by shifting the oscillator frequency from the power amplifier output, such as dividing-and-mixing or harmonic division, can require area intensive passive filters such as inductive-capacitive (LC) filters. Such schemes may not be immune to harmonic pulling and do not scale well as the number of carrier frequencies increase. All digital local oscillator schemes can separate the power amplifier output from the local oscillator frequency without including passive filters but still consume substantial chip area and power.
A conventional solution for carrier aggregation and MIMO is to generate multiple transmission signals using multiple phased-locked loops, one for each frequency band that is supported whether the bands are used concurrently or not. Such solutions use significant circuit area and power and are susceptible to pulling, sometimes referred to as re-modulation, from the multiple local oscillator signals and harmonics thereof.
The MIMO stack 930 and the carrier aggregation section 931 can include multiple transmitters 933n. In certain examples, each transmitter 933n can be a digital polar transmitter including a power amplifier 934n, a DTC 935n, and a summing junction 936n. The summing junction 936n can receive phase modulation information (φn) and a phase ramp (ψn). The DTC 935n can provide a phase modulated signal having a frequency different from a signal received from a local oscillator (LO) using the phase modulation information (φn) and the phase ramp (ψn). In certain example, the power amplifier 934n can add amplitude information (ρn) to the envelope of the phase modulated signal of the DTC 935n to provide a radio frequency signal RFn to drive one or more antennas
In certain examples, a MIMO stack 930 can provide multiple modulated signals using a common frequency. As illustrated, a first DTC 9351 and a second DTC 9352 of the MIMO stack 930 can receive the same phase ramp (ψ1) but different phase modulation information (φ1, φ2). Each DTC 9351, 9352 can provide a phase modulated signal to a respective power amplifier 9341, 9342. Each power amplifier 9341, 9342 can add amplitude information (ρ1, ρ2) to the respective phase modulated signal and can provide a radio frequency drive signal (RF1, RF2) for an antenna.
In certain examples, a carrier aggregation section 931 can include three transmitters 9333, 9334, 9335. Each DTC 9353, 9354, 9355 can receive different phase modulation information (φ3, φ4, φ5) and different phase ramp information (ψ3, ψ4, ψ5) to produce three different phase modulated signal, each having a different frequency offset from the frequency of the local oscillator (LO). In addition, each power amplifier 9343, 9344, 9345 of each of the carrier aggregation section transmitters 9333, 9334, 9335 can receive different amplitude information (ρ3, ρ4, ρ5) for providing a radio frequency signal (RF3, RF4, RF5) for driving an antenna.
In certain examples, the open loop DTCs 935n can receive a phase ramp (ψa) to offset the output frequency from the frequency of the local oscillator (LO) and thereby absorb the function of a conventional fractional multiplier/divider. The range of frequency fractionalities synthesized using a DTC can be set by the resolution of the DTC, and the output frequency range of the DTC can be determined by the maximum instantaneous frequency jump the DTC can handle. In certain examples, additional integer frequency dividers can expand the flexibility of the architecture to cover a wide range of bands without being susceptible to frequency pulling. It is understood that the illustrated example can include additional transmitters as well as corresponding receivers, as is discussed above with respect to
In Example 1, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency. In certain examples, the second frequency can be different from the first frequency
In Example 2, the first transmitter of Example 1 optionally is configured to process and transmit first information according to a first communication protocol, and the first receiver of Example 1 optionally is configured to receive and process second information according to the first communication protocol.
In Example 3, the apparatus of any one or more of Examples 1-2 optionally includes a second transmitter, the second transmitter including a second transmit DTC, the second transmit DTC configured to receive the central frequency and to provide a second transmitter signal.
In Example 4, the second transmitter of any one or more of Examples 1-3 optionally is configured to process and transmit third information according to a communication protocol different from the first communication protocol.
In Example 5, the first transmit DTC of any one or more of Examples 1-4 optionally is configured to receive first phase ramp information and to provide the first transmitter signal having the second frequency using the first phase ramp information.
In Example 6, the second transmit DTC of any one or more of Examples 1-5 optionally is configured to receive second phase ramp information and to provide the second transmitter signal using second phase ramp information.
In Example 7, the first phase ramp information and the second phase ramp information of any one or more of Examples 1-6 optionally are the same.
In Example 8, the first phase ramp information and the second phase ramp information of any one or more of Examples 1-6 optionally are different.
In Example 9, the first frequency of any one or more of Examples 1-8 optionally is different from the second frequency.
In Example 10, the first frequency of any one or more of Examples 1-9 optionally is different from the first receive frequency.
In Example 11, the second frequency of any one or more of Examples 1-10 optionally is different from the first receive frequency.
In example 12, the second frequency and the first receive frequency of any one or more of Examples 1-11 optionally are different from an integer harmonic frequency of the first frequency.
In Example 13, the first transmitter signal of any one or more of Examples 1-12 optionally includes a first modulated signal, and the first DTC of any one or more of Examples 1-12 optionally is configured to receive first phase ramp information and phase modulation information and to provide the first modulated signal using the first phase ramp information and the phase modulation information.
In Example 14, a method can include generating a central synthesized signal for a plurality of communication circuits of an electronic device using a central frequency synthesizer, receiving the central synthesized signal at a first digital-to time converter (DTC) of a first transmitter of the plurality of communication circuits, providing a first transmitter signal having a first transmitter frequency different from a nominal frequency of the central synthesized signal using the first DTC, receiving the central synthesized signal at a second DTC of a first receiver of the of the plurality of communication circuits, and providing a first receiver signal having a first receiver frequency different from the nominal frequency of the central synthesized signal using the second DTC.
In Example 15, the method of any one or more of Examples 1-14 optionally includes receiving the central synthesized signal at a third DTC, and providing a second transmitter signal having a third frequency using the third DTC. In certain examples, a second transmitter of the plurality of communication circuits can optionally include the third DTC.
In Example 16, the method of any one or more of Examples 1-15 optionally includes processing first transmission data according to a first communication protocol using the first transmitter, and processing second transmission data according to a second communication protocol using the second transmitter.
In Example 17, the first communication protocol of any one or more of Examples 1-16 optionally is different from the second communication protocol.
In Example 18, the method of any one or more of Examples 1-17 optionally includes receiving communication data from an antenna coupled to the first receiver, and processing the communication data according to the first communication protocol.
In Example 19, the first frequency of any one or more of Examples 1-18 optionally is different from the third frequency.
In Example 20, the second frequency of any one or more of Examples 1-19 optionally is different from the third frequency.
In Example 21, an integer harmonic frequency of the nominal frequency of any one or more of Examples 1-20 optionally is different from the first frequency, the second frequency, and the third frequency.
In Example 22, the providing the first transmitter signal of any one or more of Examples 1-21 optionally includes receiving first phase ramp information at the first DTC.
In Example 23, the providing the second transmitter signal of any one or more of Examples 1-22 optionally includes receiving second phase ramp information at the third DTC.
In Example 24, the first phase ramp information of any one or more of Examples 1-23 optionally is the same as the second phase ramp information.
In Example 25, the first phase ramp information of any one or more of Examples 1-24 optionally is different from the second phase ramp information.
In Example 26, a mobile electronic device can include a processor, and a wireless communication system configured to exchange information with the processor and one or more other mobile electronic devices. The wireless communication system can include a central frequency synthesizer configured to provide a central synthesized signal having a first frequency, a first wireless transmitter including a first transmitter DTC, the first DTC configured to receive the central synthesized signal and to provide a first transmitter signal having a first transmitter frequency, and a wireless receiver including a receiver DTC, the receiver DTC configured to receive the central oscillator signal and to provide a first receiver signal having a receiver frequency.
In Example 27, the first DTC of any one or more of Examples 1-26 optionally is configured to receive first phase ramp information to provide the first transmitter signal using the first phase ramp information the central synthesized signal.
In Example 28, the mobile electronic device of any one or more of Examples 1-14 optionally includes a second transmitter having a second transmitter DTC, the second transmitter DTC configured to receive the central synthesized signal and to provide a second transmitter signal having a second transmitter frequency.
In Example 29, the second transmitter DTC of any one or more of Examples 1-28 optionally is configured to receive second phase ramp information to provide the second transmitter signal using the second phase ramp information and the central synthesized signal.
In Example 30, the first phase ramp information of any one or more of Examples 1-31 optionally is different from the second phase ramp information.
In Example 31, a digital-to-time converter (DTC) can include a delay element configured to receive a periodic input signal and to provide a plurality of output phases using the periodic input signal, a multiplexer configured to receive selection information from a controller and to couple one or more of the plurality of output phases to an output of the multiplexer using the selection information, and a plurality of digital-to-analog converters (DACs) coupled to the output of the multiplexer, to receive weight information from the controller, and to provide a plurality of analog signals representative of an output signal.
In Example 32, the DACs of any one or more of Examples 1-31 optionally include current ADCs (iDACs) configured to provide a plurality of analog current signals representative of the output signal.
In Example 33, the DTC of any one or more of Examples 1-32 optionally includes a summing node configured to sum the plurality of analog current signals and to provide the output signal.
In Example 34, the selection information of any one or more of Examples 1-33 optionally includes phase ramp information configured to shift a frequency of the output signal away from a frequency of the periodic input signal.
In Example 35, the selection information of any one or more of Examples 1-34 optionally includes phase modulation information configured to provide phase modulation of the output signal.
In Example 36, weight information of any one or more of Examples 1-35 optionally is configured to suppress noise at one or more a frequencies of the output signal.
In Example 37, the delay element of any one or more of Examples 1-36 optionally includes a delay line.
In Example 38, the delay element of any one or more of Examples 1-37 optionally includes a divider circuit.
In Example 39, the delay element of any one or more of Examples 1-38 optionally includes an delay interpolator.
Example 40 can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1 through 39 to include, subject matter that can include means for performing any one or more of the functions of Examples 1 through 39, or a machine-readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1 through 39.
The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document; for irreconcilable inconsistencies, the usage in this document controls.
In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
This application is a continuation of, and claims the benefit of priority to, U.S. patent application Ser. No. 14/997,056, filed Jan. 15, 2016, which is a continuation of, and claims the benefit of priority to, Lakdawala et al., U.S. patent application Ser. No. 14/138,508, titled, “DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE”, filed Dec. 23, 2013, now issued as U.S. Pat. No. 9,288,841, each of which is hereby incorporated by reference herein in its entirety.
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Parent | 14138508 | Dec 2013 | US |
Child | 14997056 | US |