Direct digital synthesizer for reference frequency generation

Abstract

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fosc and outputs some integer fraction of those pulses at an instantaneous frequency fVp that is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator. The delay signal further controls the frequency of the multi-modulus divider output signal (Vp) to provide an output signal (VD) with an fOUT that has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention provides frequency synthesizer circuit architectures that are particularly adapted for use in computation, control and communication applications.

2. Description of Related Art

Low frequency (32 KHz-300 MHz) clock or timing signals are employed in electronic devices for many different applications. A typical reference oscillator may use a quartz resonator or another resonator which may operate on a fundamental frequency (less than about 40 MHz) or an overtone mode of oscillation (about 30 to 300 MHz). However, certain electronic devices (e.g., mobile communication devices) require higher frequency (500 MHz-3 GHz) timing signals which either cannot be generated directly by quartz resonators or other electro-acoustic resonators, or are prohibitively expensive to generate using such resonators. Also, high-frequency oscillators that use non-acoustic resonator technology (e.g., an inductor/capacitor resonant tank) cannot achieve the low phase noise or low power consumption required by many applications. Furthermore, conventional oscillator solutions may be too costly or too bulky for certain product applications and/or fail to provide a sufficient variety of output frequencies with sufficiently low noise.

An alternate approach to generating a reference signal is frequency synthesis, which can be performed either indirectly, by employing a phase lock loop (“PLL”), or directly, by employing a direct digital synthesizer (“DDS”).

In PLL frequency synthesis, a reference oscillator operating at a relatively low frequency (f_REF) is employed to generate a higher output frequency (f_OUT>f_REF) with a desired accuracy. To accomplish this synthesis, the frequency of a voltage controlled oscillator (“VCO”) is adjusted until the phase error between the reference oscillator and the VCO is minimized. The VCO is adjusted by a feedback loop that compares the frequency and phase of the VCO to that of the reference oscillator. When the loop settles, the VCO frequency closely tracks both the frequency and phase of the reference signal according to a predetermined harmonic relationship defined by the division ratios of the dividers used in the PLL circuit, e.g. f_VCO/N=f_REF/M. Non-harmonic scaling may be obtained by rapidly switching the divider between adjacent ratios P and P+1 with the aid of a controller often employing a delta-sigma modulator loop. The instantaneous output frequency alternates between f_REF*P/M and f_REF*(P+1)/M, and the average frequency equals f_REF*(P+N)/M where N is a non-integer value between 0 and 1. Simultaneously with the divider modulus control, a phase correction is also applied to the divider output signal before it is compared with the reference signal to produce an error signal that is low-pass-filtered and applied to the VCO input. This implementation is also known as a fractional-N synthesizer.

The output signal of a fractional-N PLL may be degraded by the presence of spurious signals and noise that result from the constant switching of the P divider. These undesired signals must be minimized to meet the requirements of practical applications, which results in increased power consumption and loop settling time.

In typical DDS architectures, a higher reference frequency generator is used with a numerically controlled oscillator (“NCO”) to produce an output signal having controlled frequency and phase. The DDS output frequency range and resolution is mainly determined by the reference frequency and the length of the NCO word. As a result, DDS circuits that deliver a higher synthesized output frequency tend to have higher power consumption.

While existing phase interpolating DDS architectures may provide generation of a wide range of output frequencies from a single reference oscillator, improved DDS architectures are desired.

SUMMARY OF THE INVENTION

In accordance with aspects of the present invention, DDS synthesizer architecture derive a signal with selectable output frequency (“f_OUT”) from an oscillator signal with higher fixed frequency (“f_OSC”) using a combination of a multi-modulus divider providing at least two possible modulii for reducing the frequency of an input signal to achieve the desired frequency for f_OUT and a variable delay to achieve a desired instantaneous phase for f_OUT. The resultant f_OUT signal may then be used to clock or drive circuitry in a user device that requires a lower reference frequency.

In one embodiment the frequency synthesizer has an input for receiving a clock reference signal at a first frequency f_osc. The direct digital synthesizer (DDS) architecture has a multi-modulus divider for dividing the frequency of the input signal to provide an intermediate signal. Multi-modulus, as used herein, refers to the multiple programmable division ratios used to divide the frequency of the input signal into a lower frequency. The embodiment also has a numerically controlled oscillator (NCO) having an accumulator receiving an accumulator increment (also referred to as a phase increment) value. The NCO provides a phase value to a latch circuit. The latch circuit receives and is clocked by the intermediate signal wherein the numerically controlled oscillator outputs a delay value comprised of one or more bits and an overflow signal comprised of one or more bits wherein said overflow signal is provided to the multi-modulus divider to select between at least a first divider ratio and a second divider ratio.

The DDS also has a programmable delay generator. In one embodiment, the delay generator receives the delay signal having one or more bits and the overflow signal containing one bit. In preferred embodiments the delay generator receives one or more reference clock signals (e.g. the clock input signal to the multi-modulus divider and or the signal with the intermediate adjusted frequency output from the multi-modulus divider. From the inputs, the delay generator calculates a delay time for application to each pulse in the signal with an intermediate adjusted frequency to provide an output signal which achieves improved phase noise and timing jitter performance (f_out).

In one embodiment the accumulator of the NCO receives “dithered” accumulator increment values from a Pseudo-Random Noise generator. These values introduce a noise-like phase dither to the output of the delay generator. This noise-like phase addition spreads spurious signals that would exist in the DDS output signal if dithering were not performed.

In certain preferred embodiments discussed herein, the multi-modulus divider selects between first and second divider ratios, while in other preferred embodiments the multi-modulus divider selects between a first divider ratio, a second divider ratio and a third divider ratio. In some instances selected embodiments also have one or more programmable dividers. In these embodiments, the programmable divider operates on the signal input into the multi-modulus divider or on the intermediate signal output from the programmable divider. If the former, the programmable pre-multi-modulus divider reduces the overall power consumption by providing a lower frequency signal to the multi-modulus divider. If the latter, the programmable post-multi-modulus divider provides a wide range of division ratios by which the frequency of the signal input to the multi-modulus divider is divided.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects and advantages of the invention will be appreciated more fully from the following further description thereof, with reference to the accompanying drawings, wherein:

FIG. 1 illustrates a functional block diagram of a DDS architecture in accordance with aspects of the invention.

FIG. 2 illustrates a delay generator that can be employed with aspects of the present invention.

FIG. 3 shows the waveform timing relationships for the circuit of FIG. 2.

FIG. 4 is an exemplary timing diagram for the direct digital synthesis block diagram of FIG. 1.

FIGS. 5 a and 5b are tables illustrating the behavior of a 3 and 4-bit NCO DDS systems in accordance with aspects of the present invention.

FIG. 6 illustrates an alternative embodiment of the invention.

FIGS. 7 a and 7b show details of an exemplary frequency plan of a preferred embodiment of the present invention.

FIG. 8 a shows the role of the f_OSCOffset setting of the reference oscillator in the frequency planning of a preferred embodiment.

FIG. 8 b illustrates the functionality of a MCpolarity setting in accordance with aspects of the present invention.

FIG. 9 illustrates an alternate embodiment of the invention that employs a digitally generated randomization signal to create a controlled spread-spectrum reference frequency output.

FIG. 10 illustrates yet another embodiment of the invention.

FIG. 11 illustrates another alternate embodiment of the invention that utilizes a triple-modulus divider.

FIGS. 12 a-c illustrate the operation of one embodiment of FIG. 11.

FIG. 13 illustrates the architecture of a further embodiment of the present invention.

FIG. 14 illustrates a variation of the embodiment shown in FIG. 13.

FIG. 15 a illustrates an alternative embodiment of the invention in which a non-zero-mean pseudo-random noise generator provides a non-zero-mean dither signal to the accumulator.

FIG. 15 b illustrates a detail of the embodiment presented in FIG. 15b. where the K tuning word is split to provide input to the non-zero-mean pseudo-random noise generator.

FIG. 16 a illustrates an alternate embodiment of the invention that features a Controlled PRN Generator.

FIG. 16 b illustrates the Controlled PRN Generator employed in FIG. 16a.

DETAILED DESCRIPTION

The present invention is described in terms of several embodiments. In describing these embodiments, including the drawings, specific terminology will be used for the sake of clarity. Also, in the discussion of certain mathematical relationships, certain variable values are discussed by way of illustration. However, the invention is not intended to be limited to the specific embodiments described below.

FIG. 1 is a schematic illustration of a multi-modulus divider direct digital synthesizer (“DDS”) architecture 10 in accordance with aspects of the present invention. This exemplary DDS architecture 10 includes a reference oscillator 12, a multi-modulus divider 14, an NCO 16 and a delay generator 18, which is also referred to herein as a “phase interpolator.”

Reference oscillator 12 produces a periodic waveform with a frequency f_osc. As shown in the figure, f_OSC is provided to the multi-modulus divider 14 and the delay generator 18. The reference oscillator 12 may, by way of example, utilize a bulk acoustic wave resonator (e.g., FBAR-type or SMR-type), a micromechanical or nanomechanical resonator, a dielectric resonator, an LC tank or a quartz resonator.

The multi-modulus divider 14 is illustrated as a dual modulus divider which is operable to switch between division ratios P and P+1 to modify the received f_OSC signal. As will be discussed in detail below, the division ratio is controlled by the overflow output of the NCO. This overflow output is also referred to as modulus control (“MC”). The multi-modulus divider 14 is preferably synchronous with the oscillator frequency f_OSC.

The NCO 16 includes an adder or accumulator 20 and a holding circuit/register 22. The holding circuit 22 may be, for example, a bank of delay flip-flops or latches. The NCO 16 may also include a look-up table and other phase control circuits (not shown).

The delay generator 18 generally has a programmable delay circuit 24 whose function is to delay individual pulse edges based on a control word. The delay generator 18 also includes a delay control circuit 26 that receives various timing signals along with the NCO output word and provides the control word to the delay circuit 24. The delay generator 18 is used to delay the phase of a resultant output signal relative to the phase the signal input to the delay generator 18.

As shown in FIG. 1, in response to the input signal f_OSC, the multi-modulus programmable divider 14 provides a clocking signal V_p to the NCO 16 and the phase interpolator 18. The frequency f_Vp of signal V_p is related to f_OSC as follows: f_Vp=f_OSC/P_set where P_set can be P or P+1 as determined by the modulus control signal MC output from the NCO 16.

The NCO 16, in particular holding circuit 22, is clocked by the output V_p of the multi-modulus divider 14. As further shown in FIG. 1, a digital tuning word K is provided as an input to the accumulator 20 of the NCO 16. The holding circuit 22 of NCO 16 outputs an overflow value (“OVF”) or MC as well as an output word N_A. The input word K sets the value by which the accumulator output value (“A”) of word length N_A is incremented for each V_p pulse generated by the multi-modulus programmable divider 14. The value D is the portion of the accumulator output value A that is output from the NCO 16. D is used to set the delay of the delay generator/phase interpolator 18. The word length of D is N_D. As described in further detail N_D≦N_A (N_A is the word length of value A).

In particular, the NCO 16, clocked at f_Vp, computes the phase value of the synthesized signal. Tuning word K, provided to accumulator 20 of the NCO 16, specifies how many V_p periods are counted by the accumulator 20 for each f_OUT period. The holding circuit 22 in the NCO 16 updates the phase value calculated by the accumulator 20 at intervals of 1/f_Vp. The delay value (as represented by D and which, in certain embodiments, is a truncated word of that output from the holding circuit) and the overflow signal OVF are provided to the delay generator 18 to generate a residual phase correction via delay control 26.

The instantaneous frequency of signal V_p oscillates between f_OSC/P and f_OSC/(P+¹), where P is the multi-modulus programmable divider base value, depending on the value of the modulus control signal MC. It can be shown that for N_A=N_D, the average value of the output frequency f_OUT is as follows:

f _OUTideal =f _OSC/(P+K/2^NA)  (2)

where P is the multi-modulus programmable divider base value, K is the programmed NCO accumulator increment value as described above and N_A is the NCO word length. The ratio K/2^NA can range from 0 to 1−(2^−NA. As a result, the instantaneous frequency deviation of signal V_p at the n^th pulse instant is:

$\begin{array}{cc}\begin{array}{c}\Delta f_{\mathrm{vp}}\left(n\right)=f_{\mathrm{OUTideal}}-f_{\mathrm{vp}}\left(n\right)\\ =f_{\mathrm{osc}}*\left[1/\left(P+K/2^{N_A}\right)-1/P_n\right]\\ =f_{\mathrm{osc}}/P_n*\left[P_n-\left(P+K/2^{N_A}\right)\right]/\left(P+K/2^{N_A}\right).\end{array}& \left(3\right)\end{array}$

It is easy to prove that the maximum error occurs for K=2^(NA−1). An example of this is illustrated in FIG. 5B discussed below. For large N_A values, this is −f_OSC/(2P²+P) for P_n=P, or f_OSC/(2P²+3P+1) for P_n=P+1.

Holding circuit 22 in NCO 16 latches at least the N_A bits of the accumulator output word A. It is advantageous if the holding circuit 22 also latches the overflow signal bit of the accumulator 20. The holding circuit 22 is latched by the signal V_p. A portion of the accumulator output word, which is referred to herein as delay value D_(n−1), is provided to the delay control circuit 26 of the delay generator 18 along with the overflow value OVF, with a delay of one V_p pulse period. The NCO phase value at each overflow instant represents the residual phase portion of the accumulator output word A and is used to provide a phase correction to the delay control circuit 26 while the overflow pulse OVF (MC) controls the modulus of multi-modulus divider 14. It should be noted that the edges of the V_p pulse train are delayed by the programmable delay generator 18 based on the phase value originating from the NCO 16.

The delay generator 18 may be implemented in different ways. Examples of delay generator implementations are described in U.S. Pat. No. 6,188,261 entitled “Programmable Delay Generator and Application Circuits Having Said Delay Generator” which issued on Feb. 13, 2001 and is incorporated by reference herein. One exemplary implementation of such circuits is shown in FIG. 2. FIG. 2 shows a specific implementation of a delay generator employing an integrator 50 that starts a programmable-slope ramping voltage 52 V_Ramp (e.g. by charging a capacitor with a constant current) after it receives a start pulse (Pulse In). The ramp slope is programmable via a slope control word 54 that determines the delay control range. Signals V_p and Reset are fed to an integrator 56 in addition to the slope control word 54. Signal V_p starts the integrator ramp and signal reset forces it to assume its initial value.

Before the input pulse is applied, a Delay-Set word (derived from delay word D) is input to D/A converter 58 which in turn provides a threshold voltage (V_Threshold). The voltage ramp V_Ramp 52 is compared with the threshold voltage V_Threshold by comparator 60. An output of the comparator 60 is provided to a one-shot multivibrator 62. The resultant output of one-shot multivibrator 62 (V_D) gets triggered each time there is a crossover of V_D below V_Threshold. This crossover determines the delay (t_D) of the output pulse referenced to the input edge. The corresponding waveforms are shown in FIG. 3.

Returning to the embodiment of FIG. 1, for the DDS to operate as desired, the applied delay should be a fraction of the f_OSC period. At the n^th V_p pulse, the applied delay should ideally be D_n−1/2^NA*1/f_OSC, where D_n−1 was the value of the NCO output word at the previous overflow (n−1^th V_p pulse). Depending on the actual implementation of the DDS, N_D can equal N_A or just be a fraction of it (i.e. N_A≧N_D). In any case, the words D and A are related as follows:

D=A/2^NA−ND)  (4)

Therefore, the correction delay added to the n^th V_p pulse edge is T_c(n)=D_(n−1)/2^ND*1/f_OSC. If N_A>N_D, the residual error ΔT_corr=[D_(n−1)/2^ND*A_(n−1)/2^NA]*1/f_OSC results in deterministic quantization noise, and therefore deterministic frequency jitter on the DDS output signal. One skilled in the art would realize that the operation of the overall embodiment of FIG. 1 remains unchanged if the delay has one or more but generally less than P−2 f_OSC periods added to all of the delay values.

In addition to the selected portion of the accumulated phase value A and OVF, the delay control circuit also could receive signal f_OSC from the reference oscillator 12 as this could enhance the delay accuracy. V_p is also optionally provided to the delay generator circuit 18. Since the more timing information that is provided to the delay generator, the better it will perform, FIG. 1 illustrates the delay control with inputs of V_p and f_OSC. The delay control 26 uses the truncated accumulator output value D, the value OVF and optionally, V_p and f_OSC to perform delay correction on V_p that essentially shifts the V_p pulses by a fraction of the f_OSC period according to the previous NCO output word. The resultant signal V_D is a phase corrected signal.

The output frequency is given by the following relationship: f_OUT=f_OSC/(P+K/2^NA) where f_OSC is the reference oscillator frequency, P is the dual modulus divider base ratio, K is the NCO accumulator increment, and N_A is the NCO word length.

The maximum frequency synthesis resolution (taking K=0) is given as:

Δf=f_OSC*(1/P−1/(P+1/2^NA))  (5)

The average frequency deviation over M V_D output pulses is defined as:

Δf=1/M*Σ(|f_inst(n)−f_OUTideal|)  (6)

where f_inst(n) is the instantaneous frequency of the corrected pulses after the phase correction has been applied. This is given as:

f _OUT=1/T_D(n)=1/[t_D(n+1)−t_D(n)]=1/[T_P(n)+T_OSC/2^ND*(D_(n)−D_(n−1))]  (7)

Where t_D(n+1) and t_D(n) are the delay-corrected output pulse edges at instances n+1 and n, corresponding to delay correction words D_(n) and D_(n−1) and T_p(n) is the period of the P divider output at the n^th instance.

It can be seen in FIG. 1 that NCO 16 is clocked by the dual modulus divider output signal V_p to provide a delay correction value to the delay generator circuit 18. As will be discussed in more detail below, an optional binary frequency divider 104 shown in FIG. 6 may provide a fixed binary frequency division while it will also correct the duty cycle of the output waveform (f_OUT). As the reference oscillator signal at frequency f_OSC in FIG. 1 is operated on by programmable divider 60, the frequency of V_p is necessarily lower than f_OSC.

In fact, the higher the f_OSC/f_OUT ratio, the finer the f_OUT frequency synthesis resolution for a given NCO word length as shown above. The advantage of a high f_OSC/f_OUT ratio is that the delay generator and the NCO now operate at a much lower rate than in conventional phase-interpolating DDS architectures and therefore the circuit architecture of FIG. 1 features reduced power consumption over these DDS implementations. Furthermore, in FIG. 1, interpolation by the delay generator circuit (phase interpolator) 18 occurs at lower speeds, which offers a significant improvement over the prior art as the lower clocking speed results in a lower power dissipation.

The output pulse V_D has a duty cycle that depends on the synthesized frequency f_OUT. Optionally, a toggle Flip-Flop (T-FF) with an output of half the frequency (f_OUT/2) or other latching mechanism can be used to produce a duty-cycle corrected version of the synthesized output frequency signal.

FIG. 4 is a timing diagram showing an example of operation of the circuit architecture of FIG. 1. FIG. 5A is a table that illustrates the behavior of the system described in FIG. 4. A number of signals are shown in the plots illustrated in FIG. 4. Before addressing the various plots, it is important to understand that certain parameters associated with the architectures have been selected in this example for illustrative purposes. For instance, the divider modulus base value (P) has been set to 4. This means that unless there is an overflow, four f_OSC pulses are typically passed before a V_p pulse comes from the programmable divider 18. When an overflow occurs, the divider counts 5 f_OSC pulses before a V_p is produced. A larger value of P results in a lower output frequency. While P has been set to a value of 4 in this example, it should be understood that P may be any integer value. P may be set at manufacture to a specific value or range of values depending upon operating conditions. By way of example only, P may be any integer from 3 to 30. Said another way, the larger the value of P, the better control and finer resolution there is over the synthesized output signal V_p.

In the example of FIG. 4, the word length N_A of the NCO accumulator 16 is selected to be 3 bits. This provides a maximum value of A to be 7. A larger word length N_A will result in a finer f_OUT resolution as described above. The resolution of the accumulator output value determines the resolution of the phase correction word. In other words, the precision of the ratio of the accumulator increment to the full-scale range determines the time-scale granularity of the f_OUT pulse edges. Another value set in this example is the word length of the delay being applied, which here is shown to be equal to N_D.

As mentioned above, in general N_A≧N_D. The value of N_A determines the granularity of the average frequency programming as shown above through the ratio K/2^NA. As the instantaneous frequency of signal V_p will vary between f_OSC/P and f_OSC/P+1, the value of N_D determines the effectiveness of the phase interpolation which ultimately determines the phase jitter (or Phase Noise) of the synthesizer.

Obviously, the larger the NCO word length the finer the output frequency synthesis resolution. For example, in a practical frequency synthesis application with a f_OSC frequency in the neighborhood of 2 GHz, if one wants to generate any arbitrary frequency with an accuracy of 1 PPM in the range of 400 to 500 MHz the P divider should be set up for division-by 4 or 5, while a word length N_A greater than 18 bits should be used. In this particular application, given that the instantaneous value of the frequency f_Vp will be switching between 400 and 500 MHz and given the current state of the art of delay generator designs, and given that implementations of digital to delay converters with larger N_D values become exponentially more complex and consume exponentially more power (i.e. the more bits, the more complicated, with, for example, 6 bits being more complicated than 4 bits and 9 bits more complicated than 6 bits, etc.), N_D would be chosen considerably smaller than N_A in this case. In particular, the value of N_D will generally be set as small as possible while still achieving sufficient cycle-to-cycle jitter performance and sufficient high frequency phase noise performance for the target application.

The rate of overflow is dependent on the accumulator increment value K. The rate of overflow affects how the delay value applied to the phase interpolator varies (note that it can only be greater than zero). In this example, the increment value, K, is set at 3. The ratio of K to 2^NA determines the effective divide ratio of the synthesizer (i.e. fractional division). As K assumes values in the range of 1 to 2^NA−1 the output frequency f_OUT ranges from f_OSC/(P+2^−NA) to f_OSC/(P+1−2^−NA).

In the timing diagram of FIG. 4, the topmost plot shows the waveform output by the reference oscillator. The frequency of the reference oscillator output is f_OSC as shown.

The second plot from the top shows the waveform of signal V_p output by multi-modulus divider 14. As discussed above, V_p is provided to the delay generator 18, as well as to D-FF 22 of the NCO 16. The timing of the pulses V_p depends upon the multi-modulus divider 14 toggling between P and P+1. Signal V_p sets the NCO operational frequency.

In FIG. 4, the third plot from the top presents the value of the accumulator output word (D), which produces the delay control word to be applied to V_p. A delayed version of this value is applied to the delay generator as described below.

The fourth plot from the top shows the overflow signal OVF which issues from holding or latching circuit 22. The OVF signal controls the division ratio (modulus control) of multi-modulus divider 14. It is also input into delay control circuit 26 of the delay generator 18. As shown in FIG. 4, OVF lasts for one V_p cycle every time it is triggered. The accumulator values that cause the overflow are set forth in the table in FIG. 7A. Note, in this example, the overflow value causes the P value to change from P to P+1 which causes the T_osc count to increase from 4 to 5. The increment of t_p and the value of T_p also increase in duration during overflow.

The fifth plot from the top shows a signal representing the delay value (D_(n)), which is output by the accumulator 20. In the present example, this signal may range from a value of zero to a value of 7. Other values may be selected depending upon a design choice for various operating conditions. For K=3, the leftmost delay value is zero, while the next delay value is 3, the third delay is 6, the fourth delay is 1, the fifth delay is 4, the sixth delay is 7, the seventh delay is 2, the eighth delay is 5 and the ninth delay is 0.

The sixth plot from the top presents delay value (D_(n−1)) applied to delay generator/phase interpolator 18 via signal D output from holding/latching circuit 22 of NCO 16. It can be easily observed that the D_(n−1) are staggered by one V_p cycle relative to D_(n).

Finally, the seventh plot from the top presents a pulse train showing the delay-compensated output pulse signal V_D of FIG. 1, in relation to signal V_p. Referring to FIG. 5A it is observed that the increments of t_D are uniform, and the effect of the uniform values of t_D results in a uniform value for f_out. As noted from FIG. 3 t_D is the time delay applied to the pulse V_D relative to the pulse edge for V_p. FIG. 5B illustrates the effect of a change in the value of N_A and K from 3 (in FIG. 5A) to 4 and 7, respectively, in FIG. 5B. In addition to a change in the increments for an overflow to occur, FIG. 5B illustrates that T_D and therefore f_out oscillates between two values. FIG. 5B illustrates a system operation where the input increment K≈2^NA−1. In this example, the K increment (7) is approximately equal to 2⁴⁻¹ (i.e. 8). As stated below, it is preferred if K does not assume values at or near the limits of its range of values.

As explained above with regard to FIGS. 1 and 4, the edge-corrected V_D pulses can be duty-cycle corrected by passing them through a device such as a toggle flip-flop or a binary frequency divider, as will be described in more detail below with regard to FIG. 6.

FIG. 6 is a schematic illustration of an alternative embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture 100 in accordance with aspects of the present invention. The architecture 100 includes many of the same components as the architecture of FIG. 1, which operates in the manner discussed above. For instance, the reference oscillator 12 produces a waveform with a frequency f_OSC. In the present embodiment the reference oscillator 12 also includes a frequency offset control function f_OSCOffset that causes the frequency f_OSC of its output signal to be shifted by a given amount (e.g. 2%). The architecture 100 also includes the multi-modulus programmable divider 14, programmable NCO 16, and delay generator circuit 18.

As shown in FIG. 6, the architecture 100 preferably also includes two programmable binary dividers 102 and 104, a programmable modulus control inverter 106, and a temperature sensing unit such as digital thermometer 108. The digital thermometer 108 may receive a signal Tmeas.enable as shown in the figure. This signal may enable/disable measurement by the thermometer 108.

The reference oscillator frequency f_OSC can be optionally divided using the binary divider 102 to a lower master clock frequency f_CLK to enable lower power consumption but provides cruder delay resolution (i.e. introduces more jitter). The binary divider 102 receives signal f_OSC from the reference oscillator 12 and outputs a signal of frequency f_CLK, which is provided to the multi-modulus programmable divider 14 as well as the delay control circuit 26 of delay generator 18. The binary divider 102 divides down the oscillator frequency f_OSC, e.g., by a selectable but fixed integer value (B1) to generate f_CLK. This provides reduced power dissipation, as the DDS operates now at a reduced speed, while it also increases the total delay range that must be covered by the phase interpolator. This typically degrades the absolute jitter performance of the phase interpolator because digital-to-time converters, like digital-to-analog data converters, tend to have a fixed ratio between the magnitude of the absolute errors and the full scale range. Doubling the maximum delay which the phase interpolator must provide will, to first order, double the absolute value of the maximum errors in the delay. Note that, in this embodiment, the input into the multi-modulus divider 14 is f_clk and not f_osc (as in FIG. 1). In this embodiment f_clk is optionally input into delay control 26.

The multi-modulus divider 14 is preferably synchronous with the reference oscillator 12. As discussed above with regard to FIG. 1, the output of the multi-modulus divider 14 is signal V_p. The parameters B1 of the binary divider 102 and P_set of the multi-modulus divider 14 are used to set a coarse frequency range for V_p, which also is the operational frequency of the delay generator 18. The frequency of V_p is related to f_OSC as follows:

F _Vp =f _OSC/(2^B1P_set)=f_CLK/P_set  (8)

where P_set can be P or P+1 as determined by the modulus control signal MC. The setting of B1 effectively enables a trade-off between noise performance (i.e. jitter) and power consumption.

As shown in FIG. 6, input signal K is provided to the accumulator 20 of NCO 16. K is composed of a K_Fset word along with an additional correction value K_FC originating from the digital thermometer. As explained above, the resulting increment K is used to determine the rate of overflows and subsequently defines how many V_p pulses are counted by the programmable divider 18. The output A of accumulator 20 is a delay value D_(n) and an overflow signal. A latching circuit such as a bank of N_A+1 data flip-flops (“D-FF”) 22 in the NCO 16 updates the output value of the accumulator 20, shown as signal A at specified intervals. The accumulator output values A (i.e. the phase delay values) are optionally truncated into values D which are provided to delay control circuit 26 of the delay generator 18 along with an overflow signal OVF, the master clock signal f_CLK and optionally the signal V_p. As previously noted, it is advantageous, but not required, to provide V_p and the signal input into the multi-modulus divider (f_CLK in FIG. 6) to synchronize the delay generator to the V_p pulse.

As shown, V_p is also provided to the delay generator circuit 18. The delay control 26 uses the accumulated value D and OVF to perform delay generation on V_p and to output a resultant signal V_D, which is a corrected V_p signal. Delay control 26 uses optional inputs f_clk and V_p to synchronize the delay generator with Vp. V_D is provided to the binary divider 104. As with the binary divider 102, an input to the binary divider 104, B2, may be a user-specified or predetermined input that sets the binary division ratio at the output of the delay generator 18. The binary division ratio is controlled through a B2 programming word supplied to the binary divider 104. A buffer 110 may be employed to isolate the operation of the DDS from a variety of external loads (not shown). The resultant output is a signal f_OUT.

As discussed above, coarse adjustments of the output frequency can be primarily determined through programming words to the binary frequency dividers 102 and 104. This range of frequencies is also governed by the range of values for P_set in the multi-modulus P/(P+1) divider 14. To those skilled in the art it is obvious that if the selected range of possible P/(P+1) values spans an octave, i.e., max (P_set)>2*min(P_set), in combination with a programmable binary divider such as B2, the system can yield a multi-octave output frequency (f_OUT) coverage. While programmable dividers 102 (B1) and 104 (B2) are not required to be binary, the use of other integer dividers require more power consumption and do not provide for duty cycle correction.

Additional frequency control can be had through the configuration of the divider modulus control polarity MCpolarity applied to the programmable modulus control inverter 106. In the previous embodiments (MC_p=0) it has been assumed that an overflow OVF condition causes the dual modulus divider to divide by P+1. In this case, the output frequency in the architecture of FIG. 6 is given by the following relationship:

f _OUT =f _OSC/2^B1*1/(P+K/2^NA)/2^B2  (9)

If MCpolarity is set so that during regular NCO increments the multi-modulus divider 14 divides by P+1 and during overflows it divides by P (MC_p=1) then the output frequency is:

f _OUT =f _OSC/2^B1*1/(P+1−K/2^NA)/2^B2.  (10)

This configuration also requires that the delay compensation word is bit inverted (i.e. D_MCp=1=1−D_MCp=0) So that maximum delay settings correspond to pulses resulting from division by P+1. The frequency coverage dependence on the MCpolarity signal is illustrated in FIG. 8B.

Fine adjustment of the output frequency is controlled by K as explained above. The increment word K of word length N_K is input to the NCO accumulator 20 and determines how fast the accumulator output A advances for each clock pulse V_p generated by the programmable multi-modulus divider 14. Depending on the application, the increment K can be fixed at K_Fset producing a fixed output frequency or can be dynamically adjusted producing phase or frequency deviations of the output signal.

FIG. 6 shows the increment K as a sum of the programming words K_Fset and K_FC with word lengths N_Fset and N_FC, respectively. While K_Fset may be programmed during the manufacturing process to determine the nominal output frequency f_OUT,nom, the frequency correction word K_FC is updated periodically to correct the output frequency for possible drifts of f_OSC due to temperature fluctuations as measured by the thermometer 108. The intermittently-operated thermometer 108 may include an accurate temperature sensor, an analog-to-digital converter and a numerical circuit that produces a supplementary correction value that modifies the effective synthesizer division ratio as follows:

f _OSC /f _OUT=2^B1+B2*(P+[K_Fset+K_FC]/2^NA)  (11)

If f_OSC drifts due to a difference in temperature by an amount Δf_OSC then the output frequency will also drift as follows:

f _OUT +Δf _OUT=(f_OSC+Δf_OSC)*2^−(B1+B2)/(P+[K_Fset+K_FC]/2^NA)  (12)

To eliminate the output drift the correction increment should be:

K _FC =Δf _OSC /f _OSC*(P*2^NA+K_Fset)  (13)

A variety of temperature-to-increment converters and drift correction mechanisms can be implemented in this block.

Alternatively, K_Fset can be dynamically adjusted according to a phase modulation word (not shown) to produce an output signal featuring continuously variable phase and/or frequency. In this case, a separate phase modulation controller would be inserted at the K_Fset input of the adder before the NCO 16.

FIG. 7 a shows an exemplary frequency plot for a preferred embodiment with B1=1, B2=1, and P having values of 2, 3 and 4. Also f_OSC=2000 MHz and N_A=10. It can be easily seen that no gaps in f_OUT coverage (a range of about 500 MHz to 1000 MHz) exist as P transitions through various values. It should also be understood that these values for B1, B2, P, f_OSC and N_A are merely illustrative and do not limit the scope of the invention.

FIG. 7 b shows another exemplary frequency plan for a preferred embodiment with B1=1, B2=1 and 2, and P=2, 3 and 4. And as with FIG. 7a, f_OSC=2000MHz and N_A=10. It can be easily seen that the output coverage (a range of about 250 MHz to 1000 MHz) is expanded by an additional factor of 2 by setting the output divider to divide by 2 (i.e., when B2=2).

FIG. 8 a illustrates the use of the oscillator offset function f_OSCOffset. This setting shifts the frequency of the reference oscillator f_OSC by a small amount (e.g. less than ˜2%) and may be programmed during the manufacturing of the product. It can be easily seen that this option can enable alternative output frequency coverage around the boundary frequencies for different P divider settings.

FIG. 8 b illustrates the effects of the MCpolarity setting in the frequency selection. The output frequency is plotted against the normalized K value for both configurations of the MC polarity. It can be easily seen that one curve is the inverse of the other. As the two MC polarity settings configure both the programmable divider and the delay generator in complementary ways, they provide diversity in selecting the output frequency.

FIG. 9 is a schematic illustration of an alternate embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture 200, which incorporates many of the elements shown and described with regard to FIGS. 1 and 8. FIG. 9 further includes a zero-mean Pseudo-Random Noise (“PRN”) generator 202 that produces a dynamically variable (dithering) accumulator increment. This in turn results in a phase-dithered output delay word that applies a controlled noise-like phase correction to the VP signal. This noise-like phase addition “frequency-spreads” any discrete spurious signals and thus reduces their amplitude. The coherence of the f_OUT instantaneous frequency fluctuations is reduced by this random jitter process that also features a zero-mean. The PRN generator is clocked by the V_p signal and has a word length N_PRN. One skilled in the art is aware of different approaches for the construction of PRN generators. One example is a linear code sequence generator that can be made up of any set of delay elements in conjunction with linear combining elements in a feedback path such that the number of states the generator can assume is a function of the length (in time) of the delay elements and the particular combination of feedback. These structures are referred to as Linear Feedback Shift Registers (LFSR). One skilled in the art can readily integrate such structures into a circuit. The resulting pseudo-random instantaneous output frequency jumps are as shown below:

f _OUT(n)=f_OSC*2^−(B1+B2)/(P+[K_Fset+K_FC+K_PRN(n)]/2^NA)  (14)

where f_OUT(n) is the output frequency at the n^th V_p instant and K_PRN(n) is the dithering PRN increment issued by the PRN generator 202.

FIG. 10 is a schematic illustration of another alternate embodiment 300 of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture in accordance with aspects of the present invention also shown in FIGS. 1 and 6 and 9. The only difference between the embodiments of FIG. 9 and FIG. 10 is the point where the dithering from the PRN generator 202 is inserted. The PRN 202 phase increment is added at the output of the NCO 16. The adder 203 sums delay value D_i and K_PRN to supply the output D_O along with the summation overflow bit OVF_D to the delay control block 26. In this embodiment, the PRN word length N_PRN is smaller than the accumulator input/NCO output word length N_D and much smaller than accumulator output word length N_A. It should be noted that after the PRN addition, the word length of D_O is truncated back to N_D. This embodiment can be more suitable for the purposes of further reduction in spurious signals than the embodiment illustrated in FIG. 9.

Other dithering schemes are well known to one skilled in the art. One such example is described in U.S. Pat. No. 4,410,954 entitled “Digital frequency synthesizer with random jittering for reducing discrete spectral spurs,” which issued on Oct. 18, 1983 and is hereby incorporated by reference.

Another application where the increment K is also modulated in a controlled fashion is in “spread-spectrum” clocks to enable the suppression of Electro-Magnetic Interference (“EMI”) products in noise sensitive applications. The difference with the PRN increment dithering described above is that spread spectrum clock oscillators spread out the concentrated clock energy on their nominal output frequency to a broader bandwidth and controlled frequency range (e.g. ˜1% of the output frequency). The total energy remains the same but the peak energy is spread out to near-by frequencies. The embodiments illustrated in FIGS. 9 and 10 can also implement spread-spectrum PRN functions but it is advantageous if frequency deviations do not exceed the allowed range of values of the K/2^NA ratio.

Thus, it can be seen that the output frequency f_OUT for architectures implementing aspects of the present invention is dependent upon a number of parameters, including the reference oscillator frequency, the two binary divider ratios B1 and B2, the dual modulus divider ratio P, the increment associated with the accumulator, and the settings for the P modulus control polarity configuration and the f_OSCOffset setting.

FIG. 11 is a schematic illustration of another alternate embodiment 400 of the invention. This embodiment addresses the use of the invention when temperature, spread spectrum frequency modulation, and external modulation inputs added together could cause the value of K/2^ÂN_A to move above its maximum value (1) or below its minimum value (0). In such applications a problem is created when the nominal value of K must be selected near its maximum or minimum value in order to set the output frequency to its desired value. To understand this problem, consider that the maximum output frequency for the architecture in FIG. 1 is f_osc/P_min (the oscillator frequency over the minimum value of P) and the highest frequency of the output is f_osc/(P_max+1) (the oscillator frequency over 1+the maximum value of P). By selecting the appropriate value of P and K, any arbitrary frequency between these two limits can be selected. However, the value of P and K that give a frequency are unique since K can only represent a fraction (less than 1) of an oscillator period, T_osc. Therefore, some possible output frequencies will require the normalized value of K to be near 0 or near 1. If temperature correction terms, external modulation terms, or spread spectrum modulation terms are added to K, the ratio K/2^NA would need to exceed the limits of 0 or 1 and the loop would fail to operate correctly. The discussion of FIG. 8a describes a method to keep the normalized value of K from being too close to either end of the (0,1) range by pulling the oscillator frequency when K_Fset falls too close to a limit moving the nominal value of K further from the limit.

FIG. 11 illustrates an improved structure and method for achieving this result. Instead of requiring a change in the oscillator frequency, which may compromise the oscillator's performance as a frequency reference, FIG. 11 extends the allowed normalized range of K (i.e., K/2̂N_A) to be from 0-2 oscillator periods instead of the 0-1 oscillator period range provided by the architecture in FIG. 1.

The embodiment in FIG. 11 operates in a way that is similar to the embodiment in FIG. 1 except that the division modulus of the multi-modulus divider 14′ is now controlled by both the overflow signal OVF (MC1) (which is like the OVF from FIG. 1) and the MSB (MC0) of word D instead of just using the OVF pulse as in the embodiment illustrated in FIG. 1. Also, only the N_A−1 lower bits from the NCO output word are used for feedback to the accumulator input, as well as for delay compensation (before truncation to N_D bits). For example, for the embodiment in FIG. 1, when the phase accumulator 20 output is 16 bits, 1 bit (OVF) is fed to the multi-modulus divider 14 and retired and the remaining 15 bits are added to K in the accumulator 20 to form the next accumulator 20 output. In FIG. 1, K is also a 15 bit binary word (i.e., it ranges from 1 up to 32,767); therefore, the sum of K and the 15 bit fed back remainder is a 16 bit word that can take on all possible 16-bit values, 0-65,535. In the embodiment in FIG. 11, the range of allowed increments is increased 2-fold compared to the fed-back remainder (i.e. N_K=N_A). The sum of a 15 bit remainder and a 16 bit K is a 17 bit word that ranges from 0-98,303. By increasing to a triple modulus divider P, (e.g., P, P+1, P+2), the two-bit overflow signal (MC1 and MC0) pulses are used to select the modulus while the same 15 bit remainder is returned for accumulation in the next period. As in the embodiments described above, a portion of this word is also used for the (n+1)^th instance delay compensation of the multi-modulus divider output pulse. It should be obvious that this concept can be extended to higher order modulus dividers (e.g., P, P+1, P+2, P+3 etc.) in a straightforward manner by simply using more of the MSBs of the accumulator output as part of the OVF signal to control the multi-modulus divider and returning only the remaining accumulator output bits to form the remainder to be accumulated in the next period.

Operationally, the formula for the output frequency of the embodiment in FIG. 11 is:

f _OUT =f _OSC/(P+2*K/2^NA)  (15)

where f_OSC is the reference oscillator frequency, P is the base value of the P/P+1/P+2 multi-modulus programmable divider, K is the increment and N_A=N_K is the increment word length. Since K can range from 0 to 2^NA−1, f_OUT can range from (f_OSC/2)/P to (f_OSC/2)/(P+2−1/2^NA). At the nominal center frequency, the ratio 2K/2^NA would be centered around 1 and set to range from 0.5 to 1.5 in order to select any desired frequency in the range around f_osc/(P+1). Note, the advantage of the embodiment of FIG. 11 over that of FIG. 1 is the added redundancy in defining f_out. There are now two values of P and K that can be used to create any specific frequency. The added degree of freedom is what makes it possible to avoid selecting a nominal value of K near either end of its allowed range. In the specific case of a triple modulus programmable divider DDS, having the normalized 2K/2^NA range from 0.5-1.5 allows the selection of all possible frequencies with the appropriate selection of P. And, this allows any dynamic components (e.g., temperature compensation, external modulation, spread spectrum modulation, etc.) to vary the overall output period by up to +/−0.5 of a reference oscillator period before the minimum or maximum value of K is exceeded. If larger dynamic components need to be accommodated, a higher modulus programmable divider can be employed and the range of K can be further increased.

FIG. 12 a illustrates the operation of the triple modulus DDS with P=4, f_OSC=2 GHz, N_A=N_K=4, K=11 and N_D=3. FIG. 12b shows the Modulus control truth table of the multi-modulus divider for values of MC0 and MC1 and FIG. 12c shows the P division cycle count and the output pulse period for all possible increments of a 4 bit word.

FIG. 13 shows an embodiment using the circuit architecture of FIG. 11 with elements of the embodiment of FIG. 9. For instance, it includes a P, P+1, P+2 multi-modulus divider 14′ controlled by both the overflow OVF and the MSB as well as a spreading generator 202. The output frequency f_OUT is given by the following relationship:

f _OUT=(f_OSC/2^B1+B2)*(1/(P+[K_Fset+K_FC+K_SS(n)]/2^NA))  (16)

where f_OUT(n) is the output frequency at the n^th instant and K_SS(n) is the spreading fractional increment issued by the spreading generator (202). One skilled in the art is aware of several different approaches for the effective spreading sequence that is provided by the spread generator (202). Examples include a predetermined noise generation pattern as described above, a linear deterministic function or other deterministic function (e.g. a “Hershey Kiss” function).

FIG. 14 shows a variation of the embodiments of FIGS. 11 and 13 in which the spreading word K_SS is added at the output of the accumulator, in a fashion similar to the embodiment of FIG. 10.

FIG. 15 a depicts an alternate embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture 1500 that incorporates the elements shown and described with regard to FIGS. 1 and 9. The embodiment in FIG. 15a illustrates one mechanism for inducing the generation of the dynamically variable (dithering) accumulator increment.

Dithering mitigates the spurious tones that can result from the discrete response of the NCO and the delay generator in the DDS. In an ideal DDS, the NCO would have infinite resolution and the delay generator would delay pulses Vp by the exact time delay required to synthesize the desired output signal frequency. However, in practice, the delay generator has a discrete response, i.e. it can delay pulses Vp only by certain values of time delay. Also, the NCO has a higher resolution than the delay generator. As a result, for most values of increment K, the instantaneous period of the DDS output signal toggles between two values, and the toggling action repeats with a fixed pattern. In the frequency domain, this fixed-pattern toggling action yields spurious tones that degrade the spectral purity of the DDS as a reference frequency generator. The fixed-pattern toggling action can be disrupted by arithmetically dithering the increment K, the accumulator output A, or the delay word D, or by directly dithering the response of the phase generator. Ideally, dithering should be performed by a random signal. In practice, it is sufficient to employ a pseudo-random signal that repeats with a long sequence length. By disrupting the fixed-pattern toggling action, dithering effectively spreads the spurious tone energy across a wide frequency range and therefore decreases the spurious tone peak amplitude in the frequency domain. One trade-off is that dithering, because it adds randomness to the phase increment K, increases the cycle-to-cycle jitter of the DDS output signal.

Architecturally, in the embodiment illustrated in FIG. 15a, the dithering mechanism may be provided upstream of the accumulator 20 of the NCO 16. As illustrated, FIG. 15a includes a Pseudo-Random Noise (“PRN”) generator 1502 that generates a pseudo-random sequence K_PRN with a non-zero mean. That is, the mean of K_PRN is some value (positive or negative) other than zero (although one skilled in the art knows that the mean value may be zero). Preferably the pseudo-random sequence is a sequence of binary words, although one skilled in the art understands that other numeral systems may be employed to represent the sequence of pseudo-random numbers. The pseudo-random binary sequence word width is N_PRN bits. Typically, N_PRN ranges from 2 to 5. However, one skilled in the art understands that N_PRN may range from 1 (in which case K_PRN is a single-bit sequence) to 10 or even higher.

The non-zero-mean PRN generator 1502 is clocked by the V_p signal and receives K_low, as data input. It produces pseudo-random sequence K_PRN with a mean value of K_low.

K_low is a binary word composed of the N_A−N_D least-significant bits of the total tuning increment K=K_Fset+K_FC. The N_D most-significant bits of K form K_high, such that the relationship of K_high and K_low is:

K _Fset +K _FC =K=K _high*2^(NA−ND)+K_low  (17)

FIG. 15 b illustrates a detailed configuration of the arithmetic circuit 1504 that computes K, forms K_high and K_low, and computes the dithered accumulator increment K′. Circuit 1504 comprises an adder 1506, a split circuit 1508 and another adder 1510. Adder 1506 sums the K_Fset with K_FC to produce the K word with N_A=N_K bit length, as described in FIG. 9. Then the K word is split by the split circuit 1508 into its N_D most-significant bits (to form K_high with length N_D) and its N_A−N_D least-significant bits (to form K_low with length N_A−N_D). Note that, when word K is represented in binary on a bus, the split operation implemented by circuit 1508 trivially consists in selecting the signals off MSB bus wires to form K_high and the signals off LSB bus wires to form K_low.

Adder 1510 sums K_PRN with K_high to produce the K′ word, which is the dithered accumulator increment K′ to be applied to the NCO. Therefore, the accumulator produces a reduced word of N_D bits. In contrast, the accumulator employed with the zero-mean PRN generator in FIG. 9 processes data with word length N_A≧N_D.

The dithered accumulator increment K′ induces the NCO to produce a phase-dithered D signal to set the delay of the delay generator 18. As stated above, a non-zero-mean PRN generator enables the accumulator to produce a shorter word length. Thus, a simpler and cheaper implementation of the accumulator and NCO may be realized with a non-zero-mean PRN than with a zero-mean PRN generator.

The non-zero-mean PRN generator 1502 may be integrated with a DDS as a separate component, or as part of the NCO. The skilled person is aware that there are many potential configurations of the non-zero-mean PRN generator 1502, depending upon the design of the DDS with which it is integrated. For example, for many applications of the DDS, it is advantageous to reduce the phase noise of the DDS output signal in certain frequency ranges (such as below 20 MHz, in the case of a 100 MHz output frequency). To reduce spurious tones in those frequency ranges, the non-zero-mean PRN generator can be configured to shape the pseudo-random noise out of those frequency ranges. A non-zero-mean PRN generator implemented with a digital Delta-Sigma modulator (commonly noted ΔΣ modulator, and alternately referred to as digital Sigma-Delta modulator and noted ΣΔ modulator) may provide such noise shaping properties.

A multi-stage noise shaping (MASH) ΔΣ modulator may be used for its relatively simple hardware implementation and guaranteed stability. Detailed implementations of MASH ΔΣ modulators are described in “Understanding Delta-Sigma Data Converters” by Schreier and Temes (Wiley, 2004), which is incorporated by reference herein in its entirety.

Preferably, a ΔΣ modulator with long sequence length may be used. Various techniques may be adopted to generate a long (or maximum) sequence length, such as those described in the following publications: Hosseini, K. et al. “Maximum Sequence Length MASH Digital Delta-Sigma Modulators” IEEE Transactions on Circuits and Systems—I: Regular Papers, 54(12) pp. 2628-2638 (December 2007) and Hosseini, K. et al. “Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators” IEEE Transactions on Circuits and Systems—II: Express Briefs, 55(11), pp. 1104-1108, November 2008).

The architectures illustrated in FIGS. 9 and 15a-b may be modified to selectively enable the use of PRN generator or disable its use. As such, the DDS may operate with dithering as illustrated in FIG. 9 or 15a-b or operate without dithering as illustrated in FIG. 1. This enables a DDS to selectively suppress dithering for those values of accumulator increment K that do not induce undesired spurious tones.

FIG. 16 a depicts an alternate embodiment of the invention. It illustrates a multi-modulus divider direct digital synthesizer architecture 1600 that incorporates the elements shown and described with regard to FIGS. 1, 9 and 15a. The embodiment in FIG. 16a incorporates a Controlled PRN Generator 1602, which is illustrated in details in FIG. 16b. The Controlled PRN Generator 1602 may comprise one or more PRN generators, which may be zero-mean PRN or non-zero-mean PRN. It takes K_Fset and K_FC as input signals, and outputs a tuning word K″ with N_K word length to the NCO 16. Various types of control signals, such as “dither enable” and “dither select”, may be provided to the Controlled PRN Generator to facilitate PRN enable/disable and selection functions.

FIG. 16 b illustrates a detailed architecture of the Controlled PRN Generator. It comprises a zero-mean PRN generator 202 as described in FIG. 9, and a non-zero-mean PRN generator 1502 as described in FIG. 15a. It also comprises the elements of arithmetic circuit 1504 as described in FIG. 15b. These elements include adders 1506 and 1510, and a split circuit 1508. Additional circuits, such as bit-shift multiplier 1606 and adder 1610, may also be used.

In addition, the Controlled PRN Generator may include a 3-to-1 multiplexer 1608 that may be used to select from the signals of K, K₂ and K₃. Signal K is the accumulator increment to be applied to the NCO, which is obtained by K=K_Fset+K_FC. Signal K₂ is a dithered signal of K generated by the non-zero-mean PRN generator 202. Signal K₃ is a dithered signal of K obtained by the zero-mean PRN generator 1502.

As shown, the Controlled PRN Generator comprises a dither control circuit 1604 that enables or disables the PRN generators and controls the 3-to-1 multiplexer 1608. The dither control circuit takes K_Fset as input, and is controlled by a user-provided dither enable signal and a user-provided dither select signal. Control signals may be output from the dither control circuit to disable zero-mean PRN generator 202, and non-zero-mean PRN generator 1502, and to control the multiplexer 1608.

Claims

1. A frequency synthesizer comprising: an input for receiving a clock reference signal at a first input frequency;a multi-modulus divider for dividing the input frequency to provide an intermediate signal with an adjusted frequency;a numerically controlled oscillator comprising an accumulator receiving an accumulator increment value for providing a phase value and a latch circuit that receives and is clocked by the intermediate signal with the adjusted frequency wherein the numerically controlled oscillator outputs a delay value and an overflow signal each comprised of one or more bits wherein said overflow signal is provided to said multi-modulus divider to select between at least a first divider ratio and a second divider ratio;a pseudo-random noise generator that generates a pseudo-random sequence for input into the accumulator wherein the pseudo-random noise generator is a zero-mean pseudo-random noise generator or a non-zero-mean pseudo-random noise generator; anda programmable delay generator comprising a delay control circuit that receives at least said overflow value and said delay value and calculates a delay time for application to each pulse in the intermediate signal with the adjusted frequency to provide an output signal with a final adjusted frequency (fout).

2. The frequency synthesizer of claim 1 wherein said multi-modulus divider selects between a first divider ratio, a second divider ratio and a third divider ratio.

3. The frequency synthesizer of claim 1 wherein the accumulator increment is in the range of 0 to 2NA−1 where NA is the number of bits in an accumulator value A output from the accumulator.

4. The frequency synthesizer of claim 3 wherein the numerically controlled oscillator latch circuit comprises at least NA switching elements to latch the accumulator value.

5. The frequency synthesizer of claim 4 wherein the value of A is latched at an average frequency of fOUT or at the adjusted frequency.

6. The frequency synthesizer of claim 4 wherein the latch circuit comprises at least one additional switching element for latching at least one overflow bit from the accumulator.

7. The frequency synthesizer of claim 3 wherein the delay value is at least some portion of the accumulator value.

8. The frequency synthesizer of claim 7 wherein the delay value has a number of bits ND and wherein NA≧ND.

9. The frequency synthesizer of claim 8 further comprising an arithmetic circuit that provides an accumulator increment K to the numerically controlled oscillator

10. The frequency synthesizer of claim 9 wherein the accumulator increment is the sum of the output from the non-zero-mean pseudo-random number generator and the most significant bits of a tuning increment.

11. The frequency synthesizer of claim 1 wherein the pseudo-random noise generator is a non-zero-mean pseudo-random noise generator and wherein the non-zero-mean pseudo-random noise generator induces the numerically controlled oscillator to output a phase-dithered delay value.

12. The frequency synthesizer of claim 11 wherein the non-zero-mean pseudo-random noise generator further comprises a digital ΔΣ modulator.

13. The frequency synthesizer of claim 12, wherein the non-zero-mean pseudo-random noise generator outputs a binary pseudo-random sequence.

14. The frequency synthesizer of claim 13 further comprising a dither control circuit that enables and disables the non-zero-mean pseudo-random noise generator.

15. The frequency synthesizer of claim 14 wherein the dither control circuit controls a multiplexer to select between a tuning word dithered by the non-zero-mean pseudo-random noise generator and a tuning word not dithered by the non-zero-mean pseudo-random noise generator.

16. The frequency synthesizer of claim 1 wherein the non-zero-mean pseudo-random noise generator is integrated with the numerically controlled oscillator.

17. The frequency synthesizer of claim 1 wherein a spectral shape of the pseudo-random noise output by the pseudo-random noise generator is selected to reduce the magnitude of spurious tones of the output signal at specific frequencies.

18. A frequency synthesizer comprising: an input means for receiving a clock reference signal at a first input frequency;a multi-modulus divider means for dividing the input frequency to provide an intermediate signal with an adjusted frequency;a numerically controlled oscillator means comprising an accumulator receiving an accumulator increment value for providing a phase value and a latch circuit that receives and is clocked by the intermediate signal with the adjusted frequency wherein the numerically controlled oscillator outputs a delay value and an overflow signal comprised of one or more bits wherein said overflow signal is provided to said multi-modulus divider to select between at least a first divider ratio and a second divider ratio;a pseudo-random noise generator that generates a pseudo-random sequence for input into the accumulator wherein the pseudo-random noise generator is a zero-mean pseudo-random noise generator or a non-zero-mean pseudo-random noise generator; anda programmable delay generator means comprising a delay control which receives at least said overflow value and said delay value and calculates a delay time for application to each pulse in the intermediate signal to provide an output signal with a final adjusted frequency (fout).

19. The frequency synthesizer of claim 18 wherein said multi-modulus divider selects between a first divider ratio, a second divider ratio and a third divider ratio.

20. The frequency synthesizer of claim 18 wherein the pseudo-random noise generator is a non-zero-mean pseudo-random noise generator and wherein the frequency synthesizer further comprises a dither control circuit that enables and disables the non-zero-mean pseudo-random noise generator.

21. The frequency synthesizer of claim of claim 20 wherein the non-zero-mean pseudo-random noise generator outputs a binary non-zero-mean binary sequence.